Second Year – CIS

Course Teacher: Zareen Sadiq

CS-220 DIGITAL LOGIC DESIGN

PRACTICE PROBLEMS

Combinational & Sequential Logic

Instructions: 1. Some questions refer to specific ICs. You need to look up their pin configurations and
explanations in the TTL databook. The hardcopy of databook is available in DDL Lab. You can
also find it on internet.
2. Problem # 4, 5 and 6 are related to sequential circuits, you will be able to solve them once we
finish that topic.
u v w Operation
0 0 1 AND
1. There are five inputs to a logic circuit: a, b, u, v and w. Inputs a and b represent two
0 1 0 OR
binary bits. The inputs u, v and w specify the logic operation to be performed on a and b.
the output line y is the result of the operation performed on a and b. The logic operation 0 1 1 NAND
are represented by the codes given in table 1. Design logic circuit to produce y using an 8 1 0 1 NOR
x 1 multiplexer and individual AND, OR, NAND, NOR, XOR and XNOR gates. The 1 1 0 XOR
output should be zero in case of invalid operation selection. 1 1 1 XNOR
Table 1
2. A circuit consists of two parts: one compares two numbers A and B (each of 4-bits) and
the other transfers the 4 bits of the larger number to the output. Implement it using one 4-bit magnitude comparator IC (7485), one
quad 2x1 multiplexer IC (74157) and external gates if required.

3. A 74148 octal to binary priority encoder takes input from an octal keypad with active low outputs The keypad has eight output
pins, each representing an octal digit from 0 to 7. Output of 74148 is fed into 7447 BCD to 7 segment decoder, which in turn
drives a common cathode display. The display shows the digit selected through the keypad and should remain off if no key is
pressed. Show the required connections using components given in figure 1. You may use any additional gates if needed.
74148 - Octal to Binary 7447 – BCD to Seven Seven
Keypad Priority Encoder Segment Decoder Segment
Display
E1 Vcc LT Vcc a b c d
0 1 2
BI
3 4 5 0 GS RBI OA
1 E0 OB
6 7 2 D OC
3 A2 C OD
4 A1 B OE
5 A0 A OF
0 1 2 3 4 5 6 7
6 OG e f g
7 GND GND common
Figure 1 7 GND

4. Design a MOD 4 counter using 7473 IC. The output of the counter is to be displayed on a common anode 7-segment display via
7447 IC. Assume that external clock signal is available to drive the counter.

5. For figure 3, answer the following questions. Assume the counter 7490 is initially RESET.
i. What is the MOD of the given counter?
ii. For how many counts / pulses red LED will be ON?
iii. For how many counts / pulses yellow LED will be ON?
iv. For how many counts / pulses green LED will be ON?
v. For how many counts / pulses blue LED will be ON?
vi. Which LED will be ON when the count value is 9?
vii. Which LED will be ON if R91 and R92 are connected to Vcc?
viii. Which two LEDs can be turned ON simultaneously?
 From clock 7490 74138
source Red LED
CLKA CLKB A D0
B D1
QA C D2 Yellow LED
QB D3
QC D4 Green LED
QD Vcc G1 D5
G2A’ D6
Gnd R91 R01 G2B’ D7 Blue LED
R92 R02
Gnd

Figure 3
6. Consider the circuit given in figure 4. The encoder used is a decimal to BCD priority encoder with active high inputs (1 through
9) and active high outputs (A, B, C, D with D being the MSB). The registers used are 74194 bidirectional universal shift registers
(see figure 8.b).
i. In what mode the given two registers are operated: serial or parallel?
ii. Explain how the positive edge is provided to the clocks of the two registers.
iii. Assuming the registers are initially reset, what would be stored in the two registers if input 7 of encoder goes high, provided all
other inputs are kept low?
iv. Assuming the same state (as held after part iii) and input 7 restored back to low, what would be stored in the two registers if input
3 of the encoder goes high, provided all other inputs are kept low?
v. At any stage, if 1 is applied at SL of register 1, what difference would it make?

D
C
1 B
2 A 0 0 1 1 1 0 0 1 1 1
3
4 Priority
5 Encoder A B C D SR SL CLR S1 S0 A B C D SR SL CLR S1 S0
6
7 Vcc 74194 (Register 1) 74194 (Register 2)
8 GND
9 CLK QA QB QC QD Vcc GND CLK QA QB QC QD Vcc GND

Figure 4