Interrupts

MODULE 4
Embedded Design – PCB Considerations

2
Atmega16 Interrupts
 Interrupts
◼ Atmega16 has 3 external interrupts and 17 internal
interrupts (and RESET)

Interrupt Vector Table

◼ For every interrupt there is an Interrupt service routine

or Interrupt Handler
◼ For every interrupt there is a fixed location in memory
that holds the address of its ISR
◼ The group of memory locations set aside to hold the

addresses of ISR is called interrupt vector table

◼ The complete list of vectors is shown in a table on next
slide

More Details on Page 11 and Page 42 of Datasheet

Atmega16 – Interrupt Pins
 Interrupt Enabling
◼ Enable global interrupt bit
◼ Enable local interrupt bit
◼ Mode selection, edge trigger etc
◼ Interrupt Flags
 Registers Associated with Interrupts
◼ Status Register - (SREG) [Enable global int]
◼ General Interrupt Control Register – GICR [Enable local int]
◼ MCU Control Register - (MCUCR) [Interrupt Sense Control
0,1 (mode selection, edge trigger etc)]
 Registers Associated with Interrupts
◼ MCU Control and Status Register – MCUCSR
[ Int Sense control 2, (mode selection, edge trigger etc)]

◼ General Interrupt Flag Register – GIFR

 Programming Steps:
For programming an interrupt, the following steps
must be followed:
◼ Initialize the interrupt by appropriately configuring
the MCUCR, MCUCSR and GICR registers.
◼ Clear Interrupt Flags in GIFR register

◼ Set Global Interrupt Enable bit in SREG register.

◼ Define the appropriate Interrupt Service Routine

(ISR) for the interrupt. e.g. ISR for INT0 can be

written as follows:
ISR (INT0_vect)
{
}
 Steps in Executing an interrupt
◼ It finishes the instruction it is currently executing and
saves the address of the next instruction on the stack
◼ It jumps to the fix location in memory called the
interrupt vector table. The interrupt vector table directs
microcontroller to the address of interrupt service
routine (ISR).
◼ The microcontroller starts to execute the interrupt
service routine until it reaches the last instruction of the
subroutine, which is return from interrupt
◼ Upon execution of return from interrupt instruction, the
microcontroller returns to the place where it was
interrupted. First it gets the program address from the
stack. Then it starts to execute that address
More Details on Page 11 and Page 42 of Datasheet
 Role of Status Register (SREG)

◼ Upon reset, all interrupts are disabled .

◼ The interrupts will be enabled by the software. The bit D7(I-
bit) of the SREG (Status Register) register is responsible for
enabling and disabling the interrupts globally.
◼ If I-bit = 1, each interrupt is enabled by setting to HIGH,
the interrupt enable bit for that interrupt
Interrupt Priority (interrupts occur in same cycle)

◼ If the two interrupts occur at the same time (same cycle)

than the one with the higher priority (as per polling
sequence) is served first
◼ The priority of each interrupt is related to its address in
interrupt vector table
◼ The interrupt which has a lower address has a higher
priority

More Details on Page 11 and Page 42 of Datasheet

Polling Sequence
Polling Sequence

L
 External Interrupts
The External Interrupts are triggered by the INT0 (PD2),
INT1(PD3), and INT2 (PB2) pins

INT0 and INT1

◼ The external interrupts can be triggered by a falling or
rising edge or any logical change or a low level

INT2
◼ It is only edge triggered

More Details on Page 64 of Datasheet

 Registers Associated with Interrupts
◼ General Interrupt Control Register – GICR

◼ Bit 7 – INT1: External Interrupt Request 1 Enable

◼ When the INT1 bit is set (one) the external pin

interrupt 1 is enabled
◼ The corresponding interrupt of External Interrupt

Request 1 is executed from the INT1 interrupt

Vector

More Details on Page 65 of Datasheet

 External Interrupts Registers
◼ Bit 6 – INT0: External Interrupt Request 0 Enable
◼ When the INT0 bit is set (one) the external pin interrupt 0 is
enabled
◼ The corresponding interrupt of External Interrupt Request 0
is executed from the INT0 interrupt Vector

◼ Bit 5 – INT2: External Interrupt Request 2 Enable

◼ When the INT2 bit is set (one) the external pin interrupt 2 is
enabled
◼ The corresponding interrupt of External Interrupt Request 2
is executed from the INT2 interrupt Vector
 External Interrupts Registers
◼ MCU Control Register (MCUCR)
Last four bits of this register controls the mode of external interrupt
0 and 1

◼ Bit 3, 2 – ISC11, ISC10: Interrupt Sense Control 1 Bit 1

and Bit 0 (Interrupt 1 Sense control)

More Details on Page 64 of Datasheet

 External Interrupts Registers
◼ Bit 1, 0 – ISC01, ISC00: Interrupt Sense Control 0 Bit
1 and Bit 0 (Interrupt 0 sense control)
 External Interrupts Registers
◼ MCU Control and Status Register – MCUCSR
◼ Bit-6 of this register controls the mode of interrupt 2

◼ If ISC2 is written to zero, a falling edge on INT2 activates the

interrupt
◼ If ISC2 is written to one, a rising edge on INT2 activates the
interrupt
 External Interrupts Registers
◼ For Interrupt 0
◼ Set the SREG bit-I
◼ Set the INT0 pin of GICR
◼ Select its mode by setting bits ICS01 and ICS00
of MCUCR accordingly
◼ For Interrupt 1
◼ Set the SREG bit-I
◼ Set the INT1 pin of GICR
◼ Select its mode by setting bits ICS11 and ICS10
of MCUCR accordingly
 External Interrupts Registers

◼ For Interrupt 2
◼ Set the SREG bit-I
◼ Set the INT2 pin of GICR
◼ Select its mode by setting bit ISC2 of MCUCSR
accordingly
 External Interrupts Flags Register

◼ General Interrupt Flag Register – GIFR

◼ Bit 7 – INTF1: External Interrupt Flag 1

◼ When an edge or logic change on the INT1 pin triggers an
interrupt request, INTF1 becomes set (one)
◼ If the I-bit in SREG and the INT1 bit in GICR are set (one), the
MCU will jump to the corresponding Interrupt Vector
◼ The flag is cleared when the interrupt routine is executed
◼ Alternatively, the flag can be cleared by writing a logical one to
it
 External Interrupts Flags Register

◼ Bit 6 – INTF0: External Interrupt Flag 0

◼ When an edge or logic change on the INT0 pin triggers an
interrupt request, INTF0 becomes set (one)
◼ If the I-bit in SREG and the INT0 bit in GICR are set (one), the
MCU will jump to the corresponding Interrupt Vector
◼ The flag is cleared when the interrupt routine is executed
◼ Alternatively, the flag can be cleared by writing a logical one to it
 External Interrupts Flags Register

◼ Bit 5 – INTF2: External Interrupt Flag 2

◼ When a rising or falling edge on the INT2 pin triggers an
interrupt request, INTF2 becomes set (one)
◼ If the I-bit in SREG and the INT2 bit in GICR are set (one), the
MCU will jump to the corresponding Interrupt Vector
◼ The flag is cleared when the interrupt routine is executed
◼ Alternatively, the flag can be cleared by writing a logical one to
it
 Important
◼ The interrupts will trigger even if the interrupt pins are
configured as OUTPUT
◼ The Flag of an interrupt can be cleared by writing
Logic One to it.
 Interrupt Flag Bit
Flag Bit (GIFR) Value to be written Result
0 1 0
1 1 0
0 0 0
1 0 1
 Interrupts Programming in C
◼ Interrupt Include file
Interrupt header file should be included if we want to
use an interrupt in our program. Following command is
used
#include<avr/interrupt.h>

◼ cli() and sei()

Since for enabling an interrupt we need to enable I-bit
in SREG. And AVR GCC/WinAVR does not allow us to
access a bit, so to clear or set I-bit either we have to use
bit wise AND(&) or (|) operator or we can use the cli() and
sei() macros to do the same task
interrupts() -> sei() [SEt Interrupt ]
noInterrupts() -> cli() [CLear Interrupt]
 Interrupts Programming in C
◼ Defining ISR
To write an ISR for an interrupt we use the following
structure:
ISR(interrupt vector name)
{
// user code here
}

For interrupt vector name use the ISR names given in the
table on next slides; for example for external interrupt0
ISR(INT0_vect)
{
}
 Vector Names for WinAVR(AVR GCC)
External interrupt 0 INT0_vect
External interrupt 1 INT1_vect
External interrupt 2 INT2_vect
ADC Conversion Complete ADC_vect
Analog Comparator ANA_COMP_vect
Serial Transfer Complete SPI_STC_vect
Store Program Memory Ready SPM_RDY_vect
Timer/Counter0 Compare Match TIMER0_COMP_vect
Timer/Counter0 Overflow TIMER0_OVF_vect
Timer/Counter Capture Event TIMER1_CAPT_vect
Timer/Counter1 Compare Match A TIMER1_COMPA_vect
Timer/Counter1 Compare MatchB TIMER1_COMPB_vect
Timer/Counter1 Overflow TIMER1_OVF_vect

Complete table available at : http://www.nongnu.org/avr-libc/user-manual/group__avr__interrupts.html

 Example
Write a program which
◼ Displays the value of a variable ‘x’ on PORT A,

◼ Initial value of x=0

◼ Value of variable ‘x’ increments whenever there is a high to

low pulse on pin INT1

 Example
#include <avr/io.h>
#include <avr/interrupt.h>
unsigned char x=0;
void main()
{ DDRA =0xFF; //Configures port A as output
DDRD &=0b11110111; //configure bit4 of port D as input (INT1)
MCUCR |=(0<<ISC10 | 1<<ISC11); //selecting mode of interrupt 1 = rising edge
GIFR |=0b10000000; // Clear Int Flag
GICR |=0b10000000; //Enabling Interrupt 1 Either one of
sei(); //or these could be
//SREG=SREG|0b10000000; //Enabling Global Interrupt used to
while(1) enable I-bit
{
PORTA=x; //continuously outputs x
}
}
ISR(INT1_vect)
{ x++;
• Int_inc_x.c
}
• Int.isis
Interrupt within Interrupt
◼ When an interrupt occurs, the Global Interrupt Enable
I-bit is cleared hence no other interrupt will interrupt this
ISR.
◼ The I-bit is automatically set when a Return from
Interrupt instruction is executed
◼ While executing an ISR if any interrupt occurs it will be
latched since I-bit is disabled and will be served after
completion of current ISR
◼ If more than one interrupt occurs during an ISR, they
will be served according to the Polling sequence.

• Int_nested.c
More Details on Page 11 and Page 42 of Datasheet • Case 1
 Nested Interrupts
What will happen if we set I bit of SREG in ISR ?
◼ This will allow all enabled interrupts to interrupt this ISR.
◼ If the I bit of SREG is set in an ISR and another interrupt
occurs, the controller will finish the currently executing
instruction and then serve the interrupt that occurs. After
serving that interrupt it will return to this ISR.
◼ Since this ISR can be interrupted by all other enabled
interrupts, this interrupt has lower priority in comparison
to the other interrupts. But this priority is user defined
and depends on the user’s preferences.

Int_nested.c
More Details on Page 11 and Page 42 of Datasheet Case 2
 Nested Interrupt - Example
void main ()
{
DDRA=0xFF;
DDRC=0xFF;
PORTA=0;
PORTC=0;

MCUCSR|=0x40;//INT2 CONFIGURED FOR RISING EDGE

MCUCR|=0x0F;//INT0 AND INT1 CONFIGURED FOR RISING EDGE
GICR|=0xE0;
//GIFR|=0xE0;//CLEARING FLAGS OF INT0,INT1 AND INT2
SREG|=0x80;

while(1)
{
DDRD=0xFF;
DDRB=0xFF;
PORTB=0;
PORTD=0;
PORTD=0x04;
}
}
 Nested Interrupt - Example
ISR(INT0_vect)
{
SREG|=0x80;
PORTA=0x06;
PORTD=0;
PORTD=0x08;
}

ISR(INT1_vect)
{
SREG|=0x80;
PORTC=0x05;
PORTB=0;
PORTB=0x04;
}

ISR(INT2_vect)
{
SREG|=0x80;
PORTC|=0xF0;
PORTA|=0x50;
}
Can interrupts occur while I bit of SREG is
disabled?
◼ Interrupts events (that is, noticing the event) can occur at
any time, and most are remembered by setting an "interrupt
event" flag (GICR, local int enable) inside the processor. If
interrupts are disabled (SREG, global int enable), then that
interrupt will be handled when they are enabled again, in
priority order (polling sequence).
while(1)
{ PORTB=0;
PORTD=0;
cli(); // Disables Interrupt
PORTD=0x04; // calling INT 0
x++;
x++;
sei(); // Enables Interrupt
x++;
Int_nested.c
} Case 3
Thank You