CSA 14752

SR Flip Flop:
1: Set Condition of SR Flip Flop

NOR

NOR

2: Re-Set Condition of SR Flip Flop

NOR

NOR

3: Clock off Condition of SR Flip Flop

NOR

NOR
CSA 14752

D Flip Flop:
1: Set Condition of D Flip Flop

2: Re-Set Condition of D Flip Flop

CSA 14752

JK Flip Flop:

1: Set Condition of JK Flip Flop

2: Re-Set Condition of JK Flip Flop

CSA 14752

HALF ADDER:

FULL ADDER:
CSA 14752

4 By 1 Multiplexer:

 S1=S0= 0, Y0 AND gate is selected by the complement inputs :

 S1=S0= 1, Y3 AND gate is selected by the complement inputs :

CSA 14752

8 By 1 Multiplexer:

 S2=S1=S0= 0, Y7 AND gate is selected by the complement inputs:

CSA 14752

 S2=S1=S0= 1, Y0 AND gate is selected by the complement inputs:

CSA 14752

1 to 4 DeMultiplexer:
CL Selection Lines Output Lines
K
/ S1 S0 Y3 Y2 Y1 Y0
1 0 0 0 0 0 1
1 0 1 0 0 1 0
1 1 0 0 1 0 0
1 1 1 1 0 0 0

 S1=S0= 0, Y0 AND gate is selected by the complement inputs:

CSA 14752

 S1=S0= 1, Y3 is selected by the complement inputs:

CSA 14752

1 to 8 DeMultiplexer:

CLK Selection Lines Output Lines

/ S2 S1 S0 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0
1 0 0 0 0 0 0 0 0 0 0 1
1 0 0 1 0 0 0 0 0 0 1 0
1 0 1 0 0 0 0 0 0 1 0 0
1 0 1 1 0 0 0 0 1 0 0 0
1 1 0 0 0 0 0 1 0 0 0 0
1 1 0 1 0 0 1 0 0 0 0 0
1 1 1 0 0 1 0 0 0 0 0 0
1 1 1 1 1 0 0 0 0 0 0 0
CSA 14752

 S2=S1=S0= 0, Y0 AND gate is selected by the complement inputs:

CSA 14752

 S2=S1=S0= 1, Y7 AND gate is selected by the complement inputs: