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P3939 [Total No. of Pages :2
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M.E. (E&TC) VLSI & Embedded Systems
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DIGITAL CMOS DESIGN
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(2017 Pattern) (Semester - I)
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Time : 3 Hours] [Max. Marks :50
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Instructions of the condidates:
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3) Neat diagrams must be drawn wherever necessary.
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4) Use of nonprogrammable calculator is allowed.
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Q1) a) With the help of diagram & typical dimensions, explain cross section of
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CMOS Inverter. Comment on the doping concentrations & poly silicon
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layer. [5]
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Q2) a) Derive the expression for power delay product. How is it useful to the
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designer? [5]
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Q3) a) Explore equivalent circuit of MOSFET. Explain the gm, Cgs & their
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significance. [4]
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sizing. [4]
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Q5) a) Draw a logic circuit involving dynamic hazards & explain the waveforms.
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b) Design five input CMOS NAND & NOR gates. Compare w.r.t.area,
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dissipation & delay. [4]
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c) Why hazards are not so serious in synchronous machines? [2]
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Q6) a) Design CMOS logic for P = ABCDE + F + G + H. Comment on area &
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propagation delay. [4]
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b) Draw FSM diagram & write HDL code for tea/coffee vending machine.
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c) Design 4:1 mux using transmission gates. Compare with conventional
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method. [2]
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Q7) a) What are merits of differential circuits? Explore sense amplifier based
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circuit in detail. [4]
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b) Compare at least three logic families in detail. [4]
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b) Explain in brief about materials involved in performance improvement.
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c) Write note on high speed design. [2]
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