ISSCC 2022 / SESSION 18 / DC-DC CONVERTERS / OVERVIEW

Session 18 Overview: DC-DC Converters

POWER MANAGEMENT SUBCOMMITTEE

Session Chair: Harish Krishnamurthy Session Co-Chairs: Xun Liu

Intel, Hillsboro, OR Chinese University of Hong Kong
Shenzhen, China

Power density, efficiency, and transient response have always been the key performance metrics used to measure modern DC-DC converters that are used for
powering various applications such as multi-core microprocessors, energy harvesting and direct battery-attached systems, automotive electronics, and LED
drivers. Novel topologies with high voltage-conversion ratios while minimizing inductor current, maximizing inductor slew rate for faster transient response,
and maintaining high power-conversion efficiency are introduced in this session. Fully integrated power converters for maximum power density and alternative
techniques to sense inductor current in traditional buck converters are also presented in this session for showcasing the latest DC-DC converter designs at both
system and circuit levels.

8:30 AM
18.1 A 1.23W/mm2 83.7%-Efficiency 400MHz 6-Phase Fully Integrated Buck Converter in 28nm CMOS with On-Chip
Capacitor Dynamic Re-Allocation for Inter-Inductor Current Balancing and Fast DVS of 75mV/ns
Jeong-Hyun Cho, KAIST, Daejeon, Korea
In Paper 18.1, KAIST and Samsung Electronics present a high-power density (1.23 W/mm2), high efficiency (~83%), 400MHz 6-phase
fully integrated buck converter in 28nm CMOS with on-chip capacitor dynamic reallocation for inductor current sensing and current
balancing while achieving fast DVS of 75mV/ns.

8:40 AM
18.2 A 12V/24V-to-1V DSD Power Converter with 56mV Droop and 0.9µs 1% Settling Time for a 3A/20ns Load
Transient
Jingyi Yuan, University of Science and Technology of China, Hefei, China
In Paper 18.2, the University of Science and Technology of China presents a double step-down (DSD) DC-DC converter with dual phase
charging that improves the inductor slew rate by 2× to minimize droop (56mV) for a 3A/20ns load transient.

296 • 2022 IEEE International Solid-State Circuits Conference 978-1-6654-2800-2/22/$31.00 ©2022 IEEE
 ISSCC 2022 / February 23, 2022 / 8:30 AM

8:50 AM
18.3 A 4A 12-to-1 Flying Capacitor Cross-Connected DC-DC Converter with Inserted D>0.5 Control Achieving >2×
Transient Inductor Current Slew Rate and 0.73× Theoretical Minimum Output Undershoot of DSD
Tingxu Hu, University of Macau, Macau, China
In Paper 18.3, the University of Macau and the University of Lisboa overcome the limitation of D<0.5 in DSD DC-DC converters and
reliability issues when D>0.5 by proposing a capacitor cross-connected DSD which in conjunction with a hysteretic controller improves
the droop to 0.73× of the theoretical minimum while improving the DVS rate by 1.3×.

9:00 AM
18.4 A Monolithic 3:1 Resonant Dickson Converter with Variable Regulation and Magnetic-Based Zero-Current
Detection and Autotuning
Prescott H. McLaughlin, Dartmouth College, Hanover, NH
In Paper 18.4, Dartmouth College presents a fully integrated 3:1 step-down resonant Dickson converter which achieves 78.3% efficiency
for 4.2-to-1.2V step down at 140mW. The design uses a merged electromagnetic LC resonator to reduce high-frequency winding loss
effects and improve utilization of spiral magnetics.

9:10 AM
18.5 A 12A Imax, Fully Integrated Multi-Phase Voltage Regulator with 91.5% Peak Efficiency at 1.8 to 1V, Operating
at 50MHz and Featuring a Digitally Assisted Controller with Automatic Phase Shedding and Soft Switching in
4nm Class FinFET CMOS
Christopher Schaef, Intel, Hillsboro, OR
In Paper 18.5, Intel presents a 4-phase fully integrated voltage regulator (FIVR) in 7nm CMOS delivering up to 12A load current with
a current density of 47 A/mm2 and featuring a digitally assisted control loop that allows autonomous phase shedding (APS) while
retaining fast transient response.

18
9:20 AM
18.6 A 5V Input 98.4% Peak Efficiency Reconfigurable Capacitive-Sigma Converter with Greater than 90% Peak
Efficiency for the Entire 0.4~1.2V Output Range
Xu Yang, Zhejiang University, Hangzhou, China
In Paper 18.6, Zhejiang University presents a high efficiency 98.4% peak efficiency, 5V input 0.4-to-1.2V output reconfigurable
capacitive-sigma converter. This work connects an unregulated 2:1 switched capacitor in input-series and output-shunt configuration
with a reconfigurable hybrid Dickson buck converter to interface with higher voltages while minimizing current through the output
inductor and improving the overall efficiency.

9:30 AM
18.7 A 2−5MHz Multiple DC Output Hybrid Boost Converter with Scalable CR Boosting Scheme Achieving 91%
Efficiency at a Conversion Ratio of 12
Chen Chen, University of Texas at Dallas, Richardson, TX
In Paper 18.7, the University of Texas at Dallas presents a hybrid boost converter topology with a scalable N-stage conversion ratio
(CR) boosting scheme to enlarge the minimum switch on-time, provide N DC outputs, and reduce switch VDS stress as well as capacitor
voltage. The 4-stage converter produces 4 outputs and achieves peak efficiencies of 91% at CR = 12 and fSW = 2MHz and 87% at
CR = 10 and fSW = 5MHz.

9:40 AM
18.8 A Battery-Input Sub-1V Output 92.9% Peak Efficiency 0.3A/mm2 Current Density Hybrid SC-Parallel-Inductor
Buck Converter with Reduced Inductor Current in 65nm CMOS
Guigang Cai, University of Macau, Macau, China
In Paper 18.8, the University of Macau and the University of Lisboa present an SC-parallel-inductor buck (SCPL-Buck) topology that
can significantly reduce inductor current to <0.5× of Iload, reducing the conduction losses by over 75% for the same DCR, facilitating
a peak efficiency of 92.9% for a 4.2V input voltage system.

DIGEST OF TECHNICAL PAPERS • 297

ISSCC 2022 / SESSION 18 / DC-DC CONVERTERS / 18.1
18.1 A 1.23W/mm2 83.7%-Efficiency 400MHz 6-Phase Fully
Integrated Buck Converter in 28nm CMOS with On-Chip
Capacitor Dynamic Re-Allocation for Inter-Inductor Current
Balancing and Fast DVS of 75mV/ns
Jeong-Hyun Cho1, Dong-Kyu Kim1, Hong-Hyun Bae1, Yong-Jin Lee1,2,
Seok-Tae Koh1, Younghwan Choo2, Ji-Seon Paek2, Hyun-Sik Kim1
1
KAIST, Daejeon, Korea
2
Samsung Electronics, Hwaseong, Korea
For more efficient power management in processors, a high-frequency and multi-phase
(MP) integrated voltage regulator (IVR) using multiple inductors would be an ideal
solution to deliver optimized power with rapid dynamic voltage scaling (DVS) [1-5].
Nevertheless, in practical use, MP-IVRs suffer from an inter-inductor current imbalance
because of mismatches in integrated inductances, different parasitic resistances, and
duty-control skews among all phases (top of Fig. 18.1.1). Such a current mismatch may
cause larger output ripple and efficiency degradation, losing the benefits of multi-phase
operation. Also, thermal hotspots can occur due to excessive current density and
deteriorate reliability. Previous approaches [2,4] use current sensors to calibrate the duty
cycle of each phase, but the design complexity and power overhead tend to be greatly
increased in the high-speed sensing circuitry for fast-switching converters. An additional
consideration in MP-IVRs is the phase-shedding technique, which can improve the light-
load efficiency by reducing the number of phases. In many prior works [1,2], the number
of phases was adjusted by 2N (e.g., 1-2-4) for simplicity of phase division. If the phase-
shedding is more fine-grained, the overall efficiency can be more flattened over a wide
range of loads. Moreover, because the frequency response and output ripple vary
according to the number of phases, the MP-IVR should be adaptively optimized further
for them. This paper presents a 400MHz 6-phase fully integrated buck converter (bottom
of Fig. 18.1.1). Key contributions of this work include 1) inter-inductor true-average-
current matching by the flying-capacitor-based peak-and-valley differential sensing
(PVDS) technique with near-zero power overhead, 2) area-efficient dynamic re-allocation
of on-chip capacitors used either in the PVDS or at the output for optimizing
responsiveness and voltage ripple adaptively to the number of phases, and 3) DLL-based
multi-phase clock generation (MPCG) for fine-grained phase-shedding functionality,
improving efficiency over a wide load range.
Figure 18.1.2 shows the proposed inter-inductor current balancing scheme employing
the flying-capacitor-based PVDS. To detect the mismatch between two inductor currents
(IL1 and IL2), each of inductors L1 and L2 shortly de-magnetizes with a flying capacitor CF
using ΦB1 and ΦB2, respectively, immediately after the on-duty phase (ΦP1 and ΦP2). The
remaining off-duty phase for L1 (L2) is then finalized by ΦN1 (ΦN2). During such a switching
cycle, the peak current (IL1P) of IL1 is accumulated on CF during ΦB1, and the IL2 peak (IL2P)
is also integrated on CF with the opposite direction at ΦB2 (having the same duration as
ΦB1); this is a CF-based peak differential sensing (PDS). If IL2P is identical to IL1P, the flying-
capacitor voltage VCF will stay at zero after the pair of ΦB1 and ΦB2 is performed. On the
other hand, if IL2P > IL1P (IL2P < IL1P), VCF continues to increase (decrease) positively
(negatively) as the pair of ΦB1 and ΦB2 repeats. In the same manner, valley differential
sensing (VDS) de-energizes L1 and L2 with CF at the end of ΦN1 and ΦN2, respectively, and
thus can decide which of the two valley currents (IL1V and IL2V) is higher or lower by
monitoring VCF. Therefore, CF-based PVDS combining PDS and VDS is capable of
comparing the true-averages of IL1 and IL2 even with different inductances of L1 and L2.
The proposed 6-phase buck converter regulates the output (VOUT) using voltage-mode
control. The master duty cycle (D1) for L1 is generated according to the frequency-
compensated error signal VC1 (= Type-I compensator’s output). The slave duty cycles
(D2 to D6) for the L2 to L6 phases are determined by VC2 to VC6, which are modulated
around VC1 for the current-imbalance correction. In detail, VCN is defined as the sum of
VC1 and VKN (across CKN), and the voltage VKN is adjusted by using a Gm-cell and CKN
depending on VCF that containins information about the mismatch with IL1. For instance,
if IL2 > IL1, VCF will be increased by PVDS, and subsequently, non-zero VK2 (= VC1 – VC2)
will be formed to correct the mismatch between IL1 and IL2. When IL1 and IL2 become
identical with increasing D1 and reducing D2, VK2 settles down in conjunction with
VCF = 0. The bottom of Fig. 18.1.2 shows an example of the process in which the
mismatch among IL1 to IL3 is compensated for, assuming a 3-phase operation. First, the
current IL2 is corrected (increased) to be identical to IL1. During this time, both IL1 and IL3,
which are dominated by the master VC1, are then slightly reduced to satisfy ILOAD = IL1 +
IL2 + IL3 owing to the converter’s regulation capability. Next, the current-balancing between
IL1 and IL3 is performed by adjusting VK3. Still, IL1 and IL2 are in balance even when
correcting IL3 due to the previous calibration of VK2. Finally, the average currents of all
phases are matched while evenly supplying ILOAD without significant power overhead. The
PVDS sparsely operates only once out of 8 cycles.
Figure 18.1.3 shows the dynamic re-allocation of on-chip capacitors to optimize AC-
dynamics (frequency response) of the power stage while keeping the output ripple
(ΔVOUT) constant. Under light loads, 1-phase operation can be more energy efficient, but
it increases the ripple of its supplying current (IOUT); thus, a large output capacitor (CO)
298 • 2022 IEEE International Solid-State Circuits Conference
is required to restrain ΔVOUT. On the contrary, if the load becomes heavier or requires a
faster response, it is more efficient to supply IOUT with multiple phases, also lowering the
ripple of IOUT. Accordingly, in multi-phase operations, a smaller CO can be sufficient to
achieve the acceptable ΔVOUT. However, an excessive CO, set based on 1-phase mode,
may deteriorate the responsiveness of the MP converter. The key idea of this work is to
re-allocate on-chip CO adaptively to the number of phases and re-use the surplus CO as
a flying-capacitor CF in PVDS. Note that CF is not required in 1-phase mode. If the CO is
adjusted for a constant ΔVOUT regardless of the number of phases, the LC-pole frequency
(ωO) of the 6-phase mode can be moved up to 5× higher than the fixed CO, thereby
bringing a faster transient response. Also, the capacitor (CC) of the Type-I compensator,
determining the dominant pole, is variably controlled to be optimal for ωO. The bottom-
left of Fig. 18.1.3 shows the ILOAD-estimation utilized for phase-shedding. When every
PDS or VDS works, the instantaneous ΔVCF across CF can be observed due to the current
flow of IL, which is proportional to ILOAD. The ILOAD-estimator accumulates the ΔVCF into
VINTG by a preset number of times (with RST) and determines whether to increment,
decrement, or keep the number of phases (N) by comparing VINTG with boundaries (VH
and VL).
Figure 18.1.4 shows the DLL-based MPCG for fine-grained phase-shedding functionality.
It divides multiple phases evenly within a reference clock (OSCREF) cycle. Thus, the time
delay (di) between OSCi-1 and OSCi, which are outputs of the voltage-controlled delay line
(VCDL), should be ideally equal to di = TS / N, where TS and N are the cycle period and the
number of phases, respectively. The proposed DLL converts di into a DC-voltage (Vdi)
using a low-pass filter (RLF and CLF). For example, the Vdi will become VDD if di occupies
100% of the duty cycle (TS) of OSCREF. Then, VCTRL dominating VCDL is adjusted so that
the total sum VdSUM (= Vd1 + Vd2 + … + VdN) is equal to VDD. Because VDD equivalently
indicates TS, multiple phases equally divided by N are achievable (di = TS / N). However,
when the total summed delay is higher than TS, the over-delay cannot be expressed due
to the limited supply voltage of VDD. To resolve this problem, the proposed DLL actually
acquires VdSUM during 2·TS with a 0.5×-lowered frequency and compares it with 0.5·VDD
to control VCTRL. To perform the phase-shedding (e.g., 6-phase → 5-phase), the di signal
is selectively masked to be disabled. Unlike a conventional DLL that has multiple operating
points, the proposed DLL can be guaranteed to be locked by virtue of mapping one TS to
be the supply voltage of VDD. (Note that the available VdSUM is strictly limited to up to VDD)
The proposed fully integrated buck converter using bonding-wire inductors (6×1nH) was
fabricated in 28nm CMOS (Fig. 18.1.7). It operates at 6×400MHz in 6-phase mode. The
top of Fig. 18.1.5 shows the measured waveforms of DVS transient responses with RLOAD
of 1Ω; the output tracks the reference voltage with DVS rates of 75mV/ns (rise) and
60mV/ns (fall). As shown in the middle of Fig. 18.1.5, for an on-chip load step of Δ1A
within 1ns, the droop and overshoot were measured to be 200mV with a recovery time
of 3 to 4ns in 6-phase mode (CO=200pF). When the phase-shedding was enabled, the
following load-transient responses (droop/recovery) were acquired: 300mV/14ns in
1-phase mode (CO=6nF) and 300mV/6ns in 2-phase mode (CO=2nF). The bottom of
Fig. 18.1.5, measured with inductors of 20nH, demonstrates the inter-inductor current
balancing; the current mismatch of 10mA was reduced to ≤1mA by the proposed PVDS.
Figure 18.1.6 shows the efficiency and performance summary. Peak efficiency of 83.7%
was measured at VOUT = 0.9V. Thanks to the fine-grained phase-shedding, any significant
drop or fluctuation could not be observed in the efficiency graph over a wide load range.
The proposed chip achieved a maximum power density of 1.23W/mm2, which is the
highest reported to date. Among the state-of-the-art designs listed in the table in
Fig. 18.1.6, the fastest DVS and load-transient responses were obtained in this work
while it offers highly competitive efficiency.
Acknowledgement:
This work was supported by Samsung Electronics Co., Ltd., Korea.
References:
[1] W. Kim et al., “A Fully-Integrated 3-Level DC-DC Converter for Nanosecond-Scale
DVFS,” IEEE JSSC, vol. 47, no. 1, pp. 206-219, Jan. 2012.
[2] C. Huang et al., “A 100 MHz 82.4% Efficiency Package-Bondwire Based Four-Phase
Fully-Integrated Buck Converter With Flying Capacitor for Area Reduction,” IEEE
JSSC, vol. 48, no. 12, pp. 2977-2988, Dec. 2013.
[3] C. Wang et al., “A Two-Phase Three-Level DC-DC Buck Converter with Cross-
Connected Flying Capacitors for Inductor Current Balancing,” IEEE Trans. Power
Electronics, vol. 36, no. 12, pp. 13855-13866, Dec. 2021.
[4] N. Desai et al., “Peak-Current-Controlled Ganged Integrated High Frequency Buck
Voltage Regulators in 22nm CMOS for Robust Cross-Tile Current Sharing,” ISSCC, pp.
262-263, Feb. 2021.
[5] A. Novello et al., “A 1.25GHz Fully Integrated DC-DC Converter Using
Electromagnetically Coupled Class-D LC Oscillators,” ISSCC, pp. 260-261, Feb. 2021.
[6] N. Tang et al., “Fully Integrated Buck Converter with 78% Efficiency at 365mW Output
Power Enabled by Switched-Inductor-Capacitor Topology and Inductor Current Reduction
Technique,” ISSCC, pp. 152-153, Feb. 2019.
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Figure 18.1.1: The proposed multi-phase buck converter with on-chip capacitor- Figure 18.1.2: CF-based peak-and-valley differential sensing (PVDS) and correction
reused fully differential inter-inductor current balancing. mechanism of true-average-current mismatch between inductors.

18

Figure 18.1.3: Dynamic re-allocation of on-chip capacitors to optimize ripple ΔVOUT Figure 18.1.4: The proposed DLL-based multi-phase clock generation (MPCG) for
and responsiveness according to phase-shedding, and ILOAD estimator. fine-grained phase-shedding functionality.

Figure 18.1.5: Measured waveforms: VREF (DVS) tracking responses (top), load
transient responses (middle), and current-imbalance correction (bottom). Figure 18.1.6: Measured efficiency (top) and performance summary (bottom).

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Figure 18.1.7: Die micrograph with six bond-wire inductors.

• 2022 IEEE International Solid-State Circuits Conference 978-1-6654-2800-2/22/$31.00 ©2022 IEEE

ISSCC 2022 / SESSION 18 / DC-DC CONVERTERS / 18.2
18.2 A 12V/24V-to-1V DSD Power Converter with 56mV Droop and
0.9µs 1% Settling Time for a 3A/20ns Load Transient
Jingyi Yuan, Zeguo Liu, Feng Wu, Lin Cheng
University of Science and Technology of China, Hefei, China
12V/24V-to-1V power converters with high efficiency and fast transient responses are
highly desirable in industrial and automotive applications. Double step-down (DSD, also
known as series-capacitor) converters are among suitable candidates, as they provide
2× duty-cycle extension and 2× equivalent switching frequency with reduced voltage
stress on power transistors by adding only one flying capacitor into a two-phase buck
converter [1]. However, it is still challenging to robustly control a DSD converter to
achieve fast transient responses. Hysteretic control is widely used in the buck converters
for its simple structure and fast responses. However, it may not be feasible to apply
hysteretic control to a DSD converter as the on times of the two phases must have 180°
phase shift and cannot be overlapped. PWM control with fast Type-III compensation [2]
is another attractive option, but it suffers from an inherent delay up to half of a switching
period when responds to a load transient, as will be explained later. In [1], an adaptive
on/off time (AO2T) control approach is proposed to improve the responses by extending
the on time during the transient. However, the 10% settling time of 8.2μs is longer than
16 switching periods for a load step of only 1A and a complicated phase mirroring circuit
is also needed. Moreover, as the operation principle of the DSD converter prevents the
two phases from being turned on simultaneously, the benefit of doubling the slew rate
of the inductor current which is taken advantage of by the two-phase buck converter
disappears.
In this paper, a voltage-mode controlled DSD converter with delay-insensitive and dual-
phase charging techniques is proposed to improve the transient responses. Figure 18.2.1
shows the simplified block diagram of the converter and the operational principle of the
proposed voltage-mode PWM control. The PWM controller has two feedback loops to
generate the duty-cycle signals PWM1,2 for Phase 1 and Phase 2, respectively. The power
stage transfer function of a DSD converter is similar to that of a two-phase buck
converter, and Type-III compensation is adopted to regulate the output voltage in the
Phase-1 loop. The voltage across the flying capacitor VCF is on-line regulated to VIN/2 by
the VCF-calibration circuit in the Phase-2 loop, which does not require a complicated
phase-mirroring circuit and also is immune to the mismatches between the power paths
of the two phases. The VCF-calibration circuit is designed to be much slower than that of
the Phase-1 loop to ensure the stability of the converter. To reduce the complexity of the
controller, only one ramp signal that starts from VL to VH is used. In the steady state, the
error signals of the two loops Vea1,2 range from VL to VM (=(VL+VH)/2) and from VM to VH,
respectively. During the load transient, Vea1 could swing higher than VM to achieve a duty
cycle of greater than 50%, and PWM2 is blocked by PWM1 to avoid the breakdown of
the power transistor SBL.
The performance of the transient responses of the converter with PWM control is affected
by the exact time of occurrence of the transient. As shown in Fig 18.2.2, if the load
transient occurs within the on time of the Phase 1, the loop will respond immediately to
expand the duty cycle to ramp up the inductor current, near optimal responses are
achieved. However, if the transient occurs right after the falling edge of PWM1, the loops
will not respond until CLK2 becomes “1”. Depending on the conversion ratio of the
converter, a delay Td up to half of a switching period is unavoidable regardless of the
loop bandwidth. Such a delay will result in a large droop voltage especially when the load
current step is large. To mitigate this problem, a delay-insensitive technique based on
the fast Type-III compensator reported in [2] is proposed. In the compensator of [2],
Vea1 and Vgm have the same DC voltage in the steady-state, but Vea1 has a much faster
response than Vgm when the load transient occurs. A transient detection circuit is
designed based on this unique feature. Vgm is buffered by the OTA1 with a built-in offset
Vos that is around 150mV and then compared with Vea1 to generate the transient detection
signal Vtran. In the steady state, Vtran is “0” due to the added Vos, and the PWM loops work
as normal. When an up transient occurs, Vtran becomes “1” once Vea1 swings higher than
Vgm+Vos, and PWM1 is set to “1” without the need to wait for the next clock signal.
Therefore, the immediate responses with extended on time can be achieved and the
degradation caused by Td is thus avoided. Note that the proposed delay-insensitive
technique is also applicable to the other converter topologies.
300 • 2022 IEEE International Solid-State Circuits Conference
Figure 18.2.3 shows the schematic of the proposed dual-phase charging technique. A
bidirectional switch SCH that is controlled by Vtran is inserted into the switching nodes
VSW1,2. When Vtran is “1” which means a load transient occurs, both high-side switches
of Phase 1 SAH and SCH are turned on to charge the output capacitor COUT through both
inductors L1,2 simultaneously. The droop voltage and the settling time can be effectively
reduced by nearly 2 times by using this simple technique. VCF bears a temporary offset
voltage during the transient due to the dual-phase charging, and will be regulated to VIN/2
by the calibration circuit later. The capacitance of CF should be properly chosen based
on the maximum step of the load current so that the offset voltage of VCF does not exceed
the safe operation voltage of the power transistor SBL.
The proposed DSD converter was fabricated in a 0.18μm BCD process with all power
transistors integrated on chip. The power stage switches at 1MHz with two 1.8μH
inductors, a 4.7μF flying capacitor and a 10μF output capacitor. Figure 18.2.4 shows the
measured load-transient responses with and without the proposed delay-insensitive
technique. With an Io step of 3A and a rise time of 20ns at VIN/VOUT=24V/1V, the
undershoots and 1% settling times without the delay-insensitive technique range from
94mV to 196mV and 4.6μs to 6.2μs, respectively. Although the responses obtained by
the proposed PWM control are already much faster than that in [1] (~6 switching
periods/3A step versus ~16 switching periods/1A step), the zoom-in waveforms of the
switching nodes VSW1,2 verify that the performance of the responses is seriously degraded
by the delay Td and the undershoot is increased by more than 2 times. Thanks to the
proposed delay-insensitive technique, the undershoots and 1% settling times are
insensitive to Td, with a range of only 73mV~93mV and 1.7μs~2.5μs, respectively. It can
be observed that the responses are also improved by the extended on-time due to the
proposed technique.
Figure 18.2.5 further shows the measured load-transient responses with and without the
proposed dual-phase charging technique at the same Io step of 3A. The measured
undershoot and 1% settling time at VIN =24V with the proposed technique are further
reduced to 56mV and 0.9μs, respectively. The zoom-in waveforms of VSW1,2 indicates
that SCH is turned on to charge COUT with both L1,2, resulting in a fast 1% settling time
that is even shorter than one switching period. Similar improvement is also observed
when VIN=12V, demonstrating the effectiveness of the proposed technique.
Figure 18.2.6 summarizes and compares the performance of the proposed DSD converter
with the state-of-the-art designs. Thanks to the proposed PWM control with delay-
insensitive and dual-phase charging techniques, the presented converter achieves the
fastest transient responses with the smallest output capacitor among all the other works
listed in the table, and is the only one that the performance of responses is not
compromised with the time of occurrence of the load transient. Figure 18.2.7 shows the
die micrograph of the DSD converter.
Acknowledgement:
This work was supported in part by the Strategic Priority Research Program of Chinese
Academy of Sciences under Grant No. XDB44000000 and the National Key R&D Program
of China under Grant No. 2019YFB2204800. Corresponding author: Lin Cheng.
References:
[1] D. Yan, X. Ke, and D.B. Ma, “Direct 48-/1-V GaN-Based DC–DC Power Converter With
Double Step-Down Architecture and Master–Slave AO2T Control,” IEEE JSSC, vol. 55,
no. 4, pp. 988-998, April 2020.
[2] L. Cheng and W.-H. Ki, “A 30MHz hybrid buck converter with 36mV droop and 125ns
1% settling time for a 1.25A/2ns load transient,” ISSCC, pp. 188-189, Feb. 2017.
[3] X. Yang et al., “33.4 An 8A 998A/inch3 90.2% Peak Efficiency 48V-to-1V DC-DC
Converter Adopting On-Chip Switch and GaN Hybrid Power Conversion,” ISSCC, pp.
466-467, Feb. 2021.
[4] K. Wei, Y. Ramadass, and D.B. Ma, “A Direct 12V/24V-to-1V 3W 91.2%-Efficiency
Tri-State DSD Power Converter with Online VCF Rebalancing and In-Situ Precharge Rate
Regulation,” ISSCC, pp.190-191, Feb. 2020.
[5] P.S. Shenoy et al., “A 5 MHz, 12 V, 10 A, monolithically integrated two-phase series
capacitor buck converter,” IEEE APEC, pp. 66-72, Mar. 2016.
978-1-6654-2800-2/22/$31.00 ©2022 IEEE
 ISSCC 2022 / February 23, 2022 / 8:40 AM

Figure 18.2.1: Simplified block diagram of the DSD power converter and operation Figure 18.2.2: Schematic and operation principle of the proposed delay-insensitive
principle of the proposed voltage-mode PWM control. technique.

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Figure 18.2.3: Schematic and operation principle of the proposed dual-phase Figure 18.2.4: Measured load-transient responses with and without the proposed
charging technique. delay-insensitive technique.

Figure 18.2.5: Measured load-transient responses with and without the proposed
dual-phase charging technique. Figure 18.2.6: Performance comparison with previously published works.

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Figure 18.2.7: Die micrograph.

• 2022 IEEE International Solid-State Circuits Conference 978-1-6654-2800-2/22/$31.00 ©2022 IEEE

ISSCC 2022 / SESSION 18 / DC-DC CONVERTERS / 18.3
18.3 A 4A 12-to-1 Flying Capacitor Cross-Connected DC-DC
Converter with Inserted D>0.5 Control Achieving >2×
Transient Inductor Current Slew Rate and 0.73× Theoretical
Minimum Output Undershoot of DSD
Tingxu Hu1, Mo Huang1, Yan Lu1, Rui P. Martins1,2
1
University of Macau, Macau, China
2
University of Lisboa, Lisbon, Portugal
Automotive and industrial applications require a high-efficiency DC-DC converter to
directly convert power from the 12V intermediate bus to a low-voltage point-of-load
(PoL). The double step-down (DSD) buck converter [1-4] (shown in Fig. 18.3.1) is
suitable for such applications, where a flying capacitor CF sustains a half-input-voltage
(VIN/2) stress. Therefore, all the power switches only experience VIN/2 stress except MA2,
allowing for exploiting the benefits of low-voltage devices. Two pulse-width modulation
(PWM) signals Φ1 and Φ2 with an equal duty cycle D drive the DSD. A PoL supply should
have a small output capacitor CO if a fast dynamic voltage scaling (DVS) is needed.
However, a small CO in the conventional DSD may cause a large output undershoot VUS
during a transient event. This comes from the low inductor current slew rate
IL_SR=(VIN/2−2VO)/L, due to the amplitude of the inductor switching nodes VXA1 and VXB1
being reduced to VIN/2 by CF, and the non-overlapping Φ1 and Φ2 in a conventional D≤0.5
control. Furthermore, the D should cover a wide range to respond to an integral transient
error in the control loop compensator. With D≤0.5, the DSD converter may fail to cancel
the error in time, and the accumulation and release of the error result in
overshoot/ringing. This would be more severe at a higher output voltage VO because the
steady-state D is closer to 0.5. A possible solution can be to have a DSD converter that
works with D>0.5. Nevertheless, this leads to an over-sterss on MA1, and imbalance in
inductor currents ILA and ILB, which should be eliminated [3].
This paper presents a CF-Cross-connected (CCC) buck converter with inserted D>0.5
control to improve the transient performance. As shown in Fig. 18.3.1, the CCC buck
consists of six power switches, MA1 to MA3 and MB1 to MB3, two flying capacitors, CFA
and CFB, and two inductors, LA and LB. Although it uses more power switches and CFs
than its DSD counterpart, we can prove that both topologies with optimization have
almost the same power density and efficiency. Similar to the DSD, the CCC steady-state
operation requires three working states S1, S2, and S3, and a periodic working sequence
of S1-S3-S2-S3, and Φ2 lagging π behind Φ1. During a transient event, we insert an
asynchronous state S4 (MA1 and MB1 turn on, others turn off), overlapping Φ1 and Φ2
and thus obtaining a transient IL_SR=(VIN−2VO)/L that is at least twice that of the DSD.
This reduces the VUS without over-stressing the switch nor results in unbalanced ILs.
Besides, with D not limited to a value ≤0.5, the proposed scheme reduces the
accumulated transient voltage error and thus also reduces the overshoot/ringing in
recovery. Figure 18.3.1 presents the block diagram of the proposed circuit. We use NMOS
for all power FETs, where MA1, MA3, MB1, and MB3 use low-voltage devices, while MA2 and
MB2 use high-voltage ones. VDR=5V directly drives MA1 and MB1, while the high-side (HS)
FETs (MA2, MA3, MB2, and MB3) need bootstrap (BS) gate driver (GD) and level shifter
(LS). We share the BS capacitors CBSs to save silicon area. The synchronized hysteretic
controller processes VO, reference voltage VREF and the AC component of ILA (sensed by
an RC filter), and outputs Φ1 and ΔΦ. The parameter ΔΦ is the phase lag between Φ1 and
Φ2, which is π in the steady-state but is small during a transient event. The D copier
copies the Φ1’s D (D1) to that of Φ2 (D2) with the desired phase lag. To prevent CF voltage
unbalance, D1 and D2 should always be equal. Φ1 and Φ2 generate non-overlap switching
signals A1-3 and B1-3.
Figure 18.3.2 shows the working principle and schematic of the controller and D copier.
We use a high-gain error amplifier EA to improve the VO accuracy. The ILA-emulated signal
VSNS generates Φ1 through a hysteretic comparator CMPHYS. To narrow the hysteretic
window and respond instantly to a transient event, a positive VO/(R1×CRAMP) slope
compensator [5] chops the negative slope of VSNS, and generates the compensated
output, VRAMP. A voltage follower, made from a folded cascode OTA, generates the upper
and lower hysteretic bounds of the CMPHYS (VEAL and VEAH) that follow VEA variations. In
the steady-state, the CLK rising edge synchronously resets CRAMP and Φ1=1 when
VRAMP<VEAL. Then CRAMP is charged and VRAMP goes up, and VRAMP>VEAH resets Φ1. During
Φ1=1 that lasts tUP, the D copier charges the CCP with IUP, from a starting voltage VB. After
that, the CLK falling edge generates the ΔΦ pulse, setting Φ2 and discharging CCP with
IDN. Φ2 is reset once VCP=VB, and the Φ2 pulse-width is tDN. Then tUP=tDN (or D1=D2) if
IUP=IDN. Meanwhile, the CLK’s D=0.5 imposes that Φ2 lags π behind Φ1. During a transient
event, VO drops, and VRAMP quickly reaches VEAL that follows VEA, setting Φ1 and charging
CCP. A ΔΦ pulse is generated when VO crosses VREFL=VREF−40mV, setting Φ2 shortly after
Φ1, stopping the charging of CCP and triggering S4. Then Φ1=0 once VRAMP reaches VEAH.
Φ1=1 lasts tUP+tIDLE eventually extending D to a value >0.5. CCP begins to discharge at the
302 • 2022 IEEE International Solid-State Circuits Conference
falling edge of Φ1 until VCP reaches VB. Hence, the pulse-width of Φ2 is tIDLE+tDN, which
should be equal to that of Φ1. To better match IUP and IDN against VCP variations, we
employ a charge-pump circuit similar to that of a PLL.
The shared CBS scheme in [6] requires S3 to charge the CBS, which does not suit D≥0.5
operation. This is because probably there is no S3 during transient, such as a S2-S1-
S4-S2 sequence in Fig. 18.3.2, and hence the over-discharged CBS may fail to turn on
the HS switches. Alternatively, the proposed scheme shown in Fig. 18.3.3 shares the CBS
of MA2 and MA3 as CBSA, and that of MB2 and MB3 as CBSB. CBSs charge the HS switches
through S2P and S2N (or S3P and S3N) at the beginning of each state, while VDR charges
CBSs through S1P and S1N afterwards. Hence, it does not need S3 to charge CBSs, suitable
for D≥0.5 operation. However, this scheme inserts additional series switches
(resistances) to the driving paths that lengthens the switching time TOV around the Miller
plateau (MP), inducing a larger V-I overlap loss POV. To reduce POV, we add small local
capacitors CLA2,3 and CLB2,3 to charge the HS switches without additional series switch.
As indicated by the conceptual waveforms, with the help of the local capacitors, the VGS
of HS switches rises fast over the MP, reducing TOV and thus POV. The simulated POV
decreases by 73% with CLA2,3/CLB2,3=0.12×CBSA/CBSB. The small local capacitor may not
provide sufficient charge to fully turn on the HS switch. Then, the large CBS provides
additional charge after the MP without further increasing POV. Furthermore, this work
achieves a higher VGSA3, VGSB3, and smaller total bootstrap capacitance than [6].
The proposed CCC buck converter, fabricated in a 0.18μm HV SOI CMOS process,
comprises integrated power switches, CBSs and controller, with a chip area of 2.8mm2.
We measure it with VIN=12V, fSW=2MHz, CFs=2.2μF, and Ls=0.56μH, CO=14.7μF (nominal
values). The CCC with D≤0.5 control is used as a baseline design that should have a
transient performance close to that of a conventional DSD. Figure 18.3.4 shows the
measured load transient waveforms. At VO=1.2V, at a 0-to-4A load current step with a
rising time tR=20ns, the D≤0.5 control generates a consecutive D=0.5, causing
IL_SR=4.5A/μs and VUS=0.19V. As predicted, the accumulated error due to the limited D
results in a recovery overshoot/ringing, especially at VO=1.8V. By contrast, the D>0.5
control achieves IL_SR=10.8A/μs, VUS=0.11V, and unobservable ringing. ΔΦ is π at the
steady-state while it is small during the load transient, and D1=D2. This verifies the
proposed D copier design. Figure 18.3.5 displays the measured DVS waveforms, at
RL=1.2Ω and 0.6Ω. VREF changes from 0.9V to 1.8V with a slew rate 0.3V/20ns. Still, the
D>0.5 control achieves a reduced ringing, and an up-tracking time reduction from 1.45μs
to 1.12μs at RL=1.2Ω. Figure 18.3.6 presents the measured efficiency of the proposed
CCC converter with 0.2-to-4A IO. Including the gate loss PGATE, it achieves 89.3%, 86.8%,
and 84.6% peak efficiency at VO=1.8V, 1.2V. and 0.9V, while it is 91%, 89.6%, and 88.2%
efficient without PGATE. When compared with recent works, the proposed CCC with D>0.5
achieves a VUS that is only 73% of the theoretical minimum VUS [7] achieved by a
conventional DSD with D≤0.5 (VDSD,MIN). Meanwhile, it integrates the CBSs with a small
silicon area while exhibiting a comparable peak efficiency. Figure 18.3.7 shows a chip
micrograph and a photo of the PCB.
Acknowledgement:
This work was supported by the Natural Science Foundation of China under Grant
61974046, and the Science and Technology Development Fund, Macau, SAR, under
Grant 145/2019/A3 and Grant SKL-AMSV(UM)-2020-2022.
References:
[1] P. S. Shenoy et al., “A 5 MHz, 12 V, 10 A, monolithically integrated two-phase series
capacitor buck converter,” APEC, pp. 66-72, Mar. 2016.
[2] O. Kirshenboim et al., “Closed-Loop Design and Transient-Mode Control for a Series-
Capacitor Buck Converter,” IEEE TPEL, vol. 34, no. 2, pp. 1823-1837, Feb. 2019.
[3] D. Yan et al., “Direct 48-/1-V GaN-Based DC–DC Power Converter with Double Step-
Down Architecture and Master–Slave AO2T Control,” IEEE JSSC, vol. 55, no. 4, pp.
988-998, Apr. 2020.
[4] Texas Instruments, “TPS54A20 8-V to 14-V Input, 10-A, up to 10-MHz Swift Step
Down Converter,” Accessed on Dec. 1, 2021,
<http://www.ti.com/lit/ds/symlink/tps54a20.pdf>.
[5] M.K. Song et al., “A 6A 40MHz four-phase ZDS hysteretic DC-DC converter with
118mV droop and 230ns response time for a 5A/5ns load transient,” ISSCC, pp. 80-81,
Feb. 2014.
[6] M. Huang et al., “A Hybrid Boost Converter with Cross-Connected Flying Capacitors,”
IEEE JSSC, vol. 56, no. 7, pp. 2102-2112, July 2021.
[7] Y.-W. Huang et al., “A Four-Phase Buck Converter with Capacitor-Current-Sensor
Calibration for Load-Transient-Response Optimization That Reduces
Undershoot/Overshoot and Shortens Settling Time to Near Their Theoretical Limits,”
IEEE JSSC, vol. 53, no. 2, pp. 552-568, Feb. 2018.
978-1-6654-2800-2/22/$31.00 ©2022 IEEE
 ISSCC 2022 / February 23, 2022 / 8:50 AM

Figure 18.3.1: DSD buck converter and its limitation during a load transient, with D≤0.5 Figure 18.3.2: Schematic of the synchronized hysteretic controller (left top) and D copier
and D>0.5 controls (left). Working principle of the CCC buck converter with inserted D>0.5 (left bottom). Conceptual waveforms of the controller during a light-to-heavy load transient
control (right top), and its block diagram (right bottom). event (right).

18

Figure 18.3.3: Working principle of the proposed shared CBS schemes (top).
Conceptual waveforms indicate a reduced POV with shared CBSs (bottom left), and Figure 18.3.4: Measured 0-to-4A, 20ns transition time, load transient response
simulated POV versus local capacitors (bottom right). waveforms with D≤0.5 and D>0.5 (proposed), at VO=1.2V and 1.8V.

Figure 18.3.5: Measured DVS waveforms with D≤0.5 and D>0.5 (proposed), at Figure 18.3.6: Efficiency versus IO (left), and performance comparison with the state-
RL=1.2Ω and 0.6Ω. of-the-art works (right).

DIGEST OF TECHNICAL PAPERS • 303

 ISSCC 2022 PAPER CONTINUATIONS

Figure 18.3.7: Chip micrograph and PCB photo.

• 2022 IEEE International Solid-State Circuits Conference 978-1-6654-2800-2/22/$31.00 ©2022 IEEE

ISSCC 2022 / SESSION 18 / DC-DC CONVERTERS / 18.4
18.4 A Monolithic 3:1 Resonant Dickson Converter with Variable
Regulation and Magnetic-Based Zero-Current Detection and
Autotuning
Prescott H. McLaughlin, Kishalay Datta, Jason T. Stauth
Dartmouth College, Hanover, NH
In the last decade, hybrid and resonant switched-capacitor (SC) converters have gone
from a relatively unexplored concept to one that is gaining widespread adoption in a
range of applications [1]. However, despite capabilities to operate efficiently with small
passive components, extending these topologies to use silicon-integrated inductors
remains challenging [2-6]. This work presents a nominally 3:1 step-down resonant
Dickson converter targeting low-voltage applications and providing several advances
compared to past work. Shown in Fig. 18.4.1, the design uses a merged electromagnetic
spiral resonator. As in [3], the merged resonator combines flying capacitance and
inductance into a single structure. Shared die area reduces size overhead but also
provides current ballasting which counteracts strong high-frequency (skin and proximity)
loss effects, enabling high-frequency operation with better efficiency and power density.
Improvements from past work include: 1) an extension to higher conversion ratios, which
motivates new gate driving and bootstrapping strategies; 2) leveraging magnetic coupling
in a Dickson architecture to improve inductance utilization and reduce resonant-frequency
variation in phase half cycles; and 3) the design of integrated zero-current (resonant-
frequency) autotuning using an on-chip magnetic current-sensing scheme.
Shown in Fig. 18.4.1, during phase Φ1, switches M2, M3, M5, and M7 turn on to charge
resonant tank LC2 while LC1 discharges. In phase Φ2, switches M1, M4, and M6,6C turn on
to charge LC1 as LC2 discharges. All switching devices in the 0.18μm bulk-CMOS process
are low voltage (~Vin /3) except for the cascode device M6,6C (~2Vin /3). On-chip bypass
capacitors Cog and Cio provide a low impedance, low ESR path for current flow in the two
phases. The resonator windings are configured such that the current direction remains
matched between LC1 and LC2 despite their opposing charge-discharge polarities, linking
their flux to provide increased (mutual) inductance in each resonator phase. Each
merged-LC resonator phase is implemented using 8 parallel 2-turn windings with tapered
trace widths and stackup variations in the top 4 metal layers, resulting in a series
resistance of ~650mΩ. Additional substrate losses are mitigated using a pattern of N-
well strips orthogonal to the winding direction. Each resonator phase has ~2.7nF of
winding-embedded MIM capacitance and ~10nH of coupled inductance, with EM
simulated coupling coefficient, k12, of 0.85 to 0.95 due to the high number of
interdigitated windings.
Figure 18.4.2 shows the gate drive and timing circuits for the all-NMOS powertrain.
Because distributed inductance prevents bootstrapping from flying capacitor voltages,
the proposed scheme allows all switches controlling the positive resonator terminals
(V1+ and V2+) to bootstrap off Vin, using a single external voltage Vgd for the half-bridge
switches controlling the negative resonator terminals (V1- and V2-). Synchronous
bootstrapping for Cbs7 occurs during Φ2 from Vin, with Cbs2 and Cbs4 synchronously
bootstrapping from Vgd during Φ1 and Φ2, respectively. Gate charge for the cascoded
device M6,6C is supplied directly from Vin during phase Φ2, with bootstrap capacitor Cbs6
serving to provide a bias for the gate of M6C and the bootstrap charge for Cbs5 during
phase Φ1. Since M5 is driven directly from Cbs6, this allows Cbs5 to be considerably smaller
as it is only required to supply the initial gate charge until bootstrap switch Mbs5 is
enabled. All bootstrap capacitance (~1.3nF total) is integrated on chip using MIM
capacitors. Level shifters are implemented using a current-mode design for fast response
and symmetric rise/fall propagation delays. An anti-shoot-through buffer chain reduces
voltage- and frequency-dependent losses in the last stage of the gate driver.
Figure 18.4. 3 shows the gate drive signal generation using a voltage-controlled oscillator
(VCO). To improve timing accuracy and efficiency at ~30MHz operation, the VCO is pre-
biased in an overlapping clock state, compensated by a current-starved delay line (CSDL);
this allows the VCO to achieve deadtimes <200ps, shorter than a gate delay. Fast output
voltage regulation is achieved using an off-time modulation (OTM) scheme [3], with a
linear OTA injecting a current signal, proportional to the error signal, into the VCO to
control the off-time between resonant conducting states. This results in linear regulation
of the output voltage, scaling with the effective resistance (Reff) of the converter. While
this can result in high output ripple [2], such can be mitigated with modest off-chip or
on-load bypass capacitance [3].
Also shown in Fig. 14.8.3 is the ZCS autotuning control that independently regulates the
on-times of switch phases Φ1 and Φ2. Using the availability of in-situ resonator current
due to on-chip magnetics, a small auxiliary winding is wound on the inner radius of the
resonator. The ZCS controller functions by magnetically coupling the residual resonator
current in LC1 and LC2 through the auxiliary winding and using two track and hold circuits
304 • 2022 IEEE International Solid-State Circuits Conference
to sequentially sample the winding voltage to determine the polarity of the resonator
current at the switching transition. When switches M1 and M2 are closed, capacitors Cth1
and Cth2 track the auxiliary winding voltage. When the powertrain switches turn off, switch
M1 opens to latch the initial voltage on the auxiliary winding; subsequently (during the
dead-time interval), switch M2 opens to latch the voltage at a fixed delay from the
switching edge. These capacitor voltages are then compared using a sampled
comparator. In the case of phase Φ1, if Vth2>Vth1, inductor current is still positive (pulse
width too short) as the residual flux drives VLaux to increase; if Vth2<Vth1, inductor current
is negative (pulse width too long) as residual flux forces VLaux to decrease.
Using this information, a digital controller sends an up- or down-pulse to a charge pump
that increases or decreases the VCO voltage Vt1 or Vt2, corresponding to on-times ton1 or
ton2. Phases Φ1 and Φ2 are sampled alternatively at 1/32 of the switching frequency (fsw)
to autotune the on-times individually and ensure ZCS (resonant) operation in both
switching phases. Due to low variation in the resonant frequency over time, this slow
control loop and the auxiliary winding itself consume negligible quiescent power (~6μW).
Figure 18.4.4 shows transient response data for the OTM output regulation as well as
the ZCS autotune controller. Regulation shows <30mV deviation when tracking a 100kHz,
200mVpp reference voltage, with 50mV over/undershoot for a 10-50mA, 2.5μs un/loading
event. ZCS autotuning startup from severe frequency and on-time deviations shows
steady-state settling and Vout enhancement within ~100μs. When on-time operating point
voltage Vop is modulated to inject ±4ns errors in on-time, ZCS autotuning shows accurate
regulation back to resonant operation with steady-state on-time deviation less than
±250ps (<1.6% steady-state error (SSE)) of the resonant half-period due to the
integrating control scheme.
Figure 18.4.5 provides measured converter performance data. The converter achieves a
peak efficiency of 78.3% at 140mW (fsw = 30MHz, Vin /Vout = 4.2V/1.2V) and a peak output
power of 670mW (Vin /Vout = 6.6V/1.4V). For input voltages from 3.3 to 6.6V, peak
efficiency stays above 76.5% for power between 90 to 400mW, with light-load operation
enabling efficiency above 60% from 400μW up to peak power. With closed-loop
feedback, the circuit can regulate the output between 0.8 to 1.6V (0.16<VCR<0.32) from
a 5V supply. SSE is below 0.65% showing accuracy of OTM regulation within a few mV.
Measured output voltage ripple at maximum VCR remains below 50mV when using a
100nF off-chip bypass capacitor, increasing when only on-chip bypassing is used.
Figure 18.4.6 shows a comparison to past work. This work features the first fully-
integrated ReSC converter with over 2:1 conversion ratio, achieving comparable
efficiency at higher conversion ratio while also including fast output voltage regulation
and the first implementation of closed-loop ZCS control, which uses a magnetically
coupled auxiliary winding. Figure 18.4.7 shows a chip micrograph, with a 4.1mm2
resonator area and total active die area of 8.7mm2 with bypass capacitance and 5.2mm2
without.
Acknowledgement:
This work was supported in part by the Semiconductor Research Corporation (SRC)
under Task 2810.040.
References:
[1] W.-C. Liu et al., “A 94.2%-Peak-Efficiency 1.53A Direct-Battery-Hook-Up Hybrid
Dickson Switched-Capacitor DC-DC Converter with Wide Continuous Conversion Ratio
in 65nm CMOS,” ISSCC, pp. 182-183, Feb. 2017.
[2] P. Renz et al., “A Fully Integrated 85%-Peak-Efficiency Hybrid Multi Ratio Resonant
DC-DC Converter with 3.0-to-4.5V Input and 500μA-to-120mA Load Range,” ISSCC, pp.
156-157, Feb. 2019.
[3] P.H. McLaughlin et al., “A Fully Integrated Resonant Switched-Capacitor Converter
with 85.5% Efficiency at 0.47W Using On-Chip Dual-Phase Merged-LC Resonator,”
ISSCC, pp. 192-193, Feb. 2020.
[4] A. Novello et al., “A 1.25GHz Fully Integrated DC-DC Converter Using
Electromagnetically Coupled Class-D LC Oscillators,” ISSCC, pp. 260-261, Feb. 2021.
[5] C. Schaef et al., “A Variable-Conversion-Ratio 3-Phase Resonant Switched Capacitor
Converter with 85% Efficiency at 0.91W/mm2 Using 1.1nH PCB-Trace Inductors,” ISSCC,
pp. 360-361, Feb. 2015.
[6] N. Tang et al., “Fully Integrated Buck Converter with 78% Efficiency at 365mW Output
Power Enabled by Switched-Inductor Capacitor Topology and Inductor Current Reduction
Technique,” ISSCC, pp. 152-153, Feb. 2019.
978-1-6654-2800-2/22/$31.00 ©2022 IEEE
 ISSCC 2022 / February 23, 2022 / 9:00 AM

nominal voltage waveforms floating-domain bootstrapping

bootΦ1 bootΦ2 Vin V2+ Vin Vout Vin Vin

Mbs7

Mbs6
2Vout LS LS
clk1 clk2 Vout V1+ LS
Vout
5V transistors Mbs5
Φ1 Φ2 Φ1 Φ1 Φ2 Φ1
Cbs7 Cbs6 Cbs5
anti shoot-through VH
buffer chain
LS gate
slow on, fast off LS LS LS
out voltage

VL
Vin
level shifter VH
V2+ V1+ Vout
vdd! LS M7 M6C M6 M5
out half-bridge bootstrapping
Vout
VL Cbs2,4
LS LS
Cgs current M2,4
sink Vgd
Cgd
LS
small reset M1,3

LS in
switch

Figure 18.4.1: Resonant Dickson converter powertrain with distributed coupled

inductors implemented as merged-LC resonators and current sense auxiliary Figure 18.4.2: Gate drive, level shift, and bootstrap circuits with example voltage
winding. waveforms.

voltage-controlled oscillator vdd! 100kHz 200mVpp reference voltage tracking OTM output regulation load step response (+/-40mA/2.5μs)
clk2OTM
VonEN VoffEN 50mV/div (ac coupled) Vref 200 mV/div
clk1OTM Vout
Voff Vref Vref
Vout Vout
Vt2 Vt1 Iout: 20mA/div
Vt2EN Vt1EN Vin = 5V clk1: 1V/div
D Q clk1:
500mV/div Vref,DC = 1.2V
Q
0 5 10 15 20 25 30 35 40 45 50
time (μs)
VoffEN clk1OV
zero-current autotuning S Q S Q CSDL clk1 ZCS on-time regulation response to +/-4ns injected error
18 20
Vaux M2 VonEN clk2OV
R Q R Q CSDL clk2 0 2 4 6 8 10 12 14 16 18 20 16 18
Vth2 time (μs) 14 16
C2 C1 M1 Vth1 sample during
+ Φ1 too short Φ1 too long 12 14
PT VLaux dead-time ZCS autotune controller startup 100 500 900 5100 5500 5900
L2 L1 Caux Cth1 Cth2
Laux
Vcm
- IL2 IL2
50
Vout
1.4 20
independently
900
18
on-time | frequency (ns | MHz)

IL1 IL1 autotuned on-times

40 1.2 18 700
Vt1 Vin = 5V ton1
Q pump
clk1 Q D Vth2 Vth1 fsw: MHz Iout = 250mA
VCO/ Vt2 Q pump
on-time (ns)
CTRL
voltage (V)
16 500

voltage (V)
Vth1 Vth2 30 1
CSDL logic ton2
Vref ns
clk2 Voff VLaux VLaux 14 300
V out 20 ton1 0.8
ffEN
clk1 clk2 clk1 clk2 12 response to injected Vop 100
cmpEN ton2 disturbances
up/down pulses 10 0.6
sampled strongarm latch 10 -100
-100 0 100 200 300 400 500 0 1000 2000 3000 4000 5000 6000
time (μs) time (μs)
Figure 18.4.3: Clock generation, ZCS control, and off-time modulation circuits and
example waveforms. Figure 18.4.4: Off-time modulation and ZCS autotune control transients.

efficiency with light-load off-time modulation eff. converter resistance vs. switching frequency Tang, Schaef, Renz, McLaughlin, Novello,
80 100 This Work
ISSCC19 [6] ISSCC15 [5] ISSCC19 [2] ISSCC20 [3] ISSCC21 [4]
75 Topology SIC ReSC ReSC ReSC Class-D LC ReSC
off-time modulation Conversion Ratio (N:1)* 1.33:1 2:1 2:1 2:1 2:1 3:1
70
effective resistance (Ω)

Interleaved Phases 1 3 1 2 4 1
efficiency (%)

65 Reff Technology
65 nm 0.18 μm bulk
0.13 μm BCD
0.18 μm bulk 0.18 μm bulk 0.18 μm bulk
30MHz CMOS CMOS CMOS CMOS CMOS
60 10 fsw (MHz) 450 53 35.5 47.5 1250 30
Vin = 3.7V
55 resonant Vin (V) 1.2 6/3 3.0 – 4.5 2.4 – 4.4 1 – 3.6 3.3 – 6.6
Vin = 4.2V mode Vout (V) 0.6 – 0.9 3.7/1.85 1.5 – 1.8 1.0 – 2.2 0.4 – 1.6 0.8 – 2.2
50
Vin = 5.0V Ltotal (nH) 0.85 1.1 off-chip 9 7.7 coupled 7.8 coupled 10 coupled
45 Cfly,total (nF) 1.72 24 2 × 1.0 2 × 1.7 2 × 0.23 2 × 2.7
Vin = 6.6V
Cin (nF) not reported 6 0.18 + off-chip 7 0 4.2
40 1
1 10 100 1 10 100 Cout (nF) 3.1 6 10 7 0 5.8
output power (mW) switching frequency (MHz) Area (mm2) 0.65 8.4 7.83 8.93 1.61 8.7
output regulation: <0.65% SSE, 64.5% EEF comparison to highly/fully Peak Efficiency (%) 78 85.1 85 85.5 67 78.3
efficiency enhancement factor (%)

integrated converters @ EEF** (%) 3.9 45.9 45.7 45.8 30.9 62.1
output voltage ripple (mVpp)

70
power density (W/mm2)

on-chip only this work @ Power Density (W/mm2) 0.55 0.91 0.033 0.053 0.21 0.016
steady-state error (%)

1.6 0.9 550 75 0.8

EEF 60 McLaughlin, ISSCC20
output voltage (V)

Vout 450 65 Peak Power Density (W/mm2) 0.73 0.91 0.033 0.097 0.3 0.077
1.4 0.7 50 Schaef,
350 ΔVout with 55 0.6 @ EEF** (%) -0.5 45.9 45.7 49.1 28.9 65.7
40 ISSCC15
1.2 0.5
250 diff. Cbp 45 30
Novello,
0.4
@ Efficiency (%) 74.6 85.1 85 74.5 65.2 61
SSE 15nF ISSCC21
Peak Output Power (W) 0.48 7.7 0.22 0.87 0.6 0.67
1 0.3 150 35 20 Renz, ISSCC19
100nF 0.2 Minimum VCR (Vout /Vin) 0.5 0.32 0.33 0.28 0.3 0.16
0.8 0.1 50 25 10 Tang, ISSCC19
0 Integrated Control PWM None None OTM None OTM + ZCS
0.8 1 1.2 1.4 1.6 0.15 0.2 0.25 0.3 0.35 1 2 3 4 5 6 7 *Nominal conversion ratio @ peak efficiency
reference voltage (V) voltage conversion ratio (VCR) max. conv. ratio (N:1) **Efficiency Enhancement Factor (EEF) = 1 – ηLDO/ ηconv

Figure 18.4.5: Measured efficiency, effective converter resistance, output regulation Figure 18.4.6: Comparison with recently published highly/fully integrated power
performance, and comparison to prior fully integrated ReSC converters. converters.

DIGEST OF TECHNICAL PAPERS • 305

 ISSCC 2022 PAPER CONTINUATIONS

total active area:

merged-LC 8.7mm2
resonator (5.2mm2 excl. Cio & Cog)
(4.08mm2)
aux. winding
Cio

M7
M4
M2 M6,6C
control & timing
M3 M1 M5
orthogonal
capacitors
bootstrap

N-well pattern

Cog
Laux+ Laux-
Cio to ZCS control

Figure 18.4.7: Die micrograph of the Dickson ReSC converter highlighting merged-
LC resonator and auxiliary winding in center.

• 2022 IEEE International Solid-State Circuits Conference 978-1-6654-2800-2/22/$31.00 ©2022 IEEE

ISSCC 2022 / SESSION 18 / DC-DC CONVERTERS / 18.5
18.5 A 12A Imax, Fully Integrated Multi-Phase Voltage Regulator
with 91.5% Peak Efficiency at 1.8 to 1V, Operating at 50MHz
and Featuring a Digitally Assisted Controller with Automatic
Phase Shedding and Soft Switching in 4nm Class FinFET
CMOS
Christopher Schaef1, Tamir Salus2, Rachid Rayess3, Siddarth Kulasekaran4,
Mat Manusharow4, Kaladhar Radhakrishnan4, Jonathan Douglas4
1
Intel, Hillsboro, OR
2
Intel, Haifa, Israel
3
Intel, Hudson, MA
4
Intel, Chandler, AZ
Modern compute SoCs often consume 100s of amperes at voltages of 1V and below
which poses huge challenges for delivering power to the socket. Fully integrated voltage
regulators (FIVRs) can mitigate these challenges by providing local step-down
conversion, hence reducing input current to the socket [1-4]. In addition to the large
current draw, most digital compute domains employ dynamic power management
techniques to optimize power consumption based on performance demand, that results
in a large load current range in FIVRs used in granular domains. At the same time,
transitions from low to high current can happen at nanosecond timescales. As a result,
the FIVR must provide high efficiency over a wide load current range while retaining fast
transient response to minimize performance impact from voltage droops. Past
implementations used discontinuous conduction mode (DCM) to provide a good light
load efficiency [2], however, DCM increases voltage ripple and can hurt transient
response.
This paper presents a FIVR with a digitally assisted control loop that allows autonomous
phase shedding (APS) while retaining the transient response of a high-speed analog
Type-III controller. The FIVR is implemented in a 4nm class CMOS process with package-
embedded magnetic inductors [5] which provide an inductance of 5nH per phase. A
magnetic layer that surrounds serially connected plated through-hole vias through the
package core increases inductance compared to air core inductors used in previous work
[1,2]. Each phase consists of a cascoded powertrain to support an input voltage of 1.8V.
Both, the high-side pmos and low-side nmos switches are equipped with replica-based
current sensors to sense the output current of each phase. Current information is
digitized using an 8b SAR ADC and is directed through a digital ‘Phase Control’ block
that processes the synchronous digitized current information, as well as asynchronous
transient events and sets the correct phase count to optimize efficiency and transient
response.
Figure 18.5.1 shows a system level diagram of the proposed FIVR with 4-phase
powertrain and digitally assisted analog compensation. The compensator consists of a
differential-to-single-ended conversion stage for high DC accuracy and a single-ended
compensation stage. This implementation reduces area and power overheads as
compared to a single differential compensation stage. Each of the resistor and capacitor
elements, R1-3 and C1-3, is digitally controlled, which allows pole/zero locations to be
dynamically adjusted based on phase configuration and obtain optimal control
bandwidth. The compensator output goes to a 4-phase pulse-width modulator (PWM)
which generates phase-interleaved PWM signals for each powertrain phase. An 8b SAR
ADC digitizes current information provided by each phase to decide appropriate phase
count and soft-/hard-switching settings for optimal efficiency. The current is monitored
and is compared to a programmable upper and lower current threshold, if the upper
threshold is exceeded for a predetermined time period, the phase count is increased.
Conversely, if the current is below the lower threshold, phase count is decreased.
Additionally, soft switching is enabled for 1- and 2-phase operation while hard-switching
is used for the maximum phase count of 4, since hard switching provides better efficiency
and lower device stress at high currents. For faster response to load transient, the phase
controller also accepts asynchronous inputs which can force an immediate transition to
the maximum phase count to minimize voltage droop.
Details on the current sensing implementation are shown in Fig. 18.5.2. Replica-based
current sensors are implemented on both the low-side (nmos) and high-side (pmos)
switches. Series resistors are added at the input to the common-gate sense amplifier to
create an intentional offset voltage Vos, which prevents the amplifier input voltage from
exceeding the Vin/Gnd rails when ripple current causes negative current to flow through
the switches. The resulting offset is digitally calibrated. The sense currents from low-
and high-side sensors are added for all phases and divided by the phase-count through
a programmable current mirror. The resulting current information thus represents an
average, per-phase current which reduces dynamic range requirements on the ADC. In
addition, the analog high current detection signal (hc_det) can be generated by
306 • 2022 IEEE International Solid-State Circuits Conference
comparing the average phase current to a fixed reference current. This high current signal
serves as one of two asynchronous transient events. A second transient event is
generated by directly detecting voltage droops at the FIVR output. The droop detector
uses a high-pass filter to filter out voltage setpoint transitions which happen at a relatively
slow timescale and only pass through transient droop events. The filtered voltage is
biased to a DC bias point of Vcm, a DAC generates a droop threshold voltage which is set
to Vcm–50mV for the purposes of this paper.
Measured efficiency numbers with and without automatic phase transitions are shown
in Fig. 18.5.3. With soft-switching, peak efficiency reaches ~91.5% at 0.6A (1-phase),
1.2A (2-phase) and 2.4A (4-phase), while efficiency is approximately 1% lower with
90.5% at 0.75A (1-phase), 1.5A (2-phase) and 3A (4-phase) when hard-switching is
used. With APS enabled, the efficiency curve tracks the optimal efficiency relatively well
and automatic transitions occur from soft switching at 1- and 2-phase, to hard switching
at 4-phase operation, to provide better performance at high current. Transient waveforms
during the phase transitions are shown in Fig. 18.5.4 for two different load steps from
1A to 6A and from 3A to 8A. After the current reduces from 6A to 1A, two phase
transitions occur, first from 4 to 2 phases, then from 2 to 1 phase. In contrast, when the
current is reduced to 3A, only a single transition from 4 to 2 phases occurs.
One of the most challenging aspects for FIVRs is the transient response to fast load
transients which is critical due to limited on-die output decoupling capacitance. This
implementation uses a total output capacitance of 800nF, implemented with on-die MIM
capacitance. A digitally controlled load, consisting of a 16×16 array of distributed load
cells and a skew-controlled trigger network, was implemented to create current slew
rates of >5A/ns. The droop response to a 0A to 10A load step is shown in Fig. 18.5.5. As
a baseline comparison, the droop without APS and 4 phases enabled is measured at
90mV. In comparison, droop increases significantly to 139mV with APS enabled but
voltage droop detection disabled. Due to the slower loop response in single-phase
operation and bandwidth limits of the current-sensing chain, the high current detect
signal only induces a transition to 4 phases approximately 45ns after the current step.
With droop detection enabled, this delay reduces to <6ns, with a comparator droop
threshold of –50mV. As a result, the increase in droop compared to the baseline reduces
to 5mV. The benefits of adjusting compensator RC-settings as a function of phase count
are illustrated by the loop gain measurement in Fig. 18.5.5. The FIVR achieves its highest
closed-loop bandwidth of 17MHz in 4-phase operation, 11.8MHz in 2-phase and 7MHz
in single-phase operation.
The comparison table in Fig. 18.5.6 summarizes key performance metrics. Compared to
previous work, this implementation achieves a higher peak efficiency of 91.5% at 1.8-
to-1V conversion. Based on the active circuit area of 0.255mm2 (includes powertrain and
all control circuitry), and a maximum output current of 12A, this work achieves a current
density of 47A/mm2. An annotated chip micrograph and cross-sectional X-ray of the in-
package magnetic inductors are shown in Fig. 18.5.7.
References:
[1] E.A. Burton et al., “FIVR — Fully Integrated Voltage Regulators on 4th Generation
Intel® Core™ SoCs,” pp. 432-439, APEC, Mar. 2014.
[2] C. Schaef et al., “A Fully Integrated Voltage Regulator in 14nm CMOS with Package-
Embedded Air-Core Inductor Featuring Self-Trimmed, Digitally Controlled Variable
On-Time Discontinuous Conduction Mode Operation,” ISSCC, pp. 154-155, Feb. 2019.
[3] H.K. Krishnamurthy et al., “A Digitally Controlled Fully Integrated Voltage Regulator
with On-Die Solenoid Inductor with Planar Magnetic Core in 14nm Tri-Gate CMOS,”
ISSCC, pp. 336-337, Feb. 2017.
[4] N. Sturcken et al., “A 2.5D Integrated Voltage Regulator Using Coupled Magnetic-
Core Inductors on Silicon Interposer Delivering 10.8A/mm2,” ISSCC, pp. 400-402, Feb.
2012.
[5] K. Bharath et al., “Integrated Voltage Regulator Efficiency Improvement using Coaxial
Magnetic Composite Core Inductors,” ECTC, pp. 1286-1292, June 1 to July 4, 2021.
978-1-6654-2800-2/22/$31.00 ©2022 IEEE
 ISSCC 2022 / February 23, 2022 / 9:10 AM

Figure 18.5.1: System-level diagram of the proposed 4-phase FIVR with digitally Figure 18.5.2: Circuit diagram showing current sensing implementation and transient
assisted Type III control loop. event detection.

18

Figure 18.5.3: Efficiency measurements in 1-,2-, and 4-phase configurations with Figure 18.5.4: APS response to current changes showing automatic phase-transitions
soft/hard switching and with automatic phase transitions. based on current level.

Figure 18.5.5: Transient response to a 10A load step without APS, with APS (no droop
detection) and with APS + droop detection (top). Loop gain measurements in 4-, 2-
and 1-phase operation with bandwidth and phase margin annotated (bottom). Figure 18.5.6: Performance summary and comparison with previous publications.

DIGEST OF TECHNICAL PAPERS • 307

 ISSCC 2022 PAPER CONTINUATIONS

Figure 18.5.7: Annotated die micrograph showing FIVR location with on-die load
array (left) and cross-sectional X-ray image of in-package magnetic inductors (right).

• 2022 IEEE International Solid-State Circuits Conference 978-1-6654-2800-2/22/$31.00 ©2022 IEEE

ISSCC 2022 / SESSION 18 / DC-DC CONVERTERS / 18.6
18.6 A 5V Input 98.4% Peak Efficiency Reconfigurable Capacitive-
Sigma Converter with Greater than 90% Peak Efficiency for
the Entire 0.4~1.2V Output Range
Xu Yang, Linhu Zhao, Menglian Zhao, Zhichao Tan, Lenian He, Yong Ding,
Wuhua Li, Wanyuan Qu
Zhejiang University, Hangzhou, China
For the battery- or USB-powered portable smart devices, which supply their computing
cores with a wide-range sub-volt rail, the energy-efficient high and wide voltage-
conversion-ratio (VCR) converters are crucially important. In addition, low form factor
and decent transient responses are also favorable for such applications. Prior state-of-
the-art designs either use single-stage hybrid designs using multi-level or Dickson
converters [1-3], or adopt two-stage cascaded architectures with a highly efficient
unregulated front (or rear) stage [4], as shown in Fig. 18.6.1(left). The multi-level
designs, which conduct the full inductor current through all the on-state switches, are
suited to low-to-medium power levels with limited current density. The Dickson
converters take advantage of a high conversion ratio, however, at the cost of reduced
output voltage range. The two-stage designs which show decent output range and
efficiency, however, can suffer from heavy load efficiency degradation considering that
the efficiency of both stages degrade with increasing load and the overall efficiency which
is the product of the efficiencies of the two stages is severely degraded. Inspired by the
inductive-sigma converter [5] which shunts a highly efficient unregulated LLC with a
regulated Buck, this work proposes a reconfigurable capacitive-sigma converter. By
input-series and output-shunting a highly efficient unregulated switched-capacitor (SC)
converter with a reconfigurable Dickson hybrid Buck stage, the power stage input current
is reused and output currents are combined. Therefore, the overall efficiency is greatly
improved in a wide continuous VCR range and with an enhanced loading capacity.
Besides, as will be demonstrated, the proposed design shows inherently decent load
transient and regulation performances.
Figure 18.6.1(right) demonstrates the detailed power stage configuration of the proposed
reconfigurable capacitive-sigma converter, which consists of an unregulated 2:1 SC high-
side and a reconfigurable regulated low-side converter. The high- and low-side converters
operate independently with different clocks and phases and their output currents are
summed in parallel at the output. The high-side converter, powered by VH, consists of
on-chip switch MH1 to MH7 and external capacitors CH1 and CH2. Since the SC circuit always
work in a fixed 2:1 VCR, VH≈2VO always holds and the power transfer from VH to VO is
highly efficient. The low-side stage, powered by VL, composes of the on-chip switch ML1
to ML8, the external capacitors CL1 to CL3 and inductor L. The circuit forms a
reconfigurable 2-level (or 4-level) Dickson hybrid Buck converter and the duty cycle D
of the switches are controlled to generate the desired regulated VO. Compared with the
popular Dickson hybrid Buck converters, the proposed reconfiguration capability helps
the low-side converter maintain high efficiency over an even wider continuous VCR. Since
both high- and low-side converters share the same input current and sum their output
current in parallel, and both converters are inherently highly efficient, the proposed
converter shows superior efficiency and power density.
Figure 18.6.2 describes the steady-state operations of the high- and low-side converters.
For the high-side, during phase Φ1, the switches MH1, MH3, MH4, and MH7 turn on. The
capacitor CH1 is connected between VIN and VO in the charge state, and CH2 is connected
between the ground and the bottom of VH in the discharge state. During Φ2, the MH2,
MH5, and MH6 turn on with CH1 connected in series with CH2 and VO. According to the
charge balance of capacitors, the high-side converter constitutes a floating 2:1 VCR
between VH and VO, and the voltages across CH1 and CH2 are VIN–VO and VIN–2VO,
respectively. Since the high-side circuit works in fast and hard switching condition, a
continuous output current IOH with abrupt edges is expected. For the low-side, when the
output range is 0.8V<VO≤1.2V, the converter works in a 2-level Dickson mode, in which
the capacitors CL1, CL2, and CL3 are always shunted together. In ΦA, the capacitors are
connected between VL and SW with capacitors charged and inductor L magnetized. In
ΦB, the SW is grounded by ML5-ML8 and L demagnetized. Then, during ΦC, the
capacitors are connected between SW and ground with capacitors discharged and L
magnetized. Finally, the circuit enters ΦB again. By charge and volt-second balance, the
voltage across capacitors is VCL1,2,3=VL/2 and the low-side operates in 2-level Dickson
hybrid Buck mode with duty cycles controlling the regulated VO. Similarly, for
0.4V≤VO≤0.8V, the low-side converter works in 4-level Dickson hybrid Buck mode with
VCLi= VL×(4–i)/4, where i=1,2,3, with SW node switches between VL/4 and ground.
Therefore, the proposed low-side converter enables the reconfiguration of the popular
Dickson hybrid Buck converters and helps maintain high efficiency over a wide VCR
range.
308 • 2022 IEEE International Solid-State Circuits Conference
Figure 18.6.3 depicts the detailed driver and controller circuit implementations. Here, all
the power switches are implemented with 1.8V devices (Vds,max=1.98V) and all the
controller, drivers and bootstrap capacitors are integrated on chip. The MH1 to MH3 and
ML1 are driven by the internal PMOS type floating regulators and the ML2 to ML4 are driven
by NMOS type floating regulators, as indicated in Fig. 18.6..3. The MH4 to MH7 and ML5
to ML8 adopt the typical half-bridge drivers which are not shown.
The prototype is fabricated in a 0.18μm BCD process and is verified with a typical 5V
input and 0.4-to-1.2V output. Figure 18.6.4(left) shows the measured high- and low-side
output currents IOH and IOL when VO=1V and IO=500mA. Here, IOH and lOL deliver 200mA
and 300mA, respectively, as expected by IOH/IOL=VH/VL. Figure 18.6.4(right) shows the
startup and the steady-state waveforms when the low-side works in 2-level and 4-level
hybrid Dickson modes, respectively. From the measurements, when VO=1.2V and low-
side is in 2-level Dickson, the swing of the high-side SWH1 and SWH2 both equal to
VO=1.2V. The low-side SWL1 to SWL3 are shunted together with a swing of VL/2=(5–
2×1.2)/2=1.3V observed. For VO=0.8V with low-side in 4-level Dickson, the swing of
SWH1 and SWH2 equal to VO=0.8V. The SWL1 to SWL3 are split with a swing of VL/4=(5–
2×0.8)/4=0.85V. Besides, the high and low-side clock frequencies are 500kHz and 1MHz,
respectively.
Figure 18.6.5 (top) shows the measured line transient and dynamic voltage scaling
performances. When VIN steps from 4V to 5V, the high-side switching nodes SWH1 and
SWH2 remain equal to VO=0.4V while the low-side switching nodes self-balanced to higher
voltages. When the VO scales between 0.4V and 0.8V, the SWH1 and SWH2 stay equal to
VO with the low-side self-balanced. Both measurements indicate the desired high-side
unregulated and low-side regulated operations. Figure 18.6.5(bottom) gives a full-range
load transient from 0 to 2A with 5V input and 0.6V output. VO shows a static error of
1.1mV and under/overshoot voltages of –23mV and 23.8mV with 0.1% settling time of
25μs and 30μs, respectively. Benefited from the shunting of unregulated SC high-side
and regulated low-side, the converter shows inherent low output impedance, which
results in decent regulation and load transient performances, even for the conventional
voltage-mode control used here.
Figure 18.6.6 shows the measured efficiency, the simulated power loss breakdown and
the comparison table. The converter achieves a peak efficiency of 98.4% at 1.2V output.
For the entire 0.4-to-1.2V output range, the converter shows greater than 90% peak
efficiency. The conduction loss of high- and low-side converters is 41.66% and 16.24%,
respectively and bonding wire losses contribute about 25.18% when IO =2 A. Compared
with the state-of-the-art designs listed in the comparison table, the proposed work
improves the peak efficiency by 1.5% at VCR=4.2 and 4.9% at VCR=12.5. Besides, a
load capacity of 2A and a die-area current density of 0.345A/mm2 is obtained. In
summary, in spite of the low-performance wire bond packaging type used here, the
proposed reconfigurable capacitive-sigma converter shows the highest peak efficiency
and the broadest high efficiency VO range among the listed prior arts. The loading capacity
and current density is also superior to most of the prior works.
Figure 18.6.7 shows a die micrograph with an area of 1.96×2.96mm2 with all the power
switches, drivers, bootstrap capacitors and controller integrated on chip. The inductor
volume is 7×6.9×3.8mm3 with all flying caps in 0402 package.
Acknowledgement:
This work is supported by National Key Research and Development Program of China
under Grant 2021YFB2401600.
References:
[1] W. Liu et al., “A 94.2%-Peak-Efficiency 1.53A Direct-Battery-Hook-up Hybrid Dickson
Switched-Capacitor DC-DC Converter with Wide Continuous Conversion Ratio in 65nm
CMOS,” ISSCC, pp. 182-183, Feb. 2017.
[2] C. Schaef et al., “A 93.8% Peak Efficiency, 5V-Input, 10A Max ILOAD Flying Capacitor
Multilevel Converter in 22nm CMOS Featuring Wide Output Voltage Range and Flying
Capacitor Precharging,” ISSCC, pp. 146-147, Feb. 2019.
[3] J. Rentmeister and J. Stauth, “A 92.4% Efficient, 5.5V:0.4-1.2V, FCML Converter with
Modified Ripple Injection Control for Fast Transient Response and Capacitor balancing,”
IEEE CICC, pp. 1-4, Mar. 2020.
[4] Z. Xia and J. Stauth, “A Two-Stage Cascaded Hybrid Switched-Capacitor DC-DC
Converter with 96.9% Peak Efficiency Tolerating 0.6V/μs Input Slew Rate During
Startup,” ISSCC, pp. 256-257, Feb. 2021.
[5] M.H. Ahmed et al., “Single-Stage High-Efficiency 48/1 V Sigma Converter with
Integrated Magnetics,” IEEE Trans. Industrial Electron., vol. 67, no. 1, pp. 192-202, Jan.
2020.
978-1-6654-2800-2/22/$31.00 ©2022 IEEE
 ISSCC 2022 / February 23, 2022 / 9:20 AM

Figure 18.6.1: Prior work and the proposed reconfigurable capacitive-sigma

converter. Figure 18.6.2: The steady-state operation principles of the proposed converter.

18

Figure 18.6.4: The measured output current waveforms (left) and the switching nodes
Figure 18.6.3: The driver and controller circuit implementations. and VO during the power on and steady-state operations(right).

Figure 18.6.5: Measured switching nodes waveforms during the line transient and
dynamic voltage scaling (top) and the full-range (0 to 2A) load transient responses Figure 18.6.6: Measurement efficiency curves, simulated power loss breakdown, and
(bottom). performance summary.

DIGEST OF TECHNICAL PAPERS • 309

 ISSCC 2022 PAPER CONTINUATIONS

Figure 18.6.7: Die micrograph.

• 2022 IEEE International Solid-State Circuits Conference 978-1-6654-2800-2/22/$31.00 ©2022 IEEE

ISSCC 2022 / SESSION 18 / DC-DC CONVERTERS / 18.7
18.7 A 2−5MHz Multiple DC Output Hybrid Boost Converter with
Scalable CR Boosting Scheme Achieving 91% Efficiency at a
Conversion Ratio of 12
Chen Chen, Jin Liu, Hoi Lee
University of Texas at Dallas, Richardson, TX
High conversion-ratio (CR) DC-DC boost converters are essential for LED backlighting
in smartphone and tablet displays. For realizing a high CR, a conventional boost (CB)
converter [1] shown in Fig. 18.7.1 would use a large duty ratio D and thus have short
on-time of power switch S2. This not only limits the converter switching frequency fSW
but also results in a large inductor current ripple ΔiL. As high CR also leads to a large
average inductor current IL under a given output current IO, the power efficiency of the
CB converter would be significantly degraded due to enlarged inductor conduction loss
with large ΔiL and IL. Hybrid boost converters are recently reported. Both converters in
[2,3] add a capacitor path in parallel with the inductor to reduce the inductor current
stress, while a two-phase converter in [4] doubles its switching pulse width and fSW
through 2-phase operation with 2 inductors. However, compared with the CB converter,
their improvements in CR are limited within 2 times. Moreover, output-voltage-rated
power transistors that have larger on-resistance and parasitic capacitance are required
in prior hybrid boost converters [2-4], resulting in higher power losses and inferior
performances in high frequencies.
To address above issues, this paper presents a hybrid boost converter with a scalable
CR boosting (SCRB) scheme. As shown in Fig. 18.7.1, the proposed converter consists
of an inductor L, a freewheeling switch S0A, and N SC units for boosting the CR, where
N is an integer larger than 0. Each SCRB unit has two complementary switches (SiA, SiB)
and two flying capacitors (CiA, CiB), where i = 1, 2,…, N. The proposed converter has two
operation states φA and φB and offers the following benefits. (1) As each SCRB unit
produces a DC output, there are a total of N DC outputs VO1, VO2,…, VON in the proposed
converter with N SCRB units for driving LEDs or other functions. (2) Since the output
voltage VON of the proposed N-stage converter is (N+1–D)VIN/(1–D), its CR is (N+1–D)
times larger than that of the CB converter and is scalable with N. Suppose N = 3, the CR
improvement at VO3 can be 3 to 4 times when D varies from 1 to 0. This CR boosting not
only outperforms that of the prior art [2-4], but also reduces the required duty ratio D to
allow a higher fSW and a lower ΔiL under high CR conditions. (3) The voltage stress VDS
of all power switches is the same and equals VON/(N+1–D) [=(VON–VIN)/N], which provides
(N+1–D) times reduction compared with that of the CB converter as shown in Fig. 18.7.1.
Hence, all power switches in the proposed converter can be implemented by low-voltage-
rating transistors that offer smaller on-resistance RDS,ON and output charge QOSS for
reducing different power losses. (4) Voltages across all flying capacitors are no more
than VON/(N+1–D), so that low-voltage-rating capacitors with lower ESL values can be
used to reduce voltage ringing at the switching nodes. (5) There are three parallel input
paths in the proposed converter. With flying capacitors sharing the input current, storing
and transferring energy together with the inductor, the required IL is reduced. By lowering
both ΔiL and IL, the inductor conduction loss can be minimized.
To demonstrate different features, the proposed 4-stage converter (i.e., N=4) was
designed with its structure and two operation states shown in Fig. 18.7.2. In state φA,
S0A to S4A are turned on, so L and C1A are charged and store energy from VIN. Similarly,
S1B to S4B are turned on such that L and C1A are discharged to transfer energy to the
output in state φB. All flying capacitors can be self balanced in the steady state. When
CR is 10, the duty ratios of the proposed converter and the CB converter are 0.55 and
0.9, respectively. Hence, the on-time, TON, of power switches during inductor discharging
state in the proposed converter is 0.45TS, and is 4.5 times larger than that of the CB
converter. Meanwhile, the voltage stress of each power switch is reduced to VO4/(5–D),
which is 4 to 5 times smaller than the output voltage.
310 • 2022 IEEE International Solid-State Circuits Conference
Figure 18.7.3 illustrates the schematic of the proposed 4-stage hybrid boost converter
that produces VO4 up to 24V in this work. Due to low voltage stress across power
transistors and flying capacitors, all power transistors except S4B are realized by on-chip
5V NMOS transistors that have 3 times smaller RDS,ON and COSS than 24V devices, while
low-voltage-rating reverse geometry SMD capacitors with significantly lower ESL and
DCR are utilized as flying capacitors. For driving power switches, in contrast to the
conventional bootstrap circuitry, the gate drive swings for power transistors S1A to S4A,
and S1B to S3B are provided by the same steady-state capacitor voltage (VO4–VIN)/4 (~5V)
of C2A to C4A, and C1B to C4B without using any extra off-chip bootstrap capacitors and
diodes. As shown in Fig. 18.7.3, for S3A and S3B, the gate swing of S3A is provided by
voltage across C3B, while the gate swing of S3B is given by voltage across C4A. The voltage
across C4A is charged by C3B through S4A in phase φA without using any diode. For the
NMOS S4A and PMOS S4B pair, the supply of their drivers is supported by C4B. The gate
driver of low-side NMOS S0A and the controller are powered by two external voltages
VDDL and VDDC of 5V.
Figure 18.7.4 shows the start-up process to precharge all flying capacitors. Initially,
voltage across all flying capacitors is 0 and transistors S1A to S4A, and S1B to S4B are off.
Body diodes of S1A to S4A, and S1B to S4B help precharge capacitors automatically through
controlling S0A with 2 operation states φSA and φSB. Specifically, in state φSA, a square-
wave signal EN_CLK with a duty ratio DS turns on S0A such that VSW0 is clamped to 0 and
C1A to C4A are charged via body diodes D1A to D4A. In state φSB, S0A is turned off, so VSW0
is increased to VS [=VIN/(1–DS)] based on the inductor volt-second balance. Voltages
VSW1 to VSW4 stack on VS to allow C1A to C4A charging C1B to C4B via body diodes D1B to
D4B. After a few cycles, C1A voltage would reach (VIN–VD) and the voltage of other
capacitors becomes (VS–2VD), where VD is the body diode voltage. Meanwhile, a
bootstrap voltage detector continues to monitor the voltage VC4B across C4B during start-
up. Once VC4B reaches 2V, transistor MP is turned on to assert signal EN for ending the
start-up mode. After that, PWM signals from the controller would pass to the gate drivers
for controlling the power transistors. The simulated start-up waveforms are depicted in
Fig. 18.7.4.
The proposed 4-stage hybrid boost converter was fabricated in a 0.18μm HV CMOS
process. Figure 18.7.5 shows the measured steady-state waveforms under different
frequencies with IO of 50mA. The converter realizes CR=12 and D=0.66 under VIN=1.8V
at fSW = 2MHz, whereas CR=10 and D=0.55 are achieved under VIN=2V at fSW=5MHz. Four
DC outputs are generated as 7V, 12V, 17V, and 22V when VIN=1.8V, the output ripple at
VO4 is 50mV, and IL is 470mA. The measured switching node waveforms prove the same
voltage stress of 5V across all power transistors when CR=12, and 4.5V when CR=10.
Figure 18.7.6 shows that the peak power efficiencies of the proposed converter are 93.2%
at VIN=3V, CR=6.5, IO=120mA, and fSW=2MHz; 91% at VIN=1.8V, CR=12, IO=75mA, and
fSW = 2MHz; and 86.8% at VIN=3V, CR=7.5, IO=105mA, and fSW=5MHz. Figure 18.7.6 also
provides performance comparisons between the proposed converter and state-of-the-
art designs [1-4]. Among the state-of-the-art designs listed, the proposed converter has
the lowest voltage stress across power transistors, provides four DC outputs, and
achieves the highest CR and fSW with competitive peak power efficiencies. The chip
micrograph and converter prototype are shown in Fig. 18.7.7.
References:
[1] T.H. Kong, S.W. Hong, and G.H. Cho, “A 0.791 mm2 On-Chip Self-Aligned Comparator
Controller for Boost DC-DC Converter Using Switching Noise Robust Charge-Pump,”
IEEE JSSC, vol. 49, no. 2, pp. 502-512, Feb. 2014.
[2] S.U. Shin et al., “A 95.2% Efficiency Dual-Path DC-DC Step-Up Converter with
Continuous Output Current Delivery and Low Voltage Ripple,” ISSCC, pp. 430-431,
Feb. 2018.
[3] Y.A. Lin et al., “A High-Conversion-Ratio and 97.4% Peak-Efficiency 3-Switch Boost
Converter with Duty-Dependent Charge Topology for 1.2A High Driving Current and 20%
Reduction of Inductor DC Current in MiniLED Applications,” ISSCC, pp. 272-273,
Feb. 2021.
[4] M. Huang, Y. Lu, and R.P. Martins, “A 2-Phase Soft-Charging Hybrid Boost Converter
with Doubled-Switching Pulse Width and Shared Bootstrap Capacitor Achieving 93.5%
Efficiency at a Conversion Ratio of 4.5,” ISSCC, pp. 198-199, Feb. 2020.
978-1-6654-2800-2/22/$31.00 ©2022 IEEE
 ISSCC 2022 / February 23, 2022 / 9:30 AM

Figure 18.7.1: Structure and features of the conventional boost converter and the Figure 18.7.2: Proposed 4-stage hybrid boost converter: structure, two operation
proposed multi-stage hybrid boost converter with scalable CR boosting (SCRB) states, and its characteristics of inductor current, voltage stress of power switches
scheme. and conversion ratio.

18

Figure 18.7.4: Start-up mechanism to precharge flying capacitors, start-up controller,

Figure 18.7.3: Schematic and bootstrap circuity of the proposed 4-stage hybrid boost and simulated transient waveforms to demonstrate operation from start-up to steady
converter with design considerations of power transistors and flying capacitors. states.

Figure 18.7.6: Measured power efficiencies, and performance comparisons between

Figure 18.7.5: Measured waveforms of the proposed 4-stage hybrid boost converter. the proposed and state-of-the-art boost converters.

DIGEST OF TECHNICAL PAPERS • 311

 ISSCC 2022 PAPER CONTINUATIONS

Figure 18.7.7: Micrograph and PCB prototype of the proposed 4-stage hybrid boost
converter.

• 2022 IEEE International Solid-State Circuits Conference 978-1-6654-2800-2/22/$31.00 ©2022 IEEE

ISSCC 2022 / SESSION 18 / DC-DC CONVERTERS / 18.8
18.8 A Battery-Input Sub-1V Output 92.9% Peak Efficiency
0.3A/mm2 Current Density Hybrid SC-Parallel-Inductor Buck
Converter with Reduced Inductor Current in 65nm CMOS
Guigang Cai1, Yan Lu1, Rui Martins1,2
1
University of Macau, Macau, China
2
University of Lisboa, Lisbon, Portugal
The profile of portable and wearable devices keeps shrinking, demanding high current
density power management integrated circuits. Switched-capacitor (SC) converters and
buck converters are two common solutions. Unregulated SC converters can achieve high
power density and high efficiency for specific voltage conversion ratios (VCRs). However,
to cover wide input and output voltage ranges, they require a reconfigurable topology
with multiple VCRs, thus increasing the system complexity. On the other hand, buck
converters can reach a good efficiency over a wide continuous VCR range. Yet, they need
a bulky inductor, which significantly degrades the power density. To address the power
density and efficiency tradeoff, hybrid converters composed of both inductor and
capacitor are among popular solutions [1-4]. When compared with the traditional buck
converter, these hybrid converters feature lower voltage swing (smaller current ripple)
of the inductor, higher switching frequency, and a larger duty cycle (D) for the same
VCR, alleviating the requirements on the inductor, and resulting in higher power density.
Nevertheless, as all the output current IOUT goes through the inductor, this implies a large
volume for small DCR and conduction loss PCOND_L. Recently, hybrid converters with
reduced inductor current IL have emerged [5-7]. In these hybrid converters, the SC not
only lowers down the voltage of the switch node, but also offers another current path to
the output, reducing the inductor current. In this work, we propose an SC-parallel-
inductor buck topology (which we refer to as CPL-Buck since in the proposd structure
there is a capacitor that is always in parallel with the inductor) that can further reduce IL
to less than 0.5IOUT, meaning a PCOND_L reduction of over 75% for the same DCR.
Measurement results show that, for 1.2A maximum IOUT, 3-to-4.2V input to 0.6-to-1V
output, the proposed CPL-Buck obtains a peak efficiency of 92.9% and a peak current
density of 0.3A/mm2 with a power inductor as small as 1.6×0.8×0.8mm3.
The proposed CPL-Buck, mainly consists of 1 inductor L, 2 fly capacitors CF1 and CF2, 6
switches S1-6, and 1 output capacitor COUT. Figure 18.8.1 shows the working principle of
the proposed CPL-Buck converter with a two-phase operation. For the sub-1/3× mode,
in Φ1, CF1 is charged in series with L, and CF2 discharges to VOUT. In Φ2, L de-energizes,
and CF1 charges CF2. Here, CF1 and CF2 operate as an SC with VCF1=2VOUT and VCF2=VOUT. In
other words, the fly capacitor voltages only relate to VOUT instead of VIN, which is essential
to attain high efficiency for an arbitrary VOUT. CF1 reduces the voltage stress on L, while
CF2 is always in parallel with L, reducing the current stress on L. As mentioned earlier,
this is the reason why we designate the structure as CPL-Buck converter. As there are
always two paths delivering currents to the output in both phases, IL is only IOUT/(1+2D),
significantly reducing the conduction loss on L. As VOUT=DVIN/(1+2D), ideally, the
maximum VOUT is VIN/3, then we name it the sub-1/3× mode. Although there is hard
charging in Φ1 and Φ2, we can minimize the charge redistribution loss with large CF1 and
CF2, which is more area-efficient when compared with the utilization of a large power
inductor. By doing so, the loss is dominated by the conduction losses of the switch on-
resistances and the ESR of the capacitors. In this design, CF1 and CF2 are 4.7μF which is
sufficiently large for 1.2A IOUT. To cover a wider VCR, we implement a sub-1/2× mode by
keeping S4 and S5 constantly ON and S6 constantly OFF. In this mode, VOUT=DVIN/(1+D),
and IL is IOUT/(1+D).
Figure 18.8.2 presents the full schematic of the proposed CPL-Buck with the control
circuits. Among the switches, we design S1 by stacking two 2.5V PMOS transistors, S2
and S3 by stacking one 2.5V and one 1V NMOS transistors, and S4 to S6 are 1V NMOS
transistors. For mode selection, the ramp generator outputs two clock signals clk_80
and clk_40 with duty cycles of 80% and 40%, respectively. The comparison between the
reference voltage VREF and the divided VIN mainly determines the operation mode. Next,
we will discuss in Fig. 18.8.3 the duty cycle limitations.
Figure 18.8.3(top left) shows the IL and PCOND_L reduction curves for a VCR range of 0.05
to 0.45. We can see the reduction of IL to 0.4IOUT and PCOND_L by 84% at a VCR of 0.3 in
the sub-1/3× mode. In this design, with a VCR range between 1/7 and 1/3, IL will decrease
to 0.4 to 0.71 of IOUT, meaning 84% to 49% reduction in PCOND_L. Consequently, we can
use a much smaller inductor volume with a larger DCR to maintain the same value of
PCOND_L. Although the always-dual-path (ADP) hybrid converter in [7] can reduce IL to a
fixed 0.5IOUT in its 2-phase mode, the inductor current ripple is much larger than the
proposed CPL-Buck converter. From Fig. 18.8.3(top right), at a VCR range of 0.16 to
0.3, the current ripple of [7] is 1.78 to 3.2× of the proposed CPL-Buck. As a result, to
keep the same current ripple, [7] needs a larger inductance, resulting in a larger inductor
volume or higher DCR. This, in turn, compromises the advantage of IL reduction when
312 • 2022 IEEE International Solid-State Circuits Conference
calculating PCOND_L. In addition, the proposed CPL-Buck has a comparable inductor
current ripple performance when compared with the 3-level buck converter, while the
proposed CPL-Buck can significantly reduce the inductor current and has no flying
capacitor balancing issue.
Ideally, VOUT=DVIN/(1+2D) in the sub-1/3× mode, and increasing D will result in a higher
VOUT. However, this is not always the case if D is too large, when we account for the
inductor DCR and the switch on-resistances. From Fig. 18.8.3(bottom), VOUT depends
on both D and IOUT for a given DCR and on-resistance. With a heavy load condition,
increasing D will first help VOUT to reach a peak value, and then further increasing D will
lead to a VOUT drop. This issue can result in a control error. When the control circuit finds
VOUT is lower than VREF, and the current D exceeds the effective D range, the controller
will direct D to 1 and VOUT will drop rapidly. Here, we set the maximum duty cycle DMAX
to 0.8 in the sub-1/3× mode. When D>0.8 lasts for 32T, where T is switching period, the
converter will switch to the sub-1/2× mode. Furthermore, when D<0.4 lasts for 32T, it
will switch to the sub-1/3× mode. The operation mode changes automatically by the
mode selector with designed DMAX and the D hysteretic window according to the DCR
and the on-resistance.
This work, fabricated in 65nm CMOS, occupies an area of 2.72mm2. To minimize the
parasitic inductance of the fly capacitors, CF1 and CF2 are surface mount capacitors with
a 0402 package and are directly soldered on-die. Figure 18.8.4 plots the measured
steady-state waveforms in both the sub-1/3× mode and the sub-1/2× modes. In the sub-
1/3× mode, the average inductor current IL_AVG is 570mA with VIN=4.2V, VOUT=1V, and
IOUT=1.2A, exhibiting a 52.5% reduction. The reduction is higher than the ideal case
because D has to be larger in a heavy load condition due to the inductor DCR and the
switch on-resistances. In the sub-1/2× mode, IL_AVG=730mA with VIN=3V, VOUT=1V, and
IOUT=1.2A, showing a 39.2% reduction. The measured under/overshoot are 50mV/40mV
when IOUT changes between 0.2A and 1.2A with an edge time of 1μs. This converter also
shows a good reference tracking performance. Figure 18.8.5 displays the measured
efficiency at various input and output conditions. We can observe that the circuit obtains
the peak efficiency of 92.9% with VIN=3V and VOUT=0.8V, and of 92.7% with VIN=4.2V
and VOUT=1V. In addition, we can conclude that for VOUT=1V, the efficiency of VIN=3.8V is
higher than that of VIN=3.4V. This happens because the converter works in the sub-1/3×
mode when VIN=3.8V and in the sub-1/2× mode when VIN=3.4V. Resulting from the IL
reduction, we can use a 470nH inductor with a size as small as 1.6×0.8×0.8mm3 while
still holding high efficiency. Compared with prior arts shown in Fig. 18.8.5(bottom right),
this work achieves high efficiency and the highest current density. Figure 18.8.6 presents
the performance summary and comparison with state-of-the-art works. This work uses
the smallest inductor size, and obtains the highest current density among the listed works
(for fair comparison, we adopt the total area counting method in [4]). The peak efficiency
of 92.9% is only second to [4], but with a 3× higher current density. In conclusion, by
offering an SC path in parallel to the power inductor, the proposed CPL-Buck significantly
reduces the inductor current without enlarging the current ripple, achieving high
efficiency and high current density. Figure 18.8.7 shows the chip micrograph with CF1
and CF2 attached on-die, and the compact PCB solution.
Acknowledgment:
This work is supported by the Science and Technology Development Fund, Macau SAR
under Grants 0093/2019/A2 and SKL-AMSV(UM)-2020-2022. The authors would like to
thank Ziyu Xia from Dartmouth College for sharing his on-chip soldering skill.
References:
[1] W. Liu et al., “A 94.2%-Peak-Efficiency 1.53A Direct-Battery-Hook-up Hybrid Dickson
Switched-Capacitor DC-DC Converter with Wide Continuous Conversion Ratio in 65nm
CMOS,” ISSCC, pp. 182-183, Feb. 2017.
[2] J. S. Rentmeister and J. T. Stauth, “A 92.4% Efficient, 5.5V:0.4-1.2V, FCML Converter
with Modified Ripple Injection Control for Fast Transient Response and Capacitor
Balancing,” IEEE CICC, pp. 1-4, Mar. 2020.
[3] A. Abdulslam and P.P. Mercier, “A Symmetric Modified Multilevel Ladder PMIC for
Battery-Connected Applications,” IEEE JSSC, vol. 55, no. 3, pp. 767-780, Mar. 2020.
[4] Z. Xia and J. Stauth, “A Two-Stage Cascaded Hybrid Switched-Capacitor DC-DC
Converter with 96.9% Peak Efficiency Tolerating 0.6 V/μs Input Slew Rate During
Startup,” ISSCC, pp. 256-257, Feb. 2021.
[5] C. Hardy and H.-P. Le, “A 10.9 W 93.4%-efficient (27W 97%-Efficient) flying-inductor
hybrid DC-DC converter suitable for 1-Cell (2-Cell) battery charging applications,” ISSCC,
pp. 150-151, Feb. 2019.
[6] N. Tang et al., “Fully Integrated Buck Converter with 78% Efficiency at 365mW Output
Power Enabled by Switched-Inductor Capacitor Topology and Inductor Current Reduction
Technique,” ISSCC, pp. 152-153, Feb. 2019.
[7] J. Ko et al., “A 4.5 V-Input 0.3-to-1.7 V-Output Step-Down Always-Dual-Path DC-DC
Converter Achieving 91.5%-Efficiency with 250mΩ-DCR Inductor for Low-Voltage SoCs,”
IEEE Symp. VLSI Circuits, pp. 1-2, June 2021.
978-1-6654-2800-2/22/$31.00 ©2022 IEEE
 ISSCC 2022 / February 23, 2022 / 9:40 AM

Figure 18.8.1: Working principle of the proposed CPL-Buck converter. Figure 18.8.2: Full schematic of the proposed CPL-Buck converter.

18

Figure 18.8.3: Inductor current reduction and DCR conduction loss reduction, current Figure 18.8.4: Measured steady-state waveforms of the sub-1/3X mode and the sub-
ripple performance, simulated VOUT drop, and mode switch scheme. 1/2X mode, load transient response and reference tracking response.

Figure 18.8.5: Measured efficiencies of the proposed CPL-Buck, and performance

comparison with state-of-the-art works. Figure 18.8.6: Performance summary and comparison with state-of-the-art works.

DIGEST OF TECHNICAL PAPERS • 313

 ISSCC 2022 PAPER CONTINUATIONS

Figure 18.8.7: Chip micrograph and PCB of the proposed hybrid buck converter. The
power inductor is on the back-side of the PCB, underneath the chip.

• 2022 IEEE International Solid-State Circuits Conference 978-1-6654-2800-2/22/$31.00 ©2022 IEEE