Constant Common-Mode Voltage Transformerless
Inverter for Grid-Tied Photovoltaic Application
Md N. H. Khan1, Yam P. Siwakoti1, L. Li1, and F. T. K. Suan2
1School of Electrical and Data Engineering, University of Technology Sydney, Sydney, Australia
2
School of Engineering, Asia Pacific University of Technology and Innovation, Kuala Lumpur, Malaysia
Email : MdNomanHabib.Khan@student.uts.edu.au, Yam.Siwakoti@uts.edu.au, Li.Li@.uts.edu.au, and freddy.tan@apu.edu.my
Abstract— This paper proposes a new H-bridge clamped
transformerless inverter for the grid-connected Photovoltaic
(PV) application. The clamping circuit consists of two switches
and a full bridge diodes, which can clamp the AC terminal
voltage to the DC midpoint during the freewheeling period. As
a result, the common mode voltage (CMV) is held constant,
which makes it a suitable candidate for the grid-connected PV
system. Furthermore, the efficiency of the proposed topology is
relatively higher than other topologies. The operating principle
of the proposed topology is analyzed in brief. Thermal modeling
for the proposed topology has presented for loss calculation.
Finally, the theoretical analysis is validated with simulation and
experimental results. Validation is carried out using PLECS
simulation and experimental results.
Keywords— PV panel, CMV, Inverter, Mid-point clamping.
I. INTRODUCTION
Solar photovoltaic (PV) is one of the cleanest, readily and
widely available energy sources among all renewable energies
[1]. With technological advancements in material and
manufacturing techniques, the cost of the PV system is
continuously reduced, making it the cheapest energy source
for massive deployment in the future. Many countries (USA,
Germany, China, Japan, Australia, France, Italy, Spain, etc.)
have already begun to reap the benefits through their increased
adoption and integration of this system in the utility grid.
According to the 2018 annual report of the International
Energy Agency-Photovoltaic Power Systems Program (IEA-
PVPS) [2], the global installed PV capacity reached a 100 GW
milestone in 2012, and a 200 GW level in 2015. By the end of
2018, the total installed PV capacity was estimated to be
roughly 531.7 GW, while 24 IEA-PVPS countries reached
264 GW [2]. Fig. 1 shows the cumulative installed PV
capacity of the top IEA-PVPS countries from 2012 to 2018.
From this figure, it is evident that the PV industry is exhibiting
a rapid growth in five developed countries accounting 90.1%
of all PV installations in 2018. Among them, China, USA, and
Japan experienced the largest installed PV installation
capacity increment in recent years.
Photovoltaic (PV) systems are generally categorized into
two types: stand-alone and grid-connected systems. The
stand-alone PV system is the direct connection to the electrical
application, which is integrated with an energy storage
system. On the other hand, the grid-tied PV system is widely
used for direct transmission, distribution, and consumption
[3]. The grid-connected PV application can be transformer
based or transformerless inverter. Transformer-based inverter
topologies are either operated at a low frequency (LF) or high
frequency (HF). If the system uses a LF transformer, then the
system becomes bulky, heavy, and thus expensive. It also
978-1-7281-0395-2/19/$31.00 ©2019 IEEE
reduce the system efficiency due to winding power losses. On
the other hand, even though size and weight can be reduced
dramatically for HF transformer, the efficiency remains low
due to multiple converter stages [3].
Fig. 1. Cumulative PV installations for the top IEA-PVPS countries
from 2012 to 2018 [2].
Nowadays to achieve high efficiency, low cost and high
power density, the concept of transformerless inverters are
growing rapidly [4]. However, the challenging part in the
transformerless solution is the common-mode (CM) issue,
which causes to flow more leakage current, e.g. in unipolar
full-bridge inverter [4]. Therefore, for the transformerless PV
system some safety requirements are required to be met
according to some of the standards such as DIN VDE V 0-
126-1-1, and IEC 62109-2, where both set the leakage current
to be less than 300 mA [5]. To eliminate the CM leakage
current during the freewheeling period, many topologies are
proposed in literature such as DC bypass topologies (i.e., H5,
Hybrid, and H6), and AC bypass topologies (i.e., HERIC) [6-
9]. However, such topologies carrying the CM leakage current
due to junction capacitor of the power switches. As a result,
active clamping-based topologies have been introduced to
mitigate the leakage current effectively, such as HB-ZVR,
HB-ZVR-D, oH5, and PN-NPC [10-15]. Considering all these
aspects, a new H-bridge clamped transformerless inverter is
presented in this paper to obtain high efficiency and low
leakage current with constant CMV.
The rest of the paper is organized as follows: proposed
topology with its conversion structure and operation
principles is presented in Section II. Further, a comparative
analysis of the proposed topology with existing selected
single-phase transformerless inverter topologies are discussed
in Section III. This is followed by simulation and experimental
results in Section IV. Finally, conclusion is made in Section V
to summarize the findings and results.
616
 II. PROPOSED INVERTER ANALYSIS
0 CPV1 +
Q1 Q2
A. Circuit configuration Q5

A simple modified H-Bridge Zero Voltage Switch D1 D2

Controlled Rectifier (HB-ZVSCR) is presented with very low A L1
P C Vgrid
CM effect and high efficiency. This topology is modified PV L2 o
topology of both HB-ZVR [9] and HB-ZVR-D [10]. The D3 D4 B
topology replaced two diodes of HB-ZVR-D with two extra C2 0
switches and removed the bidirectional switches, which Q3 Q4
Q6
creates a freewheeling path and further reduces the loss. 0 CPV2 -
Fig. 1 (a) shows the schematic circuit diagram of a N
proposed transformerless inverter topology (HB-ZVSCR) (a)
with the modulation pulses (see in Fig. 1 (b)).
0 CPV1 +
Q1 Q2
Q5
0 CPV1 +
Q1 Q2
C1 Q5 D1 D2

P A L1
C Vgrid
D1 D2 PV L2 o
A L1 D3 D4 B
C Vgrid C2
PV P L2 o 0
D3 D4 B Q3 Q4
C2 0 Q6
Q3 Q4 0 CPV2 -
Q6
N
0 CPV2 -
N
(b)

(a)
0 CPV1 +
Q1 Q2
Modulation Reference Carrier Signal Q5

D1 D2 A
t
P L1
Q1, Q4 C Vgrid
PV B L2 o
D3 D4
C2 0
Q2, Q3 t
Q3 Q4
Q6
0 CPV2 -
Q5, Q6 t N

(c)
t

(b) 0 CPV1 +
Q1 Q2
Fig. 1. The proposed H-bridge transformerless inverter, (a) circuit Q5
configuration of HB-ZVSCR, and (b) its switching pattern.
D1 D2
A
B. Operation principle P L1
C Vgrid
PV B L2 o
The proposed inverter has four operational modes that are D3 D4
shown in Fig. 2(a) to Fig. 2(d). The mode 1 is an active state C2 0
of the positive half cycle (see Fig. 2(a)). In this cycle, S1 and Q3 Q4
S4 are conducting, and other switches and diodes are off and Q6
0 CPV2 -
current flow through the filter and load. As a result, the voltage
N
in between point “A” to neutral (N) is equal to the DC link
voltage (VPV). On the other hand, at mode 2, S2 and S3 are (d)
active in the negative half cycle (see Fig. 2(b)). So the voltage
in between point “B” to neutral (n) is equal to the DC link Fig. 2. Operating modes of HB-ZVSCR inverter, (a) mode 1, (b) mode
2, (c) mode 3, and (d) mode 4.
voltage (VPV). The freewheeling path for positive cycle
demonstrations in Fig. 2 (c) and diodes D2, D4 is forward bias:
hence, both are on and output current is flowing through these At positive and negative half cycle, the voltage at point
two diodes and the switches S5 and S6. In the negative half “B” to “N” and “A” to “N” is zero, so the common mode
cycle, the freewheeling path expressions in Fig. 2(d). The voltage is achieved half of the DC link voltage (see equation
other two diodes are in forwarding mode, and current goes (1)-(4)).
through D1, D4 and the switches S5 and S6.
+
= (1)
2

617
 +0 ( ) = ( ). ( )
(positive half cycle) = =
2 2 (2)
( ) (6)
( ) =
0+ ( )
(negative half cycle) = = (3)
2 2 ( ) = ( ) (7)

+
2 2 The maximum allowable power dissipation ( ) can be
(zero Vector states) = =
2 2 (4) calculated by the junction temperature which is
shown in (8), where represents the ambient temperature
and is the junction temperature.
C. Thermal analysis The ambient temperature can be found by (9),
The power semiconductor devices are playing a vital role −
in the loss, efficiency, reliability, and cost. As a result, the = (8)
( )
thermal analysis is important part to design an inverter. Fig.
3 shows the thermal equilibrium model of the proposed
inverter. The junction temperature ( ) of the power module = − Z ( ) P +P +P (9)
can be estimated from the loss information. Once the power Where, =P +P +P
losses are determined, they are conducted through their
junction to case thermal impedance ( ) ,which depends
Where, Z ( ) stands the thermal resistance between
on the thermal RC ( ( ) and ( ) ) mode which can
the radiator and the environment. Moreover, P is the
be Cauer and Foster network. [17-20]. In (5) shows the
MOSFET power losses, P is the power losses of the anti-
Foster-network thermal impedance.
parallel diode of the MOSFET, and P is the diode power
losses.
Zth (H-A)

TH TH
TA Now the copper loss through the filter inductors ( and
Zth (C-H) Zth (J-C) Zth (J-C) Zth (C-H)
TC TJ TJ TC ) can be expressed in (10) and (11).
PL_PD
PL_M

(10)
1
P = ( )
+
MCf
RMf

CPV1

0 C1 A (11)
Vin RC1 W1 + 1
PV Vgrid
= ( )
M Co
-
C2 B RC2 W2
- Inverter Where, is the grid current and the internal inductor
MCf

RG
RMf

CPV2 N
0
0 winding resistances are and respectively
LCL Filter
Another loss in the inductoris hysteresis loss which
T = junction temp. , T = case temp., T = heat sink temp. , T = depends on the magnetic flux density (B), magnetic flux
ambient temp., Z( ) = thermal impedance (junction to case),
intensity (H), inductor turn ratio ( ).
Z( ) = thermal impedance (case to heat sink), Z( ) =
thermal impedance (heat sink to ambient) , P = diode power loss,
P = MOSFET power loss, and P = Anti-parallel diode of the MOSFET 1 (12)
power loss, R = Magnetic resistance for winding W , R =Magnetic =
resistance for winding W , M =Magnetic core elements for winding W ,
M = Magnetic core elements for winding W , R = Core loss resistance
1 (13)
for winding W , and R = Core loss resistance for winding W . =
Fig. 3. Thermal equilibrium circuit of mid-point clamping transformerless
inverter.
The range of magnetic flux density, and magnetic flux
Further, in (6) and (7) present the thermal resistance and intensity can be found from B-H curve.
capacitance equation respectively where ( ) and Capacitor losses are happened for capacitor leakage
( ) represent thickness and area in between junction to current ( ), and capacitor ripple voltage (∆ ).
case, and K is the thermal conductivity. On the other hand,
( ) indicates the volume between junctions to the case,
(14)
is the specific heat, and material density is ρ. = ∆ ×

( )
(5)
( ) = ( ) 1− Where is the capacitor leakage current loss and
voltage across the capacitor is ∆ .

618
 Finally, the efficiency can be calculated considering topologies. To analysis the total cost, the total components are
the rated output power is , mentioned including the DC-link capacitors, and the filter
components.

η = × (15) IV. SIMULATION AND EXPERIMENT RESULTS

100 Simulations have been carried out in PLECS software to
analyse the operation and overall performance of the proposed
To have a feeling of the loss distribution in different transformerless inverter system before verifying them in the
components of the mid-point clamping inverter topologies experiments.
simulations have been carried out using PLECS models. TABLE II. PARAMETERS USED FOR SIMULATION AND
Similar parameters and switches (SCT3022ALGC11 for EXPERIMENT.
active switches and C5D50065D for diodes) covered by the Parameter Value
heat sink was considered for the thermal modelling. The Input Voltage (V ) 400 V-DC
thermal impedance with conduction and switching (turn- Resistive Load 105 Ω
ON/OFF) loss characteristics have been imported from the Resistive-inductive Load 98.6 Ω, 70 mH
Output Voltage (V ) 230 V AC
datasheet of the devices. Passive components losses in the
Line Frequency ( ) 50 Hz
filter and capacitor are also modelled appropriately
Output Current ( ) 2.2 A
considering the magnetic property of the inductor core and Modulation Index (M) 0.9
ESR of the filter capacitor. Moreover, Fig. 4 shows losses in Rated Power 500 W
different part of the inverter, where semiconductor losses on Switching Frequency (f ) 25 kHz
the top. In addition, the loss related to the forward voltage DC Bus Capacitor (C = C ) 680 µF
drop in the bridge diodes are considerable. In contrast, the Filter Capacitor (C ) 2.2 µF
Filter Inductor (L , L ) 0.65 mH
losses in the passive components are considerably low.
Switches (SCT3022ALGC11) V = 650 V, I = 93 A
Diodes (C5D50065D) V = 650 V, I =50 A
S1-S4 Controller sb-RIO GPIC

2% S5-S6
22% Table II displays the list of components and parameters
D1-D4 used for both simulations and experiments. Fig. 5 shows the
41%
results of proposed topology in both simulation and the
LCL experimental waveform of inverter voltage, output voltage,
35% filter output current and CM behaviour accurately. All power
switches and diodes are implemented using SiC, and
individual heatsinks are used to cool the devices. ere, the
maximum heat sink temperature at a full load (500 W) reaches
Fig. 4. Losses in full load condition of proposed topology for 500 W.
42 C which is acceptable. The gate drive circuits are set up
on the bottom site of the PCB board, and the control signals
III. COMPARISON WITH EXISTING MID-POINT CLAMPING were generated by the sb-RIO GPIC controller from National
TOPOLOGIES
Instrument (NI). The achieving experimental output is for 0.9
modulation index and tested for 500 W. The output voltage,
Table I summarize the major mid-point clamped based and current are RMS 233 V and RMS 2.2 A respectively for
transformerless topologies regarding CMV, the number of resistive load (see Fig. 5 (d)). The proposed inverter has
components required, reported efficiency, and total prototype reactive capability that shows in Fig. 5 (e). The CMV shows
cost. Thus, the proposed topology achieves constant CMV and in Fig. 5 (f), and Fig 5 (g).
efficiency has measured which is more than other existing
TABLE I. DETAILED COMPARISON OF MID-POINT CLAMPED TRANSFORMERLESS TOPOLOGIES.
Passive Reported
Semiconductor Devices Common
Filter Output THD
No. No. Mode Reported
Topology name IGBTs Diodes Voltage (%) Cost#
of C* of L Voltage No. No. Efficiency, ƞ (%)
Level
No. Voltage No. Voltage CMV (V) of C of L
iH5/oH5 [8] 6 1.5×V 0 --- 2 0 199 to 200 1 2 3 N/A ++ 96.9 @ 1 kW
HERIC Active 1 [12] 7 1.5×V 2 1.5×V 2 0 199 to 200 1 2 3 N/A ++++ N/A
HERIC Active 2 [12] 7 1.5×V 0 --- 2 0 199 to 200 1 2 3 1.7 ++++ 97 @ 2 k W
HERIC Active 3 [12] 6 1.5×V 4 1.5×V 2 0 199 to 200 1 2 3 N/A ++++ N/A
PN-NPC [13] 8 1.5×V 0 --- 2 0 199 to 201.1 1 2 3 N/A ++++ 97.2 @ 1 kW
HB-ZVR [10] 5 3×V 5 1.5×V 2 0 163 to 200 1 2 3 N/A +++ 94.88 @ 2.8 k VA
HB-ZVR-D [11] 5 1.5×V 6 3×V 2 0 199 to 200 1 2 3 1.9 +++ 95.03 @ 1 k VA
H5-D [16] 5 1.5×V 1 1.5×V 2 0 152 to 210 1 2 3 N/A +++ N/A
Proposed topology 6 1.5×V 4 1.5×V 2 0199 to 200 1 2 3 1.8 +++ 97.45 @ 500 W
*
including the input capacitor
#
The more “+” represents the higher cost, + ≡ low, ++ ≡ medium, +++ ≡ high, and ++++ ≡ extremely high.
In the above table, “C” represents capacitor and “L” represents inductor, “THD” total harmonic distortion

619
 VAB (V)
Vin (V) (100 V/div)
VAB (V) (500 V/div)

Vgrid (V)
RMS 233.2 V φpf =30
(250 V/div)
Vgrid (V)
Igrid (A)

(5 A/div)
RMS 2.213 A Igrid (A)
20 ms/div
(a)
(e)
VAN (V)

200 V/div

VAN
VBN (V)

VBN 200 V/div

CMV (V)

CMV 200 V/div

20 ms/div
(b)

(f)

200 V/div
VAN

200 V/div
VBN

(c)

CMV 200 V/div

Vin (V) (100 V/div)

VAB (V) (500 V/div) (g)

Figure 5. Proposed HB-ZVSCR inverter (a) simulated inverter voltage,

RMS 232.9 V output voltage, and current, (b) simulated waveform of , , and CMV,
(250 V/div) (c) top view of proposed prototype (note: all gate drive circuts are placed at
Vgrid (V) bottom layer, and DC-link capacitors) (d) experimentally verifying the input
voltage, inverter voltage, output voltage, and current for resistive (R) load (e)
experimentally verifying the input voltage, inverter voltage, output voltage,
and current for resistive-inductive (R-L) load (f) experimental waveform of
RMS 2.203 A (5 A/div) , , and CMV at DC mode condition, and (g) experimental waveform
Igrid (A) of , , and CMV at AC mode condition.

Fig. 6 shows the efficiency curve of the proposed topology

where maximum efficiency is achieved 97.74 % at full load
(d) condition, and Table III displays the input/output power at
different load conditions.

620

98
97
Efficiency (η)
96
95
94
50 150 250 350 450 550
Output Power (W)
Fig. 6. Measured efficiency vs. load curve for the proposed topology.
V. CONCLUSION
This paper presents a new and high efficient mid-point
clamped transformerless inverter topology (HB-ZVSCR) with
reduced CM and leakage current effect. From the topological
prospective, the intrinsic relationship between different mid-
point clamping topologies are compared and summarized
considering effect of CM voltage, leakage current, required
semiconductor devices, cost, THD, and efficiency. The
simulation and experimental results shows the efficacy of the
proposed circuit with constant CMV and pure sinusoidal
output voltage and current waveforms. The measured peak
efficiency at a full load condition is 97.74% and 97±1% over
a wide range of load.
REFERENCES
[1] K. Solangi, M. Islam, R. Saidur, N. Rahim, and H. Fayaz, "A review
on global solar energy policy," Renew. Sustain. Energy Rev., vol. 15,
no. 4, pp. 2149-2163, May 2011.
[2] A. Jäger-Waldau, “PV Status Report 2018", [Online]. Available:
http://publications.jrc.ec.europa.eu/repository/bitstream/JRC113626/p
v_status_report_2018, PV Status Report 2018, 2018.
[3] Z. Ahmad and S. Singh, "Single phase transformerless inverter
topology with reduced leakage current for grid connected photovoltaic
system," Electric Power Sys. Res., vol. 154, pp. 193-203, Jan. 2018.
[4] N. Mohon, T. M. Undeland and W. P. Robbins, Power
Electronics:Converters, Applications and Design, vol. 2nd ed. New
York: Wiley, 1995.
[5] J. C. Giacomini, L. Michels, H. Pinheiro, and C. Rech, "Active
damping scheme for leakage current reduction in transformerless three-
phase grid-connected pv inverters," IEEE Trans. Power Electron., vol.
33, no. 5, pp. 3988-3999, May 2018.
621
[6] H. Schmidt, C. Siedle, and J. Ketterer, "DC/AC converter to convert
direct electric voltage into alternating voltage or into alternating
current," ed: Google Patents, 2006.
[7] M. Victor, F. Greizer, S. Bremicker, and U. Hübler, "Method of
converting a direct current voltage from a source of direct current
voltage, more specifically from a photovoltaic source of direct current
voltage, into a alternating current voltage," ed: Google Patents, 2008.
[8] B. Yang, W. Li, Y. Gu, W. Cui, and X. He, "Improved transformerless
inverter with common-mode leakage current elimination for a
photovoltaic grid-connected power system," IEEE Trans. Power
Electron., vol. 27, no. 2, pp. 752-762, Feb. 2012.
[9] W. Cui, H. Luo, Y. Gu, W. Li, B. Yang, and X. He, "Hybrid-bridge
transformerless photovoltaic grid-connected inverter," IET Power
Electron., vol. 8, no. 3, pp. 439-446, Mar. 2015.
[10] T. Kerekes, Analysis and modeling of transformerless photovoltaic
inverter systems. Institute of Energy Technology, Aalborg University,
2009.
[11] T. K. S. Freddy, N. A. Rahim, W.-P. Hew, and H. S. Che, "Comparison
and analysis of single-phase transformerless grid-connected PV
inverters," IEEE Trans. Power Electron., vol. 29, no. 10, pp. 5358-
5369, Oct. 2014.
[12] W. Li, Y. Gu, H. Luo, W. Cui, X. He, and C. Xia, "Topology review
and derivation methodology of single-phase transformerless
photovoltaic inverters for leakage current suppression," IEEE Trans.
Ind. Electron., vol. 62, no. 7, pp. 4537-4551, Jul. 2015.
[13] L. Zhang, K. Sun, L. Feng, H. Wu, and Y. Xing, "A family of neutral
point clamped full-bridge topologies for transformerless photovoltaic
grid-tied inverters," IEEE Trans. Power Electron., vol. 28, no. 2, pp.
730-739, Feb. 2013.
[14] M. N. H. Khan, M. Forouzesh, Y. Siwakoti, and L. Li, “Novel high
efficiency h-bridge transformerless inverter for grid-connected single-
phase photovoltaic systems,” in Proc. IEEE Region 10 Symposium
(TENSYMP), Sydney, Jul. 4-6, 2018, pp. 95-99.
[15] M. N. H. Khan, M. Forouzesh, Y. Siwakoti, L. Li, T. Kerekes, and F.
Blaabjerg “A classification of single-phase transformerless inverter
topologies for photovoltaic applications,” in Proc. IEEE Region 10
Symposium (TENSYMP), Sydney, Jul. 4-6, 2018, pp. 174-179.
[16] H. Li, Z. Yangbin, Z. Bo, Q. Trillion, H. Ruixiang, and Y. Zhichang,
"An improved H5 topology with low common-mode current for
transformerless PV grid-connected inverter," IEEE Trans. Power
Electron., vol. 34, no. 2, pp. 1254-1265, Feb. 2019.
[17] Y. P. Siwakoti and F. Blaabjerg, "Common-Ground-Type
Transformerless Inverters for Single-Phase Solar Photovoltaic
Systems," IEEE Trans. Ind. Electron., vol. 65, no. 3, pp. 2100-2111,
Mar. 2018.
[18] M. Melito, A. Gaito, & G. Sorrentino, “Thermal effects and junction
temperature evaluation of Power MOSFETs,” DocID028570 Rev, 1,
141, 2015.
[19] K. Ma, R. S. Muñoz-Aguilar, P. Rodriguez, & F. Blaabjerg, “Thermal
and efficiency analysis of five-level multilevel-clamped multilevel
converter considering grid codes,” IEEE trans. Ind. App., vol. 50, no.
1, PP. 415-423, Jun. 2014.
[20] K. Ma, F. Blaabjerg, & M. Liserre, “Thermal analysis of multilevel
grid-side converters for 10-MW wind turbines under low-voltage ride
through,” IEEE Trans. Ind. App., vol. 49, no. 2, pp. 909-921, Jan.
2013.