A Single-Phase Five-Level Transformerless

Photovoltaic Inverter
Xiaonan Zhu, Xinyue Chen, Renjie Sun, Zhenzhen Li, Xiumei Yue and Hongliang Wang
College of Electrical and Information Engineering
Hunan University
Changsha, China
liangliang-930@163.com

Abstract—The five-level inverters are preferred solutions for
medium-voltage PV applications because of lower total
harmonic distortion (THD), lower switching stress and lower
electromagnetic interference in contrast to two-level inverter
topologies. In order to reduce the leakage current in the five-
level inverter applications, a single-phase five-level
transformerless inverter topology is proposed in this paper. The
proposed inverter is based on an flying capacitor (FC)
configuration and the voltage of FC can be balanced through the
coordination of the two half-bridge within a switching period.
Two bidirectional circuits are added to provide the new
freewheeling paths when outputting zero voltage level. The
mechanism of suppressing the leakage current is analyzed in
detail with operational states and modulation strategy. A 1 kW
prototype is also built and tested in the laboratory, the
experimental results are finally presented to show the excellent
performance in leakage current reduction.
Keywords—Leakage current; single-phase five-level inverter;
transformerless
I. INTRODUCTION
Over the past few years, the new energy power generation
has achieved rapid development such as photovoltaic (PV)
and wind power because they generate electricity without
pollution and emission [1]-[2]. And the grid-connected
inverter plays an important role in the PV system. However,
the PV system suffers from a serious leakage current which
will reduce the system efficiency and threaten personal safety.
An effective solution is to use isolation transformer to
eliminate leakage current, but it will bring new problems such
as large size, high cost and low efficiency [3]-[4]. Thus, the
transformerless PV inverter has attracted more and more
attention both in academic and industrial fields.
The solutions reported to date can be classified into two.
On one hand, the common-mode (CM) filters are good
choices to reduce the leakage current when flowing path of
the leakage current is considered [5]-[6]. The mechanism of
CM filter is to increase the impedance of CM paths through
passive components. The leakage current paths in the
cascaded multilevel inverter are analyzed in [7], and the CM
filters are added to the DC and AC sides of each module.
Although it can eliminate the leakage current, this method
undoubtedly increases the volume, weight, and cost of the
system with the increase of the cascaded modules. An
additional CM capacitor connected between the midpoint of
the dc-link and ground is adopted in [8] to compensate the
effects of parasitic capacitors on the leakage current.
However, the method generates approximate results because
the value of the CM capacitor has a relationship with the
parasitic capacitance, which is difficult to determine in the
actual working condition. In short, changing the hardware
circuit to suppress leakage current will greatly increase the
cost and reduce the efficiency of the inverters.
On the other hand, topologies and modulation strategies
are effective methods to eliminate leakage current from the
source when the source of the leakage current is considered.
To separate the PV array from the grid in the freewheeling
period, a few active switches are introduced in the DC or AC
side as the decoupling network in the full-bridge-based
single-phase transformerless grid-connected inverters, such
as H5 in Fig. 1, HERIC in Fig. 2, and H6 in Fig. 3 [9]. A new
full-bridge topology synthesis method, which is called MN
synthesis method, is proposed in [10]. This method provides
a systematic analysis and can deduce the existing topologies
and several new simplified topologies. An improved H6
transformerless inverter topology is generated in [11].
However, the decoupling network cannot be realized because
of the junction capacitors of the active switches. Thus, the
CM voltage must be clamped to half of the input voltage in
the freewheeling mode to ensure its constant condition. In
accordance with this rule, several enhanced transformerless
inverter topologies with additional freewheeling paths are
presented, such as oH5 in [12], H-bridge zero-voltage state
rectifier (FB-ZVR) topology in [13] and other topologies.
However, these single-phase topologies are limited to
three-level inverters. In this paper, a single-phase five-level
transformerless PV inverter is proposed which can ensure a
constant CM voltage through two freewheeling paths in the
whole line cycle. The rest of the paper is organized as follows.
Section II gives the circuit configuration and operating
principles. Section III discusses the modulation strategy
under active and reactive power conditions. Section IV
presents the experimental results, and Section VI elaborates
the conclusions.

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 P P P
S5 S1 S2
S1 S2 S1 S2 L1
L1 L1
S5 G
39 C G 39 C G 39 C L2
S6 S5 S6
L2 L2
D1 D2
S3 S4 S3 S4
S3 S4
N N N

Fig. 1 H5 topology Fig. 2 HERIC topology Fig. 3 H6 topology

II. OPERATIONAL PRINCIPLES OF PROPOSED SINGLE- P

PHASE FIVE-LEVEL INVERTER
A. Proposed Single-Phase Five-Level Inverter
The schematic of the proposed inverter is shown in Fig. 4.
Cdc is the dc-link capacitor, C1 and C2 are the FCs, and L1 and
L2 are the symmetrical filter inductors. This topology is based
on a full-bridge FC configuration, where S1, S2, S3, S4, and C1
form the first half-bridge; S5, S6, S7, S8, and C2 form the
second half-bridge. Two bidirectional circuits are added to
provide the new freewheeling paths. The first path is formed
by two active switches (S9 and S10) with a reverse series
connection. One terminal of the circuit is connected to the
positive of C1, and the other terminal is connected to the
negative of C2. The second path is formed by two other active
switches (S11 and S12) with the same reverse series connection.
One terminal of the second freewheeling circuit is connected
to the negative of C1, and the other terminal is connected to
the positive of C2.
The dc-link voltage is defined as Vdc. For the proposed
single-phase five-level transformerless inverter, 12 active
switches are needed to generate a five-level voltage (Vdc,
Vdc/2, 0, −Vdc/2, and −Vdc). Notably, the voltages of C1 and C2
are controlled at a quarter of the dc-link voltage (Vdc/4). The
voltage balance control of the FC is achieved by the
coordination of the two bridge arms. The voltages of C1 and
C2 can be maintained constant within a switching period by
selecting the appropriate switching states. In other words, the
value of capacitance can be greatly decreased.
B. Operation of the Single-Phase Five-Level Inverter
According to the analysis in [14], it can be draw the
conclusion that the leakage current can be suppressed if the
CM voltage is constant in the entire period of the utility grid.
However, the CM voltage is related to the switching states.
The following part ensures that the sum of VAN and VBN is
constant.
In state A, switches S1, S2, S7, and S8 are turned on, as
shown in Fig. 5(a). Terminal A is connected to the positive
of the dc-link, and terminal B is connected to the negative of
the dc-link. The output voltage VAB is +Vdc, and the CM
voltage is Vdc/2. In this case, the anti-paralleled diodes of the
S1, S2, S7, and S8 provide a path for a negative load current.
S1 S5
S9 S10
S2 S6
G
L1 L2
39 Cdc C1
A B
C2
S3 S7
S11 S12
S4 S8
N
Fig. 4 Proposed single-phase five-level transformerless PV inverter
In state B, switches S1, S3, S6, and S8 are turned on, as
shown in Fig. 5(b). Terminal A is connected to the negative
of C1, and terminal B is connected to the positive of C2. In
this state, C1 and C2 are charged. The voltages of C1 and C2
should be charged to a quarter of the dc-link voltage (Vdc/4)
to maintain a constant CM voltage. The voltage VAN is 3Vdc/4,
and VBN is Vdc/4. Both the CM and output voltages are Vdc/2.
In state C, switches S2, S7, S11, and S12 are turned on, as
shown in Fig. 5(c). This case is in a freewheeling state.
Terminal A is connected to the positive of C1, and terminal B
is connected to the negative of C2. The inductor current is
flowing through S2, S7, S12, and the anti-paralleled diode of
S11; thus, C1 and C2 are discharged. According to the analysis
in [11], VAN ≈ 3Vdc/4 and VBN ≈ Vdc/4. Both the CM and output
voltages are Vdc/2.
In state D, switches S3, S6, S11, and S12 are turned on, as
shown in Fig. 5(d). Terminal A is connected to the negative
of C1, and terminal B is connected to the positive of C2. In
this situation, the inductors are still in the freewheeling state.
However, C1 and C2 are not involved in the current path
because S3 and S6 are on. As a result, the potentials of point
A and B are equal. Consequently, the output voltage is 0.
According to the analysis in [26], VAN = VBN ≈ Vdc/2. The CM
voltage is Vdc/2.
In state E, switches S2, S7, S9, and S10 are turned on, as
shown in Fig. 5(e). Terminal A is connected to the positive
of C1, and terminal B is connected to the negative of C2.
Similar to state D, VAN = VBN ≈ Vdc/2. The output voltage VAB
is 0, and the CM voltage is Vdc/2.

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 P P
S1 S5 S1 S5
S9 S10 S9 S10

S2 S6 S2 S6
G G
A L1 L2 B L1 L2
A B
39 Cdc C1 C2 39 Cdc C1 C2
S3 S7 S3 S7
S11 S12 S11 S12

S4 S8 S4 S8
N N

(a) State A (b) State B

P P
S1 S5 S1 S5
S9 S10 S9 S10

S2 S6 S2 S6
G G
A L1 L2 B A L1 L2 B
39 Cdc C1 C2 39 Cdc C1 C2
S3 S7 S3 S7
S11 S12 S11 S12

S4 S8 S4 S8
N N

(c) State C (d) State D

P P
S1 S5 S1 S5
S9 S10 S9 S10

S2 S6 S2 S6
G G
A L1 L2 B A L1 L2 B
39 Cdc C1 C2 39 Cdc C1 C2
S3 S7 S3 S7
S11 S12 S11 S12

S4 S8 S4 S8
N N

(e) State E (f) State F

P P
S1 S5 S1 S5
S9 S10 S9 S10

S2 S6 S2 S6
G G
A L1 L2 B L1 L2
39 Cdc C1 C2 A B
39 Cdc C1 C2
S3 S7 S3 S7
S11 S12 S11 S12

S4 S8 S4 S8
N N

(g) State G (h) State H

Fig. 5 Eight switching states of the proposed single-phase five-level transformerless PV inverter. (a) State A: +Vdc. (b) State B: +Vdc/2. (c)
State C: +Vdc/2. (d) State D: +0. (e) State E: -0. (f) State F: -Vdc/2. (g) State G: -Vdc/2. (h) State H: -Vdc.

In state F, switches S3, S6, S9, and S10 are turned on, as of C1, and terminal B is connected to the positive of C2. In
shown in Fig. 5(f). Terminal A is connected to the negative this state, the FCs provide a quarter of the dc-link voltage,

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 TABLE I SWITCHING STATES, BRIDGE VOLTAGES, DIFFERENTIAL MODE AND CM VOLTAGES AND IMPACT ON THE FC VOLTAGE

Output Voltage Flying Capacitor C1, C2

NO VAN VBN VAB VCM iout>0 iout<0
A Vdc 0 Vdc Vdc/2 - -
B 3Vdc/4 Vdc/4 Vdc/2 Vdc/2 Charge Discharge
C 3Vdc/4 Vdc/4 Vdc/2 Vdc/2 Discharge Charge
D Vdc/2 Vdc/2 0 Vdc/2 - -
E Vdc/2 Vdc/2 0 Vdc/2 - -
F Vdc/4 3Vdc/4 -Vdc/2 Vdc/2 Charge Discharge
G Vdc/4 3Vdc/4 -Vdc/2 Vdc/2 Discharge Charge
H 0 Vdc -Vdc Vdc/2 - -

Reactive power zone Active power zone

Z1 Z2 Z3 Z4

ACABACABACAB

+Vdc uc1 uc2 uc3

DCDB DCDB
+Vdc/2 uc4 um iout
t6
0 t0 t1 t2 t3 t4 t5
-Vdc/2
FEGE FEGE
-Vdc
HFGFHFGFHFGF

Fig. 6 Modulation strategy for the proposed single-phase five-level transformerless inverter

and C1 and C2 are discharged. Similar to state C, VAN ≈ Vdc/4
and VBN ≈ 3Vdc/4. The output voltage VAB is −Vdc/2, and the
CM voltage is Vdc/2.
In state G, switches S2, S4, S5, and S7 are turned on, as
shown in Fig. 5(g). Terminal A is connected to the positive
of C1, and terminal B is connected to the negative of C2. The
output voltage is −Vdc/2, and the CM voltage is Vdc/2.
In state H, switches S3, S4, S5, and S6 are turned on, as
shown in Fig. 5(h). Terminal A is connected to the negative
of the dc-link, and terminal B is connected to the positive of
the dc-link. The output voltage VAB is −Vdc, and the CM
voltage is Vdc/2.
III. MODULATION STRATEGY
carriers and one reference are required to generate the gate
signals for 12 switches. The thick red line is the reference um,
the green solid line is the first carrier uc1, the purple dashed
line is the second carrier uc2, the blue solid line is the third
carrier uc3, and the yellow dashed line is the fourth carrier uc4.
The thick blue line is the output current iout, which lags behind
the reference with a phase angle θ.
During the full period of the utility grid, four operating
zones (Z1, Z2, Z3, and Z4) can be identified on the basis of
the polarities of the output current and the grid voltage. In Z1
and Z3, the output current and the grid voltage are in opposite
direction. These zones are reactive power zones. In Z2 and
Z4, the output current and the grid voltage are in the same
direction. These zones are active power zones.

The modulation strategy for the proposed single-phase

five-level transformerless inverter is shown in Fig. 6. Four

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 VAB
Resistive Load

Auxiliary Power Supply DC-link

Capacitor Vout
Oscilloscope

iout

DSP+FPGA Freewheeling
Main DC Source Half-Bridge Filter Inductor
Controller Circuit Fig. 8 Waveforms of bridge voltage, output voltage and current
Fig. 7 Experimental prototype

TABLE I. SYSTEM PARAMETERS

VAB
Description Symbol Value
Input Voltage Vdc 360 V
Grid Voltage Vout 220 V @ 50 Hz
FC Capacitance C1, C2 68 uF VC1
Filter Inductance Lm 1.6 mH
Switching Frequency fs 20 kHz
Parasitic Capacitance Cpv 100 nF VC2
Power P 1 kW

Fig. 9 Waveforms of bridge voltage and FC voltages

The selection of the switching state sequence depends on
the polarity of reference because the proposed topology can
provide reactive power paths in all the eight switching states.
For example, the output voltage in Z1 is switched within VAN
+Vdc/2 and 0. The switching state D is selected to generate 0
output voltage level, and the redundant switching states B and
C are used to generate +Vdc/2 output voltage level and
stabilize the FCs voltage at a quarter of the dc-link voltage. 2VCM
Thus, the inverter is rotating in the sequence of (D, C, D, B)
in Z1. In Z2, states A and D are required to generate +Vdc and
0 voltage levels, respectively. Furthermore, the redundant VBN
states B and C are still selected to regulate the FCs voltage.
Consequently, the switching state sequence of (A, C, A, B)
and (D, C, D, B) are obtained. Similarly, the switching states
H and E in the negative period of the utility grid are used to Fig. 10 Waveforms of bridge voltages and double CM voltage
generate −Vdc and 0 voltage levels, respectively. The
redundant states G and F are selected to regulate the FC
voltage. Therefore, the switching state rotates in the sequence
of (F, E, G, E) in Z3, and both the sequence of (H, F, G, F)
and (F, E, G, E) are selected in Z4. VAB

IV. EXPERIMENTAL VERIFICATION

To verify the effectiveness of proposed topology and its ileakage = 24.4mA RMS
modulation strategy. A 1 kW single-phase five-level
transformerless inverter prototype is implemented, as shown
in Fig. 7. The system includes main circuit, DSP and FPGA
control board, DC source, output filter and measurement
instruments.

Fig. 11 Waveforms of bridge voltage and leakage current

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 The control board employs a combination of the Texas
Instruments TMS320F28335 control card and the Altera
Cyclone II EP2C8Q208 FPGA card to provide powerful real-
time mathematical calculations and control functions. The
experimental parameters are shown in Table I.
The differential mode performance of the proposed
single-phase five-level inverter is shown in Fig. 8 and Fig. 9.
Fig. 8 shows the differential mode voltage VAB, output
voltage Vout, and output current iout from top to bottom. It can
be seen that a five-level differential mode voltage is obtained,
and the excellent output voltage and current waveform
quality are achieved at the same time. The RMS value of the
output voltage and current are 220 V and 4.54 A, respectively.
Fig. 9 shows the FC voltages of C1 and C2. Two electrolytic
capacitors with withstand voltage and capacitance of 200 V
and 68 uF, respectively, are selected in the experiments. The
capacitor voltages are well stabilized at 90 V with little
ripples by the selection of appropriate redundant switching
states. Therefore, the volume and cost will be greatly
decreased compared with those in the conventional topology.
The CM characteristics of the proposed inverter are
shown in Fig. 10 and Fig. 11. Fig. 10 shows the bridge
voltages of VAN and VBN and the double CM voltage 2VCM.
The two bridge voltages have five voltage steps, namely, 0,
90, 180, 270, and 360 V. Moreover, the voltage 2VCM is
constant within the entire period of the utility grid. This
condition leads to the possibility of suppressing the leakage
current. Evidently, the experimental results agree closely
with the results from theoretical analysis. The leakage current
can be effectively decreased below 300 mA, which complies
with the VDE0126-1-1 standard, as shown in Fig. 11.
V. CONCLUSION
In this paper, a novel single-phase five-level
transformerless inverter and its modulation strategy for the
PV systems are proposed. The CM voltage can be maintained
at a constant value and the leakage current can be eliminated
completely by introducing two freewheeling paths, which are
formed by two anti-series active switches. The two FCs can
be regulated at a quarter of the dc-link voltage automatically
through the selection of the redundant switching states. The
theoretical analysis and experimental verification for the
conventional topology and the proposed topology are
presented. In conclusion, the proposed topology and
modulation strategy can ensure a constant CM voltage
without any high-frequency components throughout the
power frequency cycle. Consequently, the leakage current
can be significantly suppressed below 300 mA, which meets
the specification in the standard VDE-0126-1-1.
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