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Cmos Aicd
Cmos Aicd
QUESTION BANK
M. Tech – I Year – I Sem. (VLSI & Embedded Systems)
2022-2023
(VLSI&ES)
Roll No
***
B Draw the small-signal model for the MOS transistor. Briefly explain each [7M]
component in that?
3 A Explain the given simplest forms of the current mirror, the MOS version of [7M]
the current mirror?
B Explain the Bipolar simple current mirror with degeneration helper with [7M]
necessary equations?
4 What is the Current Mirror? Explain the general properties of current mirrors [14M]
with a block Diagram?
B Explain the slew rate and noise for a p-channel differential amplifier with [7M]
necessary equations?
Page 1 of 21
B Explain the design of Two-stage op-amps? [7M]
8 A Compare the dynamic latch with the NMOS and PMOS latches. What are [7M]
the advantages and disadvantages of the two latches?
B Explain the different types of Open-loop comparator? [7M]
Page 2 of 21
Code No: R20D6803 R20
MALLA REDDY COLLEGE OF ENGINEERING & TECHNOLOGY
(Autonomous Institution – UGC, Govt. of India)
(VLSI&ES)
Roll No
***
2 A Draw the small-signal model for the MOS transistor. Briefly explain [7M]
each component in that?
B Choose values of VGS = 1,2,3,4 and 5V, assume that the channel [7M]
modulation parameter is zero. Sketch to scale the output characteristics
of an enhancement n-channel device if VT = 0.7V and ID = 500μA when
VGS = 5 Vin saturation.
3 A Explain the simplest forms of the current mirror and the Bipolar version of [7M]
the current mirror?
B Explain in detail the MOS cascode current mirror with necessary equations? [7M]
4 A Explain the difference between cascade current mirror and Wilson current [7M]
mirror?
Page 3 of 21
5 A Briefly explain the differential amplifiers. With necessary equation give the [7M]
large-signal analysis of CMOS differential amplifiers?
B Derive the expression for power-supply rejection ratio of Two-stage op- [7M]
amps?
B Explain the concept of push-pull inverter with a neat diagram. Derive the [7M]
small signal voltage gain and find the zero in plane?
B With neat sketch and necessary equations explain the Design aspect of a [7M]
two stage open loop comparator for slewing response?
*****
Page 4 of 21
Code No: R18D6808
(VLSI&ES)
Roll No
***
4 Explain the difference between cascade current mirror and Wilson current mirror. [14M]
Page 5 of 21
7 Explain about the design of CMOS op-amps. [14M]
**********
Page 6 of 21
Code No: R20D6803 R20
MALLA REDDY COLLEGE OF ENGINEERING & TECHNOLOGY
(Autonomous Institution – UGC, Govt. of India)
(VLSI&ES)
Roll No
***
cm-2.
2 Interpret the simple MOS large signal model using mathematical [14M]
models.
4 What is current mirror circuit and discusses its operation using [14M]
various blocks
Page 7 of 21
5 What is Active load inverter? Develop small signal model for the Active [14M]
load inverter.
7 Draw the block diagram of a general two stage Op-Amp and explain the [14M]
8 Identify model of an Ideal comparator, comparator with finite gain and [14M]
**********
Page 8 of 21
Code No: R20D6803
(VLSI&ES)
Roll No
Time: 3 hours
Max. Marks: 70
***
SECTION-I
Page 9 of 21
4 What happens when Gate and Drain of MOS [14M]
transistor are tied together? Show its I-V
characteristics and its small signal model.
SECTION-III
Page 10 of 21
Code No: R18D6808 R18
MALLA REDDY COLLEGE OF ENGINEERING & TECHNOLOGY
(Autonomous Institution – UGC, Govt. of India)
(VLSI&ES)
Roll No
Note: This question paper Consists of 5 Sections. Answer FIVE Questions, Choosing
ONE Question from each SECTION and each Question carries 14 marks.
***
SECTION-I
OR
SECTION-II
Page 11 of 21
b).Derive the small signal voltage gain and find the zero in plane. [7M]
OR
6 a).Name the different output amplifiers and explain any one in [7M]
detailed.
[7M]
b).Illustrate the Architectures of High Gain Amplifiers.
SECTION-IV
OR
SECTION-V
OR
**********
Page 12 of 21
Code No: R18D6808 R18
MALLA REDDY COLLEGE OF ENGINEERING & TECHNOLOGY
(Autonomous Institution – UGC, Govt. of India)
(VLSI&ES)
Roll No
****
1 a).Draw the small-signal model for the MOS transistor. Briefly [7M]
explain each component in that. [7M]
2 a).Choose values of VGS = 1,2,3,4 and 5V, assume that the channel [7M]
modulation parameter is zero. Sketch to scale the output
characteristics of an enhancement n-channel device if VT = 0.7V and
ID = 500µA when VGS = 5Vin saturation.
[7M]
b).Explain the Large-signal model for the MOS Transistor.
Page 13 of 21
5 a).Briefly explain the differential amplifiers. With necessary [7M]
equation give the large signal analysis of CMOS differential
amplifiers.
[7M]
b).Design a CMOS current mirror load differential amplifier.
6 Explain about a) Current Amplifier b) Cascode Amplifier. [14M]
**********
Page 14 of 21
Code No: R18D6808 R18
MALLA REDDY COLLEGE OF ENGINEERING & TECHNOLOGY
(VLSI&ES)
Roll No
Note: This question paper Consists of 5 Sections. Answer FIVE Questions, Choosing
ONE Question from each SECTION and each Question carries 14 marks.
***
SECTION-I
1 Analyze the Simple MOS Small-Signal Model with the associated [14M]
parameters in detail.
OR
SECTION-II
3 a) Draw the model for a non ideal switch and explain its [6M]
parameters in detail
b) Draw and explain about a simple current mirror with Beta [8M]
helper.
OR
Page 15 of 21
SECTION-III
OR
SECTION-IV
OR
b) Design the two stage CMOS op-amp to meet the important [7M]
specifications
SECTION-V
OR
**********
Page 16 of 21
Code No: : R17D6805
R17
Roll No
Note: This question paper Consists of 5 Sections. Answer FIVE Questions, Choosing ONE Question from
each SECTION and each Question carries 14 marks.
*****
Blooms
Marks CO
Level
SECTION-I
Q.1. a) Draw the physical structure of n channel and p channel MOS transistor [7M] CO1 2
using well technology and highlight the importance points?
b) Explain the importance of BSIM3 model addresses threshold voltage [7M] CO1 2
reduction
OR
Q.2. a) Explain the small signal model for the MOS transistor [7M] CO2 2
b) Draw the circuit diagram of standard cascode current sink and how its
reduces the errors in V or I [7M]
OR
Q.4. a) What do you mean by band gap reference and list the principle involved? [7M] CO2 4
b) Explain 2 Input NOR gate with depletion NMOS loads. Calculate
output high
voltage and output low voltage? [7M]
SECTION-III
Q.5. a) Draw the circuit diagram of output amplifier using push pull inverting CO3 2
amplifier and comment on [7M]
Page 17 of 21
it?
SECTION-V
Q.9. a) Explain regenerative comparators? [7M] [7M] CO5 4
Page 18 of 21
Code No: R18D6808
(VLSI&ES)
Roll No
***
1 Write a brief note on various passive components that are available in CMOS
2 Analyze the Simple MOS Large-Signal Model with the associated parameters in
detail.
3 Illustrate the MOS switch operation and various models with application
4 Explain the concept of current sink and Design a current sink of 250µA and a VMIN of 0.5V
5 Illustrate the various types of CMOS inverting Amplifiers and small signal model
Page 19 of 21
8 Illustrate the discrete-time comparators with relevant schematics
**********
R15
Code No: R15D6805
Roll No
Note: This question paper Consists of 5 Sections. Answer FIVE Questions, Choosing ONE Question from
each SECTION and each Question carries 15 marks.
*****
Bloo
Marks CO ms
Level
SECTION-I
Q.1. a) Explain about MOS large- signal analysis of CMOS Device Modeling [10M] CO1 2
OR
Q.2. a) Discuss about the passive components of the MOS transistor. [7M] CO2 2
b) Write about computer simulation models for MOS transistor [8M] CO2 2
SECTION-II
Q.3. a) Explain the working of current mirror with beta helper [10M] CO2 2
Page 20 of 21
SECTION-III
Q.5. a) Explain about working of differential amplifier [10M] CO3 3
b) Explain the operation of CMOS inverter [5M] CO3 3
OR
Q.6. Discuss the principle of High Gain Amplifiers Architectures CO3 1
[15M]
SECTION-IV
Q.7. Discuss the concept of op amp compensation and give the necessary CO4 2
expressions.
[15M]
OR
Q.8. a) Explain the Design of Two-Stage Op Amps [10M] CO4 6
b) What is a comparator and list the important characteristics of a comparator [8M] CO4 2
OR
Q.10. What are the various forms of improving the slew-rate of a 2-stage op [15M] CO5 2
amp and obtain the expression for slew rate of CMOS op amp
Page 21 of 21