AN 210

Effective ESD Protection Design at System Level

Using VF-TLP Characterization Methodology

Application Note
Revision: 1.3 - December 6, 2012

RF a n d P r o te c ti o n D e vi c e s
Edition December 6, 2012

Published by
Infineon Technologies AG
81726 Munich, Germany

c 2012 Infineon Technologies AG

All Rights Reserved.

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 Application Note No. 210

Contents

Contents

1 Introduction 5
1.1 Definition of Electrostatic Discharge and Electrical Overstress . . . . . . . . . . . . . . . . . . . . . . . 5
1.2 The IEC61000-4-2 ESD Standard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.3 The IEC 61000-4-5 Surge Immunity Standard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.3.1 Surge Test Measurement Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.4 Comparison of Component Level and System Level ESD . . . . . . . . . . . . . . . . . . . . . . . . . 8

2 Characterization of ESD Protection Devices and Circuits with a Transmission Line Pulse System 9
2.1 Pulsed Device Characterisation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.2 The Transmission Line Pulse Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.2.1 How the Pulse is Generated . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.3 The TLP Measurement System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.3.1 Discrete Voltage and Current Sensors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.3.2 Remote Voltage and Current Sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.3.3 Error Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.4 Measurement Techniques . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.4.1 Four Point Kelvin TLP Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.4.2 Four Point Kelvin Very Fast TLP Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.4.3 Reverse Recovery Time of Diodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.4.4 Safe Operating Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.4.5 System Level ESD Test (HMM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.5 Typical TLP Parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.6 Typical TLP Measurement Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.6.1 DC Sweep and Spot Leakage Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.6.2 TLP Characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.6.3 Definition of the Dynamic Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.6.4 Transient Overshoot and Clamping Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.7 How TLP fits to IEC 61000-4-2 ? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.7.1 TLP Parameter Set Recomendation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.8 ESD Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.8.1 Design Consideration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.8.2 PCB Layout Consideration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.9 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3 Comparison of ESD Protection Technologies: Silicon Transient Voltage Suppressor (TVS) Diodes ver-
sus Multilayer Varistors (MLV) 21
3.1 DC Sweep . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.2 Dynamic Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.3 Transient Overshoot and Clamping Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.4 Spot Leakage Drift . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.5 Breakdown Voltage Drift . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.6 Degradation due to Multi-Pulse Stress . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.6.1 Spot Leakage Drift . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.6.2 Breakdown Voltage Drift . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

References 27

Author 28

Copyright Notice 28

Application Note Page 3 of 29 Rev. 1.3 - December 6, 2012

 Application Note No. 210

Contents

Revision History

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Revision History: December 6, 2012, Rev. 1.3

Previous Version: 1.1
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Application Note Page 4 of 29 Rev. 1.3 - December 6, 2012


1 Introduction
In today’s highly competitive markets, efficient ESD pro-
tection has became an integral part of IC/ASIC design
for system reliability. Field failures due to ESD will be per-
ceived as poor quality by disappointed customers and will
increase the number of warranty returns. Overlooking the
ESD problem can seriously impact company’s image and
its profitability.
Reliable circuit protection following IEC61000-4-2 in-
dustry’s standard is usually accomplished by the imple-
mentation of ESD protection devices at critical pins. How-
ever, some traditional approaches still rely on trial-and er-
ror practices to design for ESD protection. This can re-
quire several re-design loops until the ESD problem is fi-
nally solved, for instance during compliance testing, prac-
tice that increases costs and delay the time-to market of
new electronic products.
The introduction of Very-Fast Transmission Line Pulse
(vf-TLP) as support method is of utmost importance in
the selection of appropriate ESD protection devices and
makes the trial and error practices not longer justified.
The Very Fast Transmission Line Pulse employs high cur-
rent testing to determine the behaviour of devices and cir-
cuits in the current and time domain of ESD events. This
strategy implemented at an early circuit design stage de-
livers a faster, precise and least costly approach to im-
prove ESD robustness at system level while responding
to today’s market dynamics.
The purpose of this application note is to provide the
guidelines for optimized selection of protection devices
with the support of vf-TLP. Chapter 1 provides an in-
troduction to electrostatic discharge standards typically
used in the industry. Chapter 2 describes the charac-
teristics of TLP equipment as well as measurement set
up and testing capabilities. Section 2.6.2 explains the
typical I/V characteristic curves of unidirectional and bidi-
rectional protection devices. Chapter 3 displays a bench-
mark comparison of ESD protection devices based on dif-
ferent technologies, namely Multilayer Varistor (ceramic
technology) and TVS diode (silicon based technology).
1.1 Definition of Electrostatic Discharge
and Electrical Overstress
Electrostatic Discharge (ESD) is known as transfer of
electrostatic charge between bodies or surfaces at
different electrostatic potential. ESD can happen due
to sudden discharge of a charged body, tribo-electric
and induced charging. ESD is a high current event
in the typical range of 0.1 to 30 Apeak in a very short
period of time from 1 ns to 200 ns.
Electrical Overstress (EOS) is considered as the expo-
sure of a device or an integrated circuit (IC) to a cur-
rent or voltage beyond its absolute maximum ratings.
Application Note Page 5 of 29
Application Note No. 210
1.2 The IEC61000-4-2 ESD Standard
EOS can occur due to voltage overshoots resulting in
high destructive currents.
ESD is considered as a subset of EOS. But EOS may
caused also by a wrong application of the IC beyond its
absolute maximum voltage or current ratings. In this case
the damage of the IC may not happened due to an ESD
event.
The International Electrotechnical Commission (IEC)
has developed transient immunity standards which have
become minimum requirements for original equipment
manufacturers. The basic standards for immunity testing
are known as the IEC 61000-4-X standards. Three of the
IEC standards deal with transient immunity:
• IEC 61000-4-2 : Electrostatic Discharge (ESD)
• IEC 61000-4-4 : Electrical Fast Transient/Burst (EFT)
• IEC 61000-4-5 : Surge Immunity
IEC 61000-4-2 is related to ESD immunity [1]. IEC 61000-
4-4 and IEC 61000-4-5 are related to transient immunity
[2, 3].
1.2 The IEC61000-4-2 ESD Standard
The IEC 61000-4-2 standard [1] addresses ESD tran-
sients in electronic systems. It defines immunity require-
ments for ESD which can be coupled into the equipment,
systems or system boards directly or through radiation
(air discharge). Direct coupling includes any user acces-
sible entry points such as connectors, I/O ports, switches,
computer keyboards, panel displays, touch screens and
equipment housings.
Radiated coupling results from the spark discharge be-
tween two bodies which are external to the system. Be-
cause the human body is one of the most common ESD
generators, the IEC standard defines a test set up which
simulates an ESD event from a human body.
The Human Body Model is considered as a valid repre-
sentation of worst case ESD stress. Discharge into equip-
ment may be through direct contact (contact discharge
method) or just prior to contact (air discharge method).
Contact discharge is the usually preferred test method,
but air discharge is used where contact discharge cannot
be applied.
The ESD threat is divided into four threat levels de-
pending on material and ambient humidity, as shown in
Tab. 1. Threat level 1 is considered the least severe while
threat level 4 is the most severe. Levels 1 & 2 are re-
served for equipment which is installed in a controlled
environment and in the presence of antistatic materials.
Level 3 is used for equipment which is sparsely but not
continuously handled. Level 4 is required for any equip-
ment which is continuously handled.
Rev. 1.3 - December 6, 2012
 Application Note No. 210

1.3 The IEC 61000-4-5 Surge Immunity Standard

Relative Antistatic Synthetic Maximum Test Voltage Test Voltage

Class Humidity Material Material Charge (Contact- (Air-
(as low as) Voltage Discharge) Discharge)
1 35 % x 2 kV 2 kV 2 kV
2 10 % x 4 kV 4 kV 4 kV
3 50 % x 8 kV 6 kV 8 kV
4 10 % x 15 kV 8 kV 15 kV

Table 1: IEC 61000-4-2 severity levels and test voltages.

Indicated First Peak Current Risetime Current Current

Level Voltage of Discharge with Discharge at 30 ns at 60 ns
(±10 %) Switch (±30 %) (±30 %)
1 2 kV 7.5 A 0.7 ns to 1 ns 4A 2A
2 4 kV 15 A 0.7 ns to 1 ns 8A 4A
3 6 kV 22.5 A 0.7 ns to 1 ns 12 A 6A
4 8 kV 30 A 0.7 ns to 1 ns 16 A 8A

Table 2: IEC 61000-4-2 ESD current waveform parameters.

9 1.3 The IEC 61000-4-5 Surge Immunity

8 First Peak Current Standard
90 %
7 IEC 61000-4-5 addresses the most severe transient con-
ditions on both power and data lines. These are tran-
ESD−Current (A)

6
0.7 ns - 1 ns Risetime

sient caused by lightning strikes and switching. Switching

5 transients may be the result of power system switching,
I at 30 ns
4 load changes in power distribution systems, or short cir-
cuit fault conditions. Lightning transients may result from
3 I at 60 ns a direct strike or induced voltages and currents due to an
2 indirect strike.
The IEC 61000-4-5 standard defines a transient en-
1 10 % try point and a set of installation conditions. The tran-
0 sient is defined in terms of a generator producing a given
−50 0 50 100 150 200 waveform and having a specified open circuit voltage
Time (ns)
and source impedance. Two surge waveforms are spec-
ified: the 1.2 x 50 µs open-circuit voltage waveform and
Figure 1: 2 kV ESD current pulse waveform according
the 8 x 20 µs short-circuit current waveform (Fig. 2 and
IEC 61000-4-2 (R=330Ω, C=150 pF) [1]
Fig. 3).
Transient stress levels for each entry point into the sys-
tem are defined by installation class. The six classes are
Fig. 1 shows a 2 kV ESD current pulse waveform ac- defined as:
cording IEC 61000-4-2 with a R=330Ω and C=150 pF dis-
Class 0: well protected environment
charge circuitry. The ESD current waveform at a certain
indicated discharge voltage is specified with 4 parameters Class 1: partially protected environment
(Tab. 2):
Class 2: well separated cables
1. rise time 0.7 - 1 ns Class 3: cables run in parallel
2. first peak current of discharge (±10 %) Class 4: multi - wire cables for both electronic and elec-
trical circuits
3. Current at 30 ns (±30 %)
Class 5: connection to telecommunications cables and
4. Current at 60 ns (±30 %) overhead power lines (low density populated areas)

Application Note Page 6 of 29 Rev. 1.3 - December 6, 2012

 Application Note No. 210

1.3 The IEC 61000-4-5 Surge Immunity Standard

Power Supply Unsym. Lines Sym. Lines Data Bus

(Long Distance Bus) (Short Distance)
Class Coupling Mode Coupling Mode Coupling Mode Coupling Mode
Line-Line Line-GND Line-Line Line-GND Line-GND Line-GND
Zs= 2 Ω Zs=12 Ω Zs=42 Ω Zs=42 Ω Zs=42 Ω 42 Ω
voltage No Requirement
0 current
voltage (n/a) 0.5 kV (n/a) 0.5 kV 1 kV (n/a)
1 current 42 A 12 A 24 A
voltage 0.5 kV 1 kV 0.5 kV 1 kV 1 kV 0.5 kV
2 current 250 A 83 A 12 A 24 A 24 A 12 A
voltage 1 kV 2 kV 1 kV 2 kV 2 kV (n/a)
3 current 500 A 167 A 24 A 48 A 48 A
voltage 2 kV 4 kV 2 kV 4 kV (n/a) (n/a)
4 current 1000 A 333 A 48 A 95 A
voltage Note1 Note1 2 kV 4 kV 4 kV
5 current 48 A 95 A 95 A
Wave- voltage 1.2 x 50 µs 1.2 x 50 µs 1.2 x 50 µs 1.2 x 50 µs 1.2 x 50 µs 1.2 x 50 µs
forms current 8 x 20 µs 8 x 20 µs 8 x 20 µs 8 x 20 µs 8 x 20 µs 8 x 20 µs

Table 3: IEC 61000-4-5 Severity Levels.

V
environment is the most severe and requires the highest
1.0 transient stress level testing.
0.9
T1 = 1.67 x T = 1.2 µs +/-30 % Tab. 3 summarizes threat levels as a function of instal-
T2 = 50 µs +/-20 %
lation class. Values of voltage stress using the 1.2 x 50 µs
waveform are given. Corresponding current values are
0.5
T2 calculated by dividing the open-circuit voltages by the
0.3 source impedances. The short-circuit current values are
0.1
more useful in choosing a suppression element. The
short circuit current stress levels are defined with the
T t
T1
30% max. 8 x 20 µs waveform for power supply applications with a
2 Ω source impedance. For data lines requiring a 42 Ω
source impedance, the short-circuit current waveform is
Figure 2: IEC 61000-4-5 1.2 µs / 50 µs voltage impulse.
defined as 8 x 20 µs. For telecommunications applica-
tions, the open-circuit voltage is defined as 10 x 700 µs
I
and the short-circuit current is a 5 x 300 µs waveform.
The source impedance is given as 40 Ω. The type of sup-
1.0 I PP
pression element needed for IEC 61000-4-5 class surges
0.9
T1 = 1.25 x T = 8 µs +/-20 % depends upon the threat level and installation class. For
T2 = 20 µs +/-20 %
power supply applications high power devices are re-
0.5
quired. A discrete device or an assembly may be re-
T2 quired depending on the application. TVS diodes are
the best choice for data line applications and secondary
0.1 board level protection because of their superior clamping
T
voltage characteristics and fast response time.
30% max. t
T1

1.3.1 Surge Test Measurement Setup

Figure 3: IEC 61000-4-5 8 µs / 20 µs current impulse.
A class 0 environment is considered the lowest threat
level a has no transient stress requirements. The class 5
Fig. 4 shows the measurement setup for the 8/20 µs
surge test of TVS diodes. The amplitude of the pulse
generator is adjusted for typical peak current (Fig. 3) of
1 Depends on class of local power supply system.

Application Note Page 7 of 29 Rev. 1.3 - December 6, 2012

 Application Note No. 210

1.4 Comparison of Component Level and System Level ESD

Parameter Component Level ESD Test System Level ESD Test

Stressed pin group All pin combinations Few special pins
Supply Unpowered Powered & unpowered
Test methodology Standardized Application specific
Test set-up Commercial tester & sockets Application specific
Typical qualification goal 1 . . . 2 kV JEDEC HBM 8 kV Contact (IEC 61000-4-2, [1])
(ANSI/ESDA/JEDEC JS-001- 15 kV Air (IEC 61000-4-2, [1])
2012, [4])
Corresponding peak current 0.65 . . . 1.3 A >20 A
Junction/ambient temperature 27 ◦ C Application specific
Failure signature Destructive Functional or destructive

Table 4: Comparison of Component and System Level ESD Test.

Standard R/C Network Rise-Time First Peak Broad Peak Decay Time
Current Current
ANSI/ESDA/JEDEC R = 1.5 kΩ, C = 100 pF 2-10 ns 0.67 A/kV - 130-170 ns
JS-001-2012
IEC 61000-4-2 R = 330 Ω, C = 150 pF 0.7-1 ns 3.75 A/kV 2 A/kV -

Table 5: Comparison ESD current waveform parameters.

Figure 4: 8/20 µs surge test measurement setup.

IPP =1 A and IPP =3 A, respectively for TVS products. The
peak clamping voltage at e.g. IPP1 =1 A and IPP2 =3 A is
measured and presented in the data sheet. The dynamic
resistance can be calculated as follows:
VCL2 − VCL1
Rdyn,surge =
IPP2 − IPP1
1.4 Comparison of Component Level and
System Level ESD
Component level ESD stress occurs in wafer- or
component-fabrication areas caused by static charge
generation and during product lifetime due to human han-
dling electrostatic discharge [5], [6]. Normally, IC’s are
designed to meet 1 kV to 2 kV HBM ESD robustness ac-
cording the joint JANSI/ESDA/JEDEC standard JS-001-
2012 [4]. Recent investigations have shown that a level of
>500 V HBM (ANSI/ESDA/JEDEC JS-001-2012) ESD ro-
bustness is sufficient for state-of-the-art fabrication tech-
nologies [7]. The recommendations therein are intended
(1)
for component level safe ESD requirements and will have
little or no effect on system level ESD results. Systems
and system boards should continue to be designed to
meet appropriate ESD threats regardless of the compo-
nents in the systems that are meeting the new recom-
mendations [7], and that all proper system reliability must
be assessed through the IEC test method [1]. Tab. 4
shows a comparison of component and system level ESD
test procedure for product qualification. Tab. 5 shows the

Application Note Page 8 of 29 Rev. 1.3 - December 6, 2012

 Application Note No. 210

2.1 Pulsed Device Characterisation

typical ANSI/ESDA/JEDEC JS-001-2012 and IEC 61000- This section gives an introduction about the basic prin-
4-2 ESD current waveform parameters. Fig. 5 compares ciple of a high voltage TLP generator and how it can be
the ESD current waveform for 1 kV component level ESD used effectively for device characterisation and electro-
(ANSI/ESDA/JEDEC JS-001-2012) and 1 kV system level static discharge (ESD) design.
ESD (IEC 61000-4-2).

5 2.1 Pulsed Device Characterisation

The characterisation of devices and circuits in pulsed
4 mode has two major advantages: a) diminish self heat-
ing effects and b) limit the dissipated energy in the device
ESD−Current (A)

3 in order to avoid destruction. Usually the pulsed mode is

helpful to investigate specific device or circuit parameters
IEC 61000−4−2
in the time domain, such as:
2
• High current I-V characteristics
1
• Turn-on/off transient characteristics
ANSI/ESDA
/JEDEC JS
-001-2012
0 • Breakdown effects
−50 0 50 100 150 200
Time (ns)
• Charge recovery effects e.g. reverse and forward re-
covery of diodes
Figure 5: Comparison of a 1 kV component-level ESD
pulse according HBM ANSI/ESDA/JEDEC JS- • Safe Operating Area (SOA) or Wunsch-Bell charac-
001-2012 (R=1.5 kΩ, C=100 pF) [4] and a 1 kV teristics
system-level ESD pulse according IEC 61000-
4-2 (R=330Ω, C=150 pF) [1]. • Ruggedness of transistors (RF-LDMOS, DMOS,
CMOS, BJT, . . . )

• MOS gate oxide reliability

• Packaging and handling ESD, published in the joint

2 Characterization of ESD standard ANSI/ESDA/JEDEC JS-001-2010
Protection Devices and Circuits • Human-Metal-Model (HMM) and system level ESD
with a Transmission Line Pulse (IEC-61000-4-2)

System If the pulse width and pulse rise time becomes small,
impedance matched transmission lines are used to con-
A Transmission-Line Pulse (TLP) system is a valuable nect the DUT to the measurement system (Fig. 6).
measurement equipment for circuit and device character-
Z0
ization in pulsed operation mode in the high power time
Z0 IDUT (t)
domain [8].
The classical TLP measurement system consists of a
V0 (t) DUT VDUT (t)
50 Ω high voltage pulse generator, a high speed digital
oscilloscope, a Source Meter Unit (SMU) and a control
computer. The typical range of the pulse waveform pa-
rameters are: output voltage amplitude in the range of up Figure 6: Simplified pulsed mode measurement setup
to ±4 kV, output currents up to ±80 A, pulse width in the
range of 1 ns up to 1.6 µs, pulse rise time in the range In this setup for a passive DUT the maximum open load
from 100 ps to 50 ns. The transient voltage and currents output voltage is
in the device under test (DUT) are recorded using a high VDUT,max = V0 (2)
speed digital oscilloscope with e.g. 12 GHz bandwidth
and 40 GS/s sampling rate. and the maximum short circuit DUT current is
Such a measurement system can be used very effec- V0
tive to investigate transient characteristics of semiconduc- IDUT,max = . (3)
Z0
tor devices and circuits in the high voltage and high cur-
rent time domain. For electrostatic discharge sensitivity The pulsed voltage source V0 and the characteristic
testing two standards are available [9] and [10]. impedance of the transmission lines Z0 limit the maximum

Application Note Page 9 of 29 Rev. 1.3 - December 6, 2012

 Application Note No. 210

2.2 The Transmission Line Pulse Generator

V(z)
DUT voltage and short circuit DUT current. To achieve
V0
higher level of VDUT and IDUT , V0 can be increased and Z0
can be decreased. V0/2

Usually Z0 = 50 Ω is widely used as a compromise be- z

z=-L z=-L/2 z=0 z=+L/2 z=+L
V(z)
tween low loss and power handling capability for coax-
V0
ial cables and measurement systems [11]. Example: -V0 / 2
in order to achieve 40 A short circuit DUT current in a V0/2
+V0 / 2
Z0 = 50 Ω system, a pulsed voltage source of 2 kV is re- z=-L z=-L/2 z=0 z=+L/2 z=+L
z

quired. V(z)

So far no commercial pulse generators based on solid- V0

-V0 / 2
state devices or vacuum tubes are available to handle V0/2
+V0 / 2
such high voltage with excellent pulse waveform qual- z=-L z=0 z=+L
z
z=-L/2 z=+L/2
ity with a dynamic range from below 1 V up to several V(z)

kilo volts amplitude. The concept of using high voltage V0

charged transmission lines to generate rectangular pulse V0/2
-V0 / 2 +V0 / 2
waveforms with high quality is well known for a very long z=-L
z
z=-L/2 z=0 z=+L/2 z=+L
time, which has been described in [12] or even much ear- V(z)

lier. This leads us to the classical transmission line pulse V0

generator. V0/2
-V0 / 2
z
z=-L z=-L/2 z=0 z=+L/2 z=+L
S1
2.2 The Transmission Line Pulse Generator R TL1 TL2
Z0 Z0 IDUT (t)
Fig. 7 shows the basic concept of the classical TLP V0 +− VDUT (t)
DUT
generator. It consists of a high voltage source V0 , an L

impedance matched transmission line TL1 , the switch S1 S1 TL2

TL1
and the transmission line TL2 . The necessary core ele- Z0 IDUT (t)
Z0
ments are just two: TL1 and S1 . In the bottom of Fig. 7
V0 DUT VDUT (t)
two possible circuit realisations of the TLP generator are
+
−

shown. Both are based on the basic principle of an

open ended transmission line TL1 with a characteristic
impedance Z0 and a mechanical length L. TL1 is often Figure 7: The classical transmission line pulse (TLP)
called charge line. For the initial condition at times t < 0, generator
TL1 has to be charged with high voltage V0 . This can be
done at the open end of TL1 using a resistor If R is very high or ∞, then ρ = +1. This means when a
voltage wave hits the open end, the current has nowhere
R  Z0 (4)
to go, and so a voltage wave of the same polarity prop-
or directly at the switch side using a single pole, double agates back up the line, adding to the original voltage.
throw switch (SP2T). v is the propagation velocity in the With this background we can consider the states along
transmission line the charge line TL1 in Fig. 7:
c
v≈√ (5) t < 0 This is the initial condition: the switch S1 is open
r
and TL1 is charged with the high voltage V0 constant
with c the speed of light and r the relative dielectric over the length L. TL2 has no voltage potential.
constant of the transmission line inner insulator. v ≈
0.2 m/ns is a good rule of thumb for polytetrafluoroethy- t = 0 S1 switched on: after short time t > 0 the volt-
lene (PTFE or Teflon) dielectrics. age at the switch drops down to Z0 · V0 /(Z0 + Z0 ) =
V0 /2 because source impedance of TL1 and load
impedance of TL2 is Z0 . At this time two voltage
2.2.1 How the Pulse is Generated waves start immediately to propagate in opposite di-
In the general case, the amplitude of the wave reflected rections. One voltage wave with amplitude +V0 /2
at the open end of the charge line is determined by the starts to propagate in positive z direction. Another
reflection coefficient ρ. The value of ρ depends on the voltage wave with amplitude −V0 /2 starts to prop-
characteristic impedance Z0 and R, the termination resis- agate in negative z direction, adding to the original
tance at the end of the line: voltage.
L
R − Z0 t= 2v At this time both voltage waves have propagated
ρ= (6) already a distance of z = ±L/2.
R + Z0

Application Note Page 10 of 29 Rev. 1.3 - December 6, 2012

 Application Note No. 210

2.3 The TLP Measurement System

VDUT (t) IDUT (t) TLP Current

V I

I ( V, I )

Averaging

Averaging
Window

Window
500 mV

t t TLP
t1 t2 t1 t2 Voltage
V
500 ps
Figure 9: Extraction of the TLP characteristic

each captured voltage and current waveforms the arith-

metic mean values V and I are calculated in the aver-
Figure 8: TLP waveform measurement result at 40 GS/s aging window between t and t . For all pulse ampli-
1 2
tudes these mean values are collected in an IV-diagram
t = vL The voltage wave along negative z direction with with the so called TLP voltage V on the x-axis and the
amplitude −V0 /2 hits the open end of TL1 . A voltage TLP-current I on the y-axis. This diagram represents the
wave with same polarity propagates back up the line quasi-stationary IV-characteristic of the DUT. It is always
and adds to the original voltage −V0 /2 + V0 /2 = 0 necessary to specify four important measurement condi-
which leads to cancellation. tions in addition to the diagram:

t= 3L
The cancellation voltage wave propagates back 1. characteristic impedance of the TLP system
2v
up the line and has reached z = −L/2. At the same 2. width of the pulse
time the other voltage wave with +V0 /2 amplitude
has reached the location z = 3L/2 (not shown in 3. rise time of the pulse
Fig. 7).
4. location of the averaging window: t1 and t2
This consideration leads to the conclusion that a rectan- Usually after the caption of each pulse waveform a dc
gular pulse waveform is propagating along the transmis- leakage measurement is done and a second plot is added
sion lines. On the transmission line a mechanical dis- to the TLP-characteristic: bottom x and left y axis remain
tance of 2L is travelled by the waveform and the pulse as the traditional TLP voltage and current, and on top
width in the time domain is x and left y the evolution of leakage current (top x) ver-
2L √ 2L sus TLP current (left y) is added [14], [15], as shown in
tp = ≈ r · (7) Fig. 10.
v c
which is the basic design equation of the classical TLP Leakage Current [A]
-7 -6
generator. Fig. 8 shows a typical pulse waveform rising 10 10 10-5 10-4 10-3
edge, measured with a 12 GHz oscilloscope (Tektronix 80
DUT IV Characteristic
TDS6124C) at 40 GS/s sampling rate.
70 Leakage Current at +5V

60
2.3 The TLP Measurement System
TLP Current [A]

50
For the investigation and development of ESD protection
devices T. Maloney and N. Khurana did introduce TLP in 40
1985 for the first time [13]. Barth Electronics introduced 30
the first commercial TLP system in the mid-1990s includ-
ing the concept and calibration of the measurement sys- 20
tem [14], [15]. The DUT (Fig. 6) is excited with rectangu- 10
lar pulse waveforms with variable amplitude. The voltage
waveforms VDUT (t) and current waveforms IDUT (t) at the 0
0 5 10 15 20
DUT are recorded using a digital high speed oscilloscope
with single shot waveform capture capability. In general, TLP Voltage [V]
the entire waveforms are valuable for the evaluation of
the transient DUT characteristics in the time domain. Es- Figure 10: Measured TLP characteristic of a 5 V TVS
pecially for ESD design the pulsed IV-characteristic, also diode
called TLP-characteristic, is important (Fig. 9). Out of

Application Note Page 11 of 29 Rev. 1.3 - December 6, 2012

 Application Note No. 210

2.3 The TLP Measurement System

2.3.1 Discrete Voltage and Current Sensors Sensor Sensitivity Bandwidth Rise Time A x µs
[V/A] [GHz] [ns] Rating
Fig. 11 shows a pulsed mode measurement setup with CT-1 5 1 < 0.35 1
discrete sensors for current and voltage. The sensors CT-2 1 0.2 < 0.5 50
should be located as close as possible to the DUT.
Table 6: Comparison of current sensor parameters [17]
TLP Generator Current Sensor
LD
50 Ω
50 Ω IDUT (t)
TLP Generator Pickoff Delay
High Impedance Probe

V0 (t) DUT VDUT (t) Tee Line

50 Ω
50 Ω 50 Ω IDUT (t)
Oscilloscope
V0 (t) DUT VDUT (t)

IDUT (t) 50 Ω

Oscilloscope
VDUT (t) 50 Ω
VI(t), VR(t) 50 Ω

Figure 11: Pulsed mode measurement setup with dis-

crete sensors Figure 14: Simplified VF-TLP measurement setup

2.3.2 Remote Voltage and Current Sensing

Voltage Sensor Current Sensor
Output The voltage VDUT (t) and current IDUT (t) can be calcu-
Output
lated out from incident and reflected waves, far away from
the DUT. This becomes indispensable if the pulse width
50 Ω
50 Ω

becomes very small and the overlapping region of inci-

dent and reflected pulses is inadequate to take an I-V
Pulse Pulse
measurement directly at the DUT using discrete sensors.
4.95 kΩ Input Output Usually this is the case at pulse width tp ≤ 10 ns. The
Pulse Input 50 Ω 50 Ω adequate measurement setup, shown in Fig. 14, is called
(a) High impedance probe (b) Current sensor
very-fast TLP (VF-TLP) [18], [19] based on time-domain
reflectometry (TDR).
The voltage probe (pickoff tee) is placed so far away
Figure 12: Discrete voltage and current sensors from the DUT that incident and reflected waveforms ap-
pear separated. This can be achieved by inserting a delay
Fig. 12 show practical realisations for discrete voltage line between the probes and DUT of mechanical length
and current probes. Voltage probes can be realised eas-
ier for higher bandwidth than current probes. The high tp · v c
LD > ≈ tp · √ (8)
impedance V-probe shown in Fig. 12(a) has an input 2 2 r
impedance of 5 kΩ and a sensitivity (or voltage division
ratio) of 50/(4950 + 50) = 0.01 V/V. The voltage sensor With separated pulses the response at the DUT can be
output must be terminated with 50 Ω. GGB [16] offers calculated by numerically overlapping the incident and re-
probe tips with such integrated resistors (Model 10) for flected pulses according to following equations:
wafer-level testing up to 11 GHz.
VDUT (t) = VI (t) + VR (t) (9)
Discrete I-probes for pulse waveforms are often based
on transformers, as shown in Fig. 12(b). The Tektronix IDUT (t) = II (t) − IR (t) (10)
CT-1 and CT-2 current sensors [17] have become an in-
VI (t), VR (t) are incident and reflected voltage wave-
dustry standard for TLP applications up to 100 A, de-
forms. II (t), IR (t) are incident and reflected current wave-
pending on the pulse width tp .
forms. Since incident and reflected pulses appear sepa-
Tab. 6 summarises the typical specifications of the Tek-
rate, there is a correlation between the current and volt-
tronix CT-1 and CT-2 current sensors. The maximum cur-
age on the transmission line defined by its characteristic
rent depends on the pulse width and is limited by the L/R
impedance Z0 according to:
time constant and the amp x second rating. If the product
(current x pulse width) exceeds the maximum rating, the VI (t)
core saturates and the output drops to zero. II (t) = (11)
Z0

Application Note Page 12 of 29 Rev. 1.3 - December 6, 2012

 Application Note No. 210

2.4 Measurement Techniques

GPIB

SMU
DUT Leakage Test

LEAKAGE
TEST
Leakage
PC + System Control Software

DUT
CURRENT SENSOR
TLP Switch Control 50 Ω Picoprobe
GPIB DUT Pulse Force Model 10
GENERATOR L < 2 inch
Pulse 50 Ω 50 Ω
50 Ω Pulse Output 50 Ω

DUT

SWITCH PAD PAD

DIGITAL
OSCILLOSCOPE
DUT Pulse Sense 5 kΩ
50 Ω
VDUT (t) Pulse Sense
5 kΩ Picoprobe
Model 10
GPIB
Current
IDUT (t) 50 Ω
A1

Figure 13: Four point Kelvin TLP method including dc leakage measurement

VR (t) On the pulse force line a standard 50 Ω ground-signal

IR (t)
By combining Eqn. 11, Eqn. 12 and Eqn. 10, the follow-
ing equation is obtained
IDUT (t) =
with Z0 = 50 Ω. Thus, VI (t) and VR (t) gives enough in-
formation to calculate VDUT (t) and IDUT (t). In order to
refine the results and to improve the accuracy, the fre-
quency response of all components have to be included
in the calculations by calibration and deembedding.
2.3.3 Error Sources
In order to achieve high resolution and high accuracy in
the time domain, proper compensation of the non-ideal
characteristics of the components in the measurement
system is required. Major contribution come from in-
terconnection cables (lossy transmission lines), voltage
probes, current sensors and parasitic contact resistance
in case of wafer measurements with probes.
= (12)
Z0 (GS) type RF probe tip is used. The discrete current sen-
sor should be located as close as possible to the DUT,
typically not more than 5 cm far away. Thus, the setup is
suitable for pulse with of tp > 5 ns.
VI (t) − VR (t) The sense probe tip has an integrated resistive divider,
(13) which enables the voltage to be measured with minimal
Z0
parasitic loading (1-5 kΩ). The bandwidth of the high
impedance probe is 7 to 11 GHz depending on the probe
tip model.
To ensure differential voltage measurement directly at
the device sheath waves should be suppressed on the
transmission lines with ferrite cores and the ground of the
probe tip holder should be isolated from the chuck and
DUT fixture surrounding grounds.
The switch configuration with the source meter unit
(SMU) is used to perform a dc (spot) leakage measure-
ment in the pA to mA range after each high current pulse,
in order to check if the DUT is already damaged or starts
degrading. This method can be used for wafer-level as
well as for component- or circuit level measurements.
2.4.2 Four Point Kelvin Very Fast TLP Method

For very fast TLP measurements (VF-TLP) with pulse

2.4 Measurement Techniques widths < 10 ns, incident and reflected signals are
2.4.1 Four Point Kelvin TLP Method recorded separately with a wide-band pickoff tee in the
pulse-force line (see Fig. 15). The transient device re-
To eliminate the error from non-zero contact resistance sponse is calculated by combining the incident and re-
at high currents, a four point Kelvin method is preferred flected pulse signals numerically according Eqn. 9 (DUT
to measure the differential voltage directly at the device voltage) and Eqn. 13 (DUT current).
(Fig. 13) [20]. But the DUT voltage is preferably measured directly

Application Note Page 13 of 29 Rev. 1.3 - December 6, 2012

 Application Note No. 210

2.4 Measurement Techniques

GPIB

SMU
DUT Leakage Test

LEAKAGE
TEST

Leakage
DUT
PC + System Control Software

TLP Switch Control 50 Ω Picoprobe

Delay
GPIB Model 10
GENERATOR
Pulse 50 Ω
50 Ω Pulse Output 50 Ω
PICK
OFF
DUT
TEE
SWITCH PAD PAD
DIGITAL
OSCILLOSCOPE DUT
Pulse Sense 5 kΩ
Pulse Sense
50 Ω
VDUT (t)
5 kΩ Picoprobe
A3 Model 10
GPIB Incident/Reflected
Wave Signal
VI(t), VR(t)
A1

Figure 15: Four point Kelvin VF-TLP method including dc leakage measurement

Source Meter
with a second Picoprobe Model-10 with integrated volt-
IF Forward Current
age dividing resistor. This assures high bandwidth and
Bias Tee
minimizes the voltage error due to parasitic contact resis- 50 kHz - 12 GHz
tance. It also eliminates the digital noise that is typical TLP Generator Current Sensor

for voltage measurements of low-ohmic devices with this 50 Ω

method. In addition precise de-embedding of cable loss 50 Ω

(amplitude and phase) enables accurate pulse measure-

High Impedance Probe
V0 (t)
IDUT (t)
ments in the time-domain.
DUT VDUT (t)
Oscilloscope

2.4.3 Reverse Recovery Time of Diodes IDUT (t) 50 Ω

Reverse recovery measurements are becoming more and VDUT (t) 50 Ω

more important to determine the ESD robustness of cir-
cuits during operation. The recovery times can be mea-
sured extremely fast and efficient with TLP in the range Figure 16: 50 Ω reverse recovery measurement setup
from about 200 ps up to 1 µs. The DUT is mounted in
a 50 Ω test fixture. When a diode is conducting current
in the forward direction, a significant amount of charge is Reverse Recovery Definition - I: 25 % of nominal peak
injected into the resistivity region and the PN junction of reverse current achieved This definition is used by
the diode. When reverse voltage is applied the extraction commercial reverse recovery equipment manufacturers
of this charge leads to the reverse recovery phenomenon [24].
[21], [22].
A diode reveals an excessive transient forward voltage
Reverse Recovery Definition - II: 10 % of nominal peak
when it is switched rapidly into the forward conduction
reverse current achieved This definition is recom-
region. The amplitude and time duration of this voltage
mended by the standard MIL-STD-750D, method 4031.3
peak is representing the forward recovery characteristic
for diodes with trr < 6 ns [22].
[23].
In the literature the reverse recovery time trr of diodes
is defined multiple with different procedures of extraction Reverse Recovery Definition - III: 90 % of reverse volt-
(Fig. 17) and with different impedance conditions 50 Ω age achieved Michael Reisch propose in his book [25],
and 100 Ω [24], [25], [22]. Section 14.2.3, page 629, to use 90 % settling time of the

Application Note Page 14 of 29 Rev. 1.3 - December 6, 2012

 Application Note No. 210

2.4 Measurement Techniques

VTLP
• Measurement of the nominal peak reverse current.
• Extract 25 % (or 10 % according MIL-STD) of the
V0 nominal peak reverse current.
• The time where the current IDUT decreases down to
25 % (or 10 % according MIL-STD) of the nominal
t peak reverse current, is the reverse recovery time.
VDUT Reverse Recovery Time Definition by M. ReischFig. 16 shows the block diagram of a 50 Ω reverse re-
t rr
covery time measurement setup. The DUT is operated
with 50 Ω source resistance. The DUT voltage and cur-
90 % of reverse voltage VR
VR
rents are measured with discrete sensors. Therefore the
setup is useful for trr > several ns.
Fig. 18 shows a typical result of a silicon diode, mea-
t sured with setup Fig. 16 and extraction of 25 % of the
- VF nominal peak reverse current. For each forward current
density just only one TLP sweep is required. Postpro-
IDUT Reverse Recovery Time Definition by AVTECH Corp. cessing of the captured TLP waveforms has been done
trr using Matlab [26].
Fig. 19 shows a 100 Ω reverse recovery measurement
IR setup. In contrast to Fig. 16 no current sensor is nec-
essary, because IDUT (t) = VA (t)/50 Ω. The pickoff-tee is
25 % of nom. peak rev. current
used to measure the voltage at the cathode VC (t). The in-
10 % of nom. peak rev. current
t
terconnection between pickoff tee and the DUT results in
a separation of incident and reflected waves. Therefore,
- IF trr the setup is useful for trr > several ns.

10 % of nom. peak rev. current

30
defined by MIL-STD-750D, METHOD 4031.3
Reverse Recovery Time trr [ns]

JF = 1.4E-6 A/µm2
25 JF = 4.1E-6 A/µm2
JF = 6.8E-6 A/µm2
Figure 17: Typical reverse recovery waveforms with setup
20
Fig. 16
15
reverse voltage. This definition gives a more worst case
10
value of the reverse recovery time.
5
Reverse Recovery Definition - IV: reverse recovered
charge A more general approach to evaluate the re- 0
verse recovery phenomenon is to plot the reverse recov- 0 5 10 15 20 25 30 35 40 45 50 55 60
ered charge versus rate of rise of reverse current for dif- Reverse Voltage VR [V]
ferent values of forward bias current [21].
If we follow [24] or the MIL-STD we can extract the re-
verse recovery time as follows: Figure 18: Reverse recovery measurement result of a sil-
icon diode
• Set the pulse parameters to minimum available rise
time (e.g. 100 ps) and a pulse width which is ap- For extremely small recovery times in the sub-ns range
proximately two to three times the expected reverse the setup in Fig. 20 is based on TDR remote sensing. The
recovery time. DUT voltage and current can be calculated as follows:

• Operate diode in forward mode with a defined for- VDUT (t) = VI (t) + VR (t) − VA (t) (14)
ward bias current IF . VA (t) VI (t) − VR (t)
IDUT (t) = (15) =
Z0 Z0
• Apply a reverse mode TLP pulse with a defined re-
verse voltage VR = VTLP −|VF |. The pulse width of the where Z0 = 50 Ω, VI (t) is the incident voltage wave, VR (t)
TLP has to be increased until the voltage VR remains is the reflected voltage wave and VA (t) is the voltage at
steady state. the anode of the DUT.

Application Note Page 15 of 29 Rev. 1.3 - December 6, 2012

 Application Note No. 210

2.6 Typical TLP Measurement Results

Source Meter
TLP System Impedance: 50 Ω source impedance TLP
IF Forward Current
systems are widely used. However, sometimes for
Bias Tee specific snapback measurements and evaluation of
50 kHz - 12 GHz
the holding voltage a higher source impedance e.g.
TLP Generator
500 Ω is recommended.
50 Ω Pickoff Tee
50 Ω Pulse Width: The standard TLP pulse width is 100 ns
IDUT (t)
VC(t) because the total pulse energy is similar to ESD
V0 (t)
DUT VDUT (t) pulses according to the ANSI/ESDA/JEDEC JS-001-
VA(t) 2012 HBM. The variable pulse width of commercial
Oscilloscope TLP measurement systems is in the range from 1 ns
up to 1000 ns.
VC(t) 50 Ω
Pulse Rise-Time: Standard TLP systems have a pulse
rise-time of 10 ns. VF-TLP systems offer rise times
VA(t) 50 Ω down to 100 ps to investigate turn-on characteristic
of the DUT.

Figure 19: 100 Ω reverse recovery measurement setup Averaging Window: The averaging window t1 and t2
has to be specified according Sect. 2.3, Fig. 9.
Source Meter
IF Forward Current
Spot Leakage and Curve Tracing: The test method for
LD
Bias Tee
evaluation of the device failure must be defined. DC-
50 kHz - 12 GHz presweep, spot leakage measurement and dc curve
TLP Generator Delay
Pickoff
Tee
Line tracing are widely used.
50 Ω
50 Ω 50 Ω
IDUT (t)
V0 (t)
DUT
2.6 Typical TLP Measurement Results
VDUT (t)
VA(t)
2.6.1 DC Sweep and Spot Leakage Measurement
Oscilloscope

VI(t), VR(t) 50 Ω
The DUT ist characterized with a DC measurement pro-
cedure before, during and after TLP measurement. DC I-
V characteristics or single spot measurements with forced
VA(t) 50 Ω
currents or voltages can be used to monitor device dc
drifts or damage during the TLP measurements.
Figure 20: 100 Ω recovery measurement setup with TDR
2.6.2 TLP Characteristic

2.4.4 Safe Operating Area
The Safe Operating Area (SOA) for ESD and pulsed elec-
trical overstress (EOS) of active and passive devices can
be easily measured using a TLP test system with variable
pulse widths in the full range from about 1 ns to 1.5 µs.
2.4.5 System Level ESD Test (HMM)
State of the art TLP systems also offers a Human Metal
Model (HMM) pulse waveform as an alternative test
method to IEC 61000-4-2 with significant improved repro-
ducibility of the test results.
2.5 Typical TLP Parameter
The following parameters are necessary to specify a TLP
measurement:
Fig. 21 illustrates typical TLP characteristics which are
discussed in general ESD protection concepts [6].
In Fig. 21(a) the protection device has a simple turn-
on at a threshold point (Vt1 , It1 ) with t1 being the trigger-
ing time to form a low-impedance channel to discharge
ESD transients. In the reverse direction the dynamic re-
sistance Rdyn,rev can be observed. In the forward direc-
tion the device shows the forward dynamic resistance
Rdyn,fwd . Fig. 21(b) shows a snapback device where it
turned on at a triggering point (Vt1 , It1 , t1), then driven
into a snapback region with low holding (Vh , Ih ) to create
a low impedance discharge path. Again in the reverse di-
rection the dynamic resistance Rdyn,rev can be observed.
In the forward direction the device shows the forward on-
resistance Rdyn,fwd . The second breakdown or irreversible
destruction of the device can be observed at the point
(Vt2 , It2 ). Fig. 21(c) shows a uni-directional character-
istic. For negative voltages the device shows a forward
PN-junction. In Fig. 21(d) a bi-directional characteristic is

Application Note Page 16 of 29 Rev. 1.3 - December 6, 2012

 Application Note No. 210

2.6 Typical TLP Measurement Results

2nd Breakdown
(V ,,II )
t2 t2 2nd Breakdown
(V , I )
t2 t2
ESD Protection Region
TLP Current (A)

ESD Protection Region

(Low-R Discharge)

rev
TLP Current (A)
(Low-R Discharge)

dyn ,
ev
Triggering

R
Holding

n,r
Turn-On (V , I ) (V , I , t )
h h t1 t1 1

dy
R
(V , I , t )
t1 t1 1
d

d
fw

fw
0
n,

n,
dy

dy
R

R
0 0
TLP Voltage (V) TLP Voltage (V)
(a) Simple turn-on [6]. (b) Snapback [6].
TLP Current (A)

TLP Current (A)

0 0

0 0
TLP Voltage (V) TLP Voltage (V)
(c) Uni-directional I-V characteristic. (d) Bi-directional I-V characteristic.

Figure 21: Typical TLP I-V characteristics used for ESD protection design.

presented. The device has a symmetrical transfer char- for non-snapback and snapback devices. However, it is
acteristic. recommended to calculate the least squares fit out of the
TLP characteristic between two TLP currents ITLP2 and
ITLP1 as shown in Fig. 22. In general the dynamic resis-
2.6.3 Definition of the Dynamic Resistance tance is dependent on:
The dynamic resistance of a device can be evaluated as • the location on the I-V characteristic of the device
the derivation dV /dI at a certain point on its high current
I-V characteristic: • the pulse width

dV • the location and length of the averaging window to

Rdyn (V , I) = (16) extract the mean of the voltage and current (Fig. 9)
dI
If the I-V characteristic is constant in a wide range, as For longer pulse width, like the 8 µs / 20 µs surge im-
shown in e.g. Fig. 21(a) in reverse mode between turn-on munity test, increased self heating of the device is ex-
and 2nd break down, then the dynamic resistance can be pected. The dynamic resistance can extracted as pre-
extracted with two points: sented in Sect. 1.3.1.
Vt2 − Vt1
Rdyn = (17) 2.6.4 Transient Overshoot and Clamping Voltage
It2 − It1
Vt2 − Vh
= (18) The mystery about ESD protection is gone. Advanced
It2 − Ih TLP tester show that the first nanosecond can determine
(19) whether a chip will live or die. In essence sometimes chip

Application Note Page 17 of 29 Rev. 1.3 - December 6, 2012

 Application Note No. 210

2.8 ESD Design

60 30
TLP Characteristic IEC 61000-4-2 (R=330Ω, C=150 pF) Pulse Energy
RDYN
1 kV 0.5 µJ
50 25
2 kV 2.03 µJ
ITLP2 = 40 A

Equivalent VIEC [kV]

40 20
4 kV 8.1 µJ
RDYN = 0.136 Ω 8 kV 32.5 µJ
ITLP [A]

30 15 15 kV 114.5 µJ

20 10 Table 7: Pulse energy of ESD pulses according IEC

61000-4-2 (R=330Ω, C=150 pF).
10 ITLP1 = 10 A 5

0 0
sensitive to the first peak of the IEC pulse. In most cases
0 5 10 15 20
VTLP [V] the pulse energy is the performance limiting parameter.
Therefore, a correlation with 2 A/kV can be used (Fig. 22,
Figure 22: Extraction of the dynamic resistance using a right y-axis).
least squares fit between two TLP currents
ITLP2 and ITLP1 . The value of ITLP2 and ITLP1 2.7.1 TLP Parameter Set Recomendation
can be defined in order to cover the interesting
ESD current region. Using a TLP equipment to measure the dynamic resis-
tance, turn-on characteristic and maximum fail current
of TVS diode the following TLP parameters are recom-
manufacturers look at failure at voltages too late in the
mended (Tab. 8):
ESD event. Investigation of transient turn on and over-
shoot in the picosecond range makes the difference be-
Parameter Value Comment
tween protecting or not. In Sect. 3 two state of the art
TLP source 50 Ω
ESD protection device technologies will be compared.
impedance
Maximum TLP up to 2 A/kV IEC broad
2.7 How TLP fits to IEC 61000-4-2 ? current ±80 A peak value (30 ns)
Pulse width 65 ns worst case 100 ns
In general there is no correlation between standards and Pulse rise time 0.6 ns correlates well with
TLP measurement results allowed, because generation commercial IEC ESD
of the test signal is different and also the DUT sensitivity tester.
against waveform parameters (e.g. rise time) is most Averaging 30-60 ns
likely different. TLP generates a rectangular voltage window
waveform with 50 Ω source resistance. IEC61000-4-2
generates a different waveform shown in Fig. 1 at Table 8: Typical TLP parameter for IEC 61000-4-2
different time variant source impedance. However, the (R=330Ω, C=150 pF) performance evaluation.
big advantage of TLP is the well defined and exact con-
trollability of the waveform parameters such as source
impedance, pulse width, rise time, amplitude.
2.8 ESD Design
In general the energy per pulse can be calculated as
Z T For packaging and handling ESD [4], TLP techniques up
Epulse = p(t) dt (20) to 20 A have been used for the development of protec-
0 tion devices for more than 25 years. But recent develop-
where p(t) is the instantaneous power of the DUT. If the ments are focused more on the development of system
ESD protection device has turned on and has a very level ESD [1] protection solutions in two directions:
low resistance in order to shunt the ESD current the
1. TLP characterisation of the ESD protection
pulse energy of pulse waveforms according IEC 61000-
device
4-2 (R=330Ω, C=150 pF) can be calculated as shown in
Tab. 7. 2. TLP characterisation of the device/circuit/system to
Based on the broad peak currents shown in Tab. 5 a be protected
TLP impulse with 2 A amplitude, 63.4 ns pulse width,
< 600 ps rise time gives a pulse energy of 0.508 µJ which With this information the ESD protection solutions can be
correlates very well to a 1 kV pulse according IEC 61000- designed and optimized in a systematic way, in contrast
4-2 (R=330Ω, C=150 pF). In general TVS diodes are not to the widely used try-and-error approach in the past.

Application Note Page 18 of 29 Rev. 1.3 - December 6, 2012

 Application Note No. 210

2.8 ESD Design

15 kV air discharge, according IEC-61000-4-2 [1], is a

15 kV IC
common standard for original equipment manufacturers
(OEM) of e.g. mobile phones. IESD IPIN
15 kV contact discharge is used by the component sup- PIN
ITVS

VPIN
pliers to guarantee the performance (clamping character- VTVS
istic) and quality (minimum 1000 pulses to withstand at
maximum ratings) of the ESD protection devices (Fig. 23).

80
15 kV Contact Discharge ITLP
70
15 kV Air Discharge 8 mm
60 IESD

50 ΔV
Current [A]

ΔV
40 ΔI RDYN
ΔI
30
IPIN
20

10

0 Vt1 VPIN VTLP

-25 0 25 50 75 100 125 150 175 200
Time [ns] Figure 24: ESD protection: TVS is sufficient

Figure 23: Comparison of 15 kV contact and air dis-

charge current. 15 kV IC
IESD R IPIN
The first peak current at 15 kV contact discharge ex-
ceeds 60 A. Thus, a TLP system with 80 A capabilities PIN
ITVS
is suitable to develop 15 kV system level ESD protection VTVS VPIN
solutions.

2.8.1 Design Consideration

Fig. 24 shows an example where the clamping voltage ITLP R . IPIN
of the TVS diodes is lower than the fail voltage VPIN and
IESD
fail current IPIN of the IC. In this case the protection is
sufficient and the improvement of the protection results in ΔV
IESD − IPIN . ΔV
In Fig. 25 the TVS is not able to protect the IC because ΔI RDYN
ΔI
the clamping voltage of the TVS is higher than the fail
voltage of the IC. In this case an additional resistor can IPIN
close the gap and can be calculated as follows:

(IESD − IPIN ) · RDYN + Vt1 − VPIN

R≥ (21) VPIN Vt1 VTLP
IPIN

Figure 25: ESD protection: TVS is not sufficient. Addi-

2.8.2 PCB Layout Consideration
tional resistor is required to close the gap.
ESD design results in a combination of four basic fields of
knowledge: high frequency (RF), high voltage, high cur-
rent and device physics. In the PCB design the following • Low wiring parasitics
items have to be addressed:
• Clear definition of the ESD current path
• Solid thermal connection of the protection device (es-
• Solid GND and terminal connections pecially necessary for surge applications)

Application Note Page 19 of 29 Rev. 1.3 - December 6, 2012

 Application Note No. 210

2.9 Conclusion

2.9 Conclusion
The characterisation in pulsed mode is heavily used in
the development of semiconductor devices and circuits
including ESD. Pulse generators are required which can
deliver pulse waveforms up to several kilo volts in 50 Ω.
The TLP generator is still state of the art in handling such
high dynamic range.
The basic principle of the classical TLP generator has
been reviewed. TLP measurement systems based on dis-
crete voltage and current sensors, and the TDR based re-
mote sensing (VF-TLP) method for measurements in the
sub-ns range have been presented.
The four point Kelvin technique for TLP and VF-TLP
is preferred for improved measurement accuracy at high
currents.
Reverse recovery measurements are important to de-
termine the ESD robustness of circuits during operation.
Different measurement configurations, especially for the
sub-ns region, are explained.
Finally, ESD design can be done in a very systematic
way first time right such as RF design using advanced
TLP techniques.

Application Note Page 20 of 29 Rev. 1.3 - December 6, 2012

 Application Note No. 210

3 Comparison of ESD Protection Technologies: Silicon Transient Voltage

Suppressor (TVS) Diodes versus Multilayer Varistors (MLV)
Fig. 26 shows a photograph of 3 devices for performance comparison. All devices have been measured with 400 µm
pitch wafer-level RF-probes contacted directly at its pads. This is a significant advantage because no 50 Ω test fixture
and no deembedding is necessary. The transient waveforms are measured directly on the pads of the devices which
reflects exactly the application on the PCB.

(a) Infineon TVS ESD08V0R1B-02LS (b) MLV-1 (0201). (c) MLV-2 (0201).
and ESD206-B1-02LS (0201).

Figure 26: Comparison of ESD protection devices: Transient Voltage Suppressor diodes (TVS, silicon technology)
and Multi-Layer Varistors (MLV, ceramic technology).

3.1 DC Sweep
In comparison to best-in-class 0201 MLV in ceramic technology the 0201 TVS diode in silicon technology has much
lower DC leakage current. This results in significant improvement in battery life time of mobile handsets using silicon
TVS diodes. In Fig. 27 the leakage current of the TVS diode ESD8V0R1B-02LS is even lower than the measurement
limit of the equipment. Breakdown is well defined and sharp.

-3
10
TVS (IFX ESD206-B1-02LS)
10-4 TVS ESD8V0R1B-02LS
MLV-1
MLV-2
10-5
|DC Leakage Current| (A)

10-6

10-7

10-8

10-9

10-10

10-11
-15 -10 -5 0 5 10
Voltage (V)

Figure 27: DC characteristic comparison.

Application Note Page 21 of 29 Rev. 1.3 - December 6, 2012

 Application Note No. 210

3.2 Dynamic Resistance

3.2 Dynamic Resistance

Fig. 28 presents the TLP characteristics of ceramic MLVs compared to silicon TVS. At 25 A the clamping voltage of
the MLVs are 2.5 times and 5.5 times higher compared to the silicon TVS. The TVS has 0.77 Ω compared to 2 Ω and
5 Ω of the MLVs, respectively. Fig. 29 gives a detailed view at lower current levels. The TVS ESD206 shows lowest
dynamic resistance and steepest turn-on characteristic.

30
0.17Ω

25

0.77Ω 2Ω 5Ω
20
TLP Current (A)

15

10

5 ESD206-B1-02LS
ESD8V0R1B-02LS
MLV-1
MLV-2
0
0 50 100 150 200
TLP Voltage (V)

Figure 28: I/V characteristic comparison. TLP-parameter: 50 Ω, 100 ns pulse width, 290 ps rise time.

5
0.17Ω

0.77Ω 2Ω 5Ω
TLP Current (A)

1
ESD206-B1-02LS
ESD8V0R1B-02LS
MLV-1
MLV-2
0
0 10 20 30 40 50 60 70 80 90 100 110 120
TLP Voltage (V)

Figure 29: I/V characteristic comparison: detail view.

Application Note Page 22 of 29 Rev. 1.3 - December 6, 2012

 Application Note No. 210

3.3 Transient Overshoot and Clamping Voltage

3.3 Transient Overshoot and Clamping Voltage

In Fig. 30 the transient overshoot of MLV-2 is 250 V at 16 A TLP current, which relates to approximately 8 kV according
IEC-61000-4-2. The overshoot of 250 V is too high for sensitive sub-100 nm CMOS technologies. The TVS diode
results in much lower clamping voltage at same ESD current level. In general the TVS diode shows the lowest
clamping voltage. Fig. 31 shows the turn-on in detail at 25 ps sampling interval. The TVS has also very low overshoot.

250
ESD206-B1-02LS
TVS ESD08V0R1B-02LS
MLV-1
200 MLV-2
Clamping Voltage (V)

150

100

50

0
-10 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140
Time (ns)

Figure 30: Clamping voltage comparison at 16 A TLP current. TLP-parameter: 50 Ω, 100 ns pulse width, 290 ps rise
time. Scope: Tektronix TDS6124C, 12.5 GHz bandwidth, 40 GS/s sampling rate.

250
ESD206-B1-02LS
TVS ESD08V0R1B-02LS
MLV-1
200 MLV-2
Clamping Voltage (V)

150

100

50

0
-0.5 0 0.5 1 1.5
Time (ns)

Figure 31: Turn-on comparison at 16 A TLP current. TLP-parameter: 50 Ω, 100 ns pulse width, 290 ps rise time.
Scope: Tektronix TDS6124C, 12.5 GHz bandwidth, 40 GS/s sampling rate.

Application Note Page 23 of 29 Rev. 1.3 - December 6, 2012

 Application Note No. 210

3.4 Spot Leakage Drift

3.4 Spot Leakage Drift

Fig. 32 shows the DC spot leakage drift at 5 V reverse working voltage during a single TLP sweep up to >25 A.
MLV-1 and MLV-2 show significant drift in leakage current. The TVS diode has extremely low leakage and zero drift.

35
TVS ESD8V0R1B-02LS
MLV-1
MLV-2
30

25
TLP Current (A)

20

15

10

0
10-11 10-10 10-9 10-8 10-7
Spot Leakage Current (A)

Figure 32: DC spot leakage drift at 5 V reverse working voltage. TLP-parameter: 50 Ω, 100 ns pulse width, 290 ps
rise time.

3.5 Breakdown Voltage Drift

Fig. 33 shows the breakdown voltage drift at 1 mA force current during a single TLP sweep up to >25 A. MLV-2 has
slight drift. ML-1 has significant drift. TVS shows zero drift which means no pulse-to-pulse degradation.

35
TVS ESD8V0R1B-02LS
MLV-1
MLV-2
30

25
TLP Current (A)

20

15

10

0
10 15 20 25 30
Breakdown Voltage (V)

Figure 33: Breakdown voltage drift at 1 mA force current. TLP-parameter: 50 Ω, 100 ns pulse width, 290 ps rise time.

Application Note Page 24 of 29 Rev. 1.3 - December 6, 2012

 Application Note No. 210

3.6 Degradation due to Multi-Pulse Stress

3.6 Degradation due to Multi-Pulse Stress

In this test the device is stressed with multiple pulses at a certain current level: 100 pulses at about 5 A, 100 pulses
at about 10 A, and so on, up to about 25 A to 30 A . The spot leakage drift is recorded for each stress pulse. In the
first experiment the DC leakage current at 5 V reverse working voltage is recorded and in the second experiment the
breakdown voltage drift at 1 mA force current is recorded using a fresh device. Each group of dots is representing
100 pulses. In total each device is stressed with about 500 to 600 pulses up to >25 A.

3.6.1 Spot Leakage Drift

Fig. 34 shows the multi-pulse DC spot leakage current drift at 5 V reverse working voltage. MLV-1 shows extremely
high drift and was destroyed at 25 A and about 100 pulses. MLV-2 shows significant multi-pulse drift. The TVS is
extremely stable and shows no multi-pulse degradation. The variation is due to the measurement limits of the source
meter at low currents (noise).

35
TVS ESD8V0R1B-02LS
MLV-1
MLV-2
30

25
TLP Current (A)

20

15

10

0
10-11 10-10 10-9 10-8 10-7 10-6 10-5
Spot Leakage Current (A)

Figure 34: Multi-pulse DC spot leakage current drift at 5 V reverse working voltage. TLP-parameter: 50 Ω, 100 ns
pulse width, 1 ns rise time.

Application Note Page 25 of 29 Rev. 1.3 - December 6, 2012

 Application Note No. 210

3.6 Degradation due to Multi-Pulse Stress

3.6.2 Breakdown Voltage Drift

Fig. 35 shows the multi-pulse breakdown voltage drift at 1 mA force current. MLV-1 and MLV-2 show significant multi-
pulse degradation. The TVS has zero drift in breakdown voltage at each group of 100 stress pulses up to >25 A (total
600 stress pulses).

35
TVS ESD8V0R1B-02LS
MLV-1
MLV-2
30

25
TLP Current (A)

20

15

10

0
10 15 20 25
Breakdown Voltage (V)

Figure 35: Multi-pulse breakdown voltage drift at 1 mA force current. TLP-parameter: 50 Ω, 100 ns pulse width, 1 ns
rise time.

Application Note Page 26 of 29 Rev. 1.3 - December 6, 2012

 Application Note No. 210

References

References
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[3] International Electrotechnical Commission, “Electromagnetic compatibility (EMC) - Electromagnetic compatibility
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[7] JEDEC Solid State Technology Association, “Recommended ESD Target Levels for HBM/MM Qualification”,
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[23] “MIL-STD-750D, Method 4026.3, Forward Recovery Voltage and Time”.

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 Application Note No. 210

References

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Author
Werner Simbürger

Copyright Notice
Section 2 is partially reprint of the publication [8] with granted permission by the ARMMS RF & Microwave Society,
19th to 20th November 2012 at Wyboston Lakes, Wyboston, UK.

Application Note Page 28 of 29 Rev. 1.3 - December 6, 2012

w w w . i n f i n e o n . c o m

Published by Infineon Technologies AG