Micro Project REPORT

on
Prepare Report On FPGA Design
SUBMITTED BY

Prajakta Rupchand Deshmukh

ENROLLMENT NO:-2200910317

Roll No: 19 (EJ6I)

GUIDED BY: (R. B. Sathe Sir)

ODD-24

(ELECTRONICS AND TELECOMMUNICATION ENGG.)

ACADEMIC SESSION 2023-24

DEPARTMENT OF ELECTRONICS AND TELECOMMUNICATION

ENGG.
GOVERNMENT POLYTECHNIC SAKOLI
 GOVERNMENT POLYTECHNIC
SAKOLI
DEPARTMENT OF ELECTRONICE AND TELECOMMUNICATION ENGG.

CERTIFICATE

This is to certify that the seminar report titled submitted Prepear Report on FPGA
Design. Prajakta Rupchand Deshmukhe of VI semester towards the partial
fulfilment of requirement for the award of diploma in electronics and
telecommunication.

DATE: 18/03/20224

YEAR: 2024-25

ACKNOWLEDGEMENT
I would like to place on record of our deep sense of gratitude to R. B. Sathe sir
lecturer, Dept. of Electronics & Telecommunication for her generous guidance,
help and useful suggestions.

I express our sincere gratitude to Prof. A. A. Ali, Head of Dept. of Electronics &
telecommunication, for his stimulating guidance, continuous encouragement and
supervision throughout the course of present work.

I am extremely thankful to Prof. S. P. Lambhade, Principal, for providing me

infrastructural facilities to work in, without which this work would not have been
possible.

THANK YOU

Name of Student

Prajakta R. Deshmukh

Enrollment No.2200910317
 INDEX

Sr. No. Content Page No.

1 Introduction 01

2 Working Principle/Theory 02

4 Applications 13

5 Advantages 13

6 Disadvantages 14

7 Conclusion 15

8 References 16
 Introduction

Digital electronics is concerned with circuits which represent information using a finite set of
output states [1] Most of the applications use in fact just two states, which are often labelled '0'
and '1' Behind this choice is the fact that the whole Boolean formalism then becomes available
for the solution of logic problems, and also that arithmetic using binary representations of
numbers is a very mature field.

Different mappings between the two states and the corresponding output voltages or currents
define different logic families. For example, the Transistor-Transistor Logic (TTL) family defines
an output as logic '1' if its voltage is above a certain threshold (typically 2.4 V). For the same
family, if we set the input threshold for logic '1' as 2 V, we will have a margin of 0.4 V which will
allow us to interconnect TTL chips inside a design without the risk of misinterpretation of logic
states. This complete preservation of information even in the presence of moderate amounts of
noise is what has driven a steady shift of paradigm from analog to digital in many applications.
Here we see as well another reason for the choice of binary logic: from a purely electrical point
of view, having only two different values for the voltages or currents used to represent states is
the safest choice in terms of design margins

Historically, TTL chips from the 74 series fuelled an initial wave of digital system designs in the
1970s. From this seed, we shall focus on the separate branches that evolved to satisfy the
demand. for programmability of different logic functions. By programmability, we mean the
ability of a designer to affect the logic behaviour of a chip after it has been produced in the
factory
 Abstract

This paper presents an introduction to digital hardware design using Field Programmable Gate
Arrays (FPGAs). After a historical introduction and a quick overview of digital design, the
internal structure of a generic FPGA is discussed. We then describe the design flow, ie, the steps
needed to go from design idea to actual working hardware. Digital signal processing is an
important area where FPGAs have found many applications in recent years. Therefore a
complete section is devoted to this subject. The paper finishes with a discussion of important
peripheral concepts essential for success in any project involving FPGAs.

This paper presents the overview of an FPGA system in which different complex arithmetic and
logical operations are performed by using a set of programumable and reconfigurable arrays of
various logic gates and the task of performing a single operation is distributed equally to a set
of given number of gates and the system is provided with a clock generator which provides the
necessary timing and control to the system with the help of an external oscillator which is set to
a given desired frequency. A set of instructions which is called as program is written to execute
a certain task which is required to perform a single part of a given set of operations to be
performed by the electronic circuit.

The language of programming like Very High Speed Integrated Circuits Hardware Description
Language (VHDL) and Verilog is used to program a logic gate like AND, OR, NOT, NAND, NOR,
EX-OR gates and the study of different modules is done to understand the working of the
programming language in order to gain preliminary knowledge about the syntax and
instructions which constitute the base of any digital system. A basic knowledge about the
language and its structured components like hardware modules and the commands is essential
to acquire a general hold over the understanding of FPGA.
Working

A field-programmable gate array (FPGA) is a type of configurable integrated circuit that can be
programmed or reprogrammed after manufacturing. FPGAs are part of a broader set of logic
devices referred to as programmable logic devices (PLDs). They consist of an array of
programmable logic blocks and interconnects that can be configured to perform various digital
functions. FPGAs are commonly used in applications where flexibility, speed, and parallel
processing capabilities are required, such as in telecommunications, automotive, aerospace,
and industrial sectors.

FPGA configuration is generally specified using a hardware description language (HDL), similar
to that used for an application-specific integrated circuit (ASIC). Circuit diagrams were
previously used to specify the configuration.

The logic blocks of an FPGA can be configured to perform complex combinational functions, or
act as simple logic gates like AND and XOR. In most FPGAs, logic blocks also include memory
elements, which may be simple flip-flops or more complete blocks of memory. [1] Many FPGAs
can be reprogrammed to implement different logic functions, allowing flexible reconfigurable
computing as performed in computer software.

FPGAs also have a role in embedded system development due to their capability to start system
software development simultaneously with hardware, enable system performance simulations
at a very early phase of the development, and allow various system trials and design iterations
before finalizing the system architecture.

FPGAs are also commonly used during the development of ASICs to speed up the simulation
process.
FPGA Design

Contemporary FPGAs have ample logic gates and RAM blocks to implement complex digital
computations. FPGAs can be used to implement any logical function that an ASIC can perform.
The ability to update the functionality after shipping, partial re-configuration of a portion of the
design and the low non-recurring engineering costs relative to an ASIC design (notwithstanding
the generally higher unit cost), offer advantages for many applications.

As FPGA designs employ very fast I/O rates and bidirectional data buses, it becomes a challenge
to verify correct timing of valid data within setup time and hold time. Floor planning helps
resource allocation within FPGAs to meet these timing constraints.

Some FPGAs have analog features in addition to digital functions. The most common analog
feature is a programmable slew rate on each output pin, allowing the engineer to set low rates
on lightly loaded pins that would otherwise ring or couple unacceptably, and to set higher rates
on heavily loaded high-speed channels that would otherwise ring or couple unacceptably, and
to set higher rates on heavily loaded high-speed channels that would otherwise run too slowly.

Also common are quartz-crystal oscillator driver circuitry, on-chip RC oscillators, and phase-
locked loops with embedded voltage-controlled oscillators used for clock generation and
management as well as for high-speed serializer-deserializer (SERDES) transmit clocks and
receiver clock recovery. Fairly common are differential comparators on input pins designed to
be connected to differential signaling channels.

A few mixed signal FPGAS have integrated peripheral analog-to-digital converters (ADCs) and
digital-to-analog converters (DACs) with analog signal conditioning blocks, allowing them to
operate as a system-on-a- chip (SoC). Such devices blur the line between an FPGA, which carries
digital ones and zeros on its internal programmable interconnect fabric, and field-
programmable analog array (FPAA). which carries analog values on its internal programmable
interconnect fabric.
Logic Blocks

The most common FPGA architecture consists of an array of logic blocks called configurable
logic blocks (CLBs) or logic array blocks (LABs) (depending on vendor), I/O pads, and routing
channels. [1] Generally, all the routing channels have the same width (number of signals).
Multiple I/O pads may fit into the height of one row or the width of one column in the array.

An application circuit must be mapped into an FPGA with adequate resources. While the
number of logic blocks and I/Os required is easily determined from the design, the number of
routing channels needed may vary considerably even among designs with the same amount of
logic. For example, a crossbar switch requires much more routing than a systolic array with the
same gate count.

Since unused routing channels increase the cost (and decrease the performance) of the FPGA
without providing any benefit, FPGA manufacturers try to provide just enough channels so that
most designs that will fit in terms of lookup tables (LUTs) and I/Os can be routed. This is
determined by estimates such as those derived from Rent's rule or by experiments with existing
designs.

In general, a logic block consists of a few logical cells. A typical cell consists of a 4-input LUT, a
full adder (FA) and a D-type flip-flop. The LUT might be split into two 3-input LUTs. In normal
mode those are combined into a 4-input LUT through the first multiplexer (mux). In arithmetic
mode, their outputs are fed to the adder. The selection of mode is programmed into the second
mux. The output can be either synchronous or asynchronous, depending on the programming
of the third mux. In practice, the entire adder or parts of it are stored as functions into the LUTs
in order to save space.
Hard blocks

Modern FPGA families expand upon the above capabilities to include higher-level functionality
fixed in silicon. Having these common functions embedded in the circuit reduces the area
required and gives those functions increased performance compared to building them from
logical primitives. Examples of these include multipliers, generic DSP blocks, embedded
processors, high-speed I/O logic and embedded memories.

Higher-end FPGAs can contain high-speed multi- gigabit transceivers and hard IP cores such as
processor cores, Ethernet medium access control units, PCI or PCI Express controllers, and
external memory controllers. These cores exist alongside the programmable fabric, but they are
built out of transistors instead of LUTs so they have ASIC-level performance and power
consumption without consuming a significant amount of fabric resources, leaving more of the
fabric free for the application-specific logic.

The multi-gigabit transceivers also contain high-performance signal conditioning circuitry along
with high-speed processor cores, Ethernet medium access control units, PCI or PCI Express
controllers, and external memory controllers. These cores exist alongside the programmable
fabric, but they are built out of transistors instead of LUTs so they have ASIC-level performance
and power consumption without consuming a significant amount of fabric resources, leaving
more of the fabric free for the application-specific logic.

The multi-gigabit transceivers also contain high-performance signal conditioning circuitry along
with high-speed serializers and deserializers, components that cannot be built out of LUTs.
Higher-level physical layer (PHY) functionality such as line coding may or may not be
implemented alongside the serializers and deserializers in hard logic, depending on the FPGA.
Soft Core

An alternate approach to using hard macro processors is to make use of soft processor IP cores that are
implemented within the FPGA logic. Nios II, MicroBlaze and Mico32 are examples of popular softcore
processors. Many modern FPGAs are programmed at run time, which has led to the idea of
reconfigurable computing or reconfigurable systems - CPUs that reconfigure themselves to suit the task
at hand. Additionally, new non-FPGA architectures are beginning to emerge. Software- configurable
microprocessors such as the Stretch S5000 adopt a hybrid approach by providing an array of processor
cores and FPGA-like programmable cores on the same chip.
Integration

In 2012 the coarse-grained architectural approach was taken a step further by combining the
logic blocks and interconnects of traditional FPGAs with embedded microprocessors and
related peripherals to form a complete system on a programmable chip. Examples of such
hybrid technologies can be found in the Xilinx Zynq-7000 all Programmable SoC, which includes
a 1.0 GHz dual-core ARM Cortex-A9 MPCore processor embedded within the FPGA's logic fabric,
or in the Altera Arria V FPGA, which includes an 800 MHz dual-core ARM Cortex-A9 MPCore.

The Atmel FPSLIC is another such device, which uses an AVR processor in combination with
Atmel's programmable logic architecture. The Microsemi SmartFusion devices incorporate an
ARM Cortex-M3 hard processor core (with up to 512 kB of flash and 64 kB of RAM) and analog
peripherals such as a multi-channel analog-to-digital converters and digital-to-analog
converters in their flash memory-based FPGA fabric.

Clocking

Most of the logic inside of an FPGA is synchronous circuitry that requires a clock signal. FPGAs
contain dedicated global and regional routing networks for clock and reset, typically
implemented as an H tree, so they can be delivered with minimal skew. FPGAs may contain
analog phase-locked loop or delay-locked loop components to synthesize new clock frequencies
and manage jitter.

Complex designs can use multiple clocks with different frequency and phase relationships,
each forming separate clock domains. These clock signals can be generated locally by an
oscillator or they can be recovered from a data stream. Care must be taken when building clock
domain crossing circuitry to avoid metastability. Some FPGAs contain dual port RAM blocks that
are capable of working with different clocks, aiding in the construction of building FIFOS and
dual port buffers that bridge clock domains.
3D architectures

To shrink the size and power consumption of FPGAs, vendors such as Tabula and Xilinx have
introduced 3D or stacked architectures. Following the introduction of its 28 nm 7-series FPGAs,
Xilinx said that several of the highest- density parts in those FPGA product lines will be
constructed using multiple dies in one package, employing technology developed for 3D
construction and stacked-die assemblies.

Xilinx's approach stacks several (three or four) active FPGA dies side by side on a silicon
interposer - a single piece of silicon that carries passive interconnect. The multi-die construction
also allows different parts of the FPGA to be created with different process technologies, as the
process requirements are different between the FPGA fabric itself and the very high speed 28
Gbit/s serial transceivers. An FPGA built in this way is called a heterogeneous FPGA.

Altera's heterogeneous approach involves using a single monolithic FPGA die and connecting
other dies and technologies to the FPGA using Intel's embedded multi die interconnect bridge
(EMIB) technology.
Applications of FPGA

• Processing of images in SDRs

• Weaponry for defence

• Prototype ASIC

• WCDMA, WiMAX, and other wireless communications

• Computers with high performance

• Various diagnostic tools are employed

• Therapeutic equipment

• Personal electronics

• Household set-top boxes, etc.

• Displays using flat panels.

Advantages of FPGA

• Parallel processing is possible using FPGA.

• Comparatively speaking, it performs better than a regular CPU.

• The price is reasonable.

• They assist you in quickly completing your product development. They may be quickly and
easily released on the market.
Disadvantages of FPGA

• It uses more energy.

• The power optimization process is out of the coders' hands.

• An FPGA can only be used when manufacturing is minimal.

• The programming required is more complex than plain C programming.

Conclusion

Field-programmable gate arrays, or FPGAs, are dynamic devices that allow for flexible hardware
implementation thanks to their programmable logic blocks and configurable interconnects.
Without the need for custom silicon, their architecture, which includes programmable elements
and embedded components, enables flexible digital circuit design. FPGAs are used in many
different industries for a variety of tasks, including hardware acceleration and real-time signal
processing. In conclusion, FPGAs are essential in the field of digital hardware design and a wide
range of applications because they provide a powerful blend of performance and adaptability.
References

[1] J.F. Wakerly, Digital Design: Principles and Practices, 4th ed. (Prentice Hall, Upper Saddle
River, NJ, 2006)

[2] A. Rushton, VHDL for Logic Synthesis, 2nd ed. (John Wiley & Sons, Chichester, 1998).

[3] U. Meyer-Baese, Digital Signal Processing with Field Programmable Gate Arrays, 3rd ed.
(Springer, Berlin, 2007).

[4] J.G. Proakis and D.K. Manolakis, Digital Signal Processing, 4th ed. (Prentice Hall, Upper
Saddle River, NJ, 2006).

[5] R. Andraka, A survey of CORDIC algorithms for FPGAs, Proc. 1998 ACM/SIGDA 6
International Symposium on Field Programmable Gate Arrays, Feb, 22-24, Monterrey, CA, USA,
pp. 191-200. URL: http://www.andraka.com/files/crdesrvy.pdf.

[6] M. Alexander, Power Supply Distribution (PDS) Design: Using bypass/decoupling

capacitors,XilinxURL.

http://www.xilinx.com/support/documentation/application notes/xapp623.pdf.