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Khushi
Khushi
On
Prepare Report on Implementation of general purpose using
VHDL
SUBMITTED BY
Khushi Dilip Tembare
ENROLLMENT NO:-2200910319
Even-2024
CERTIFICATE
This is to certify that the Micro Project report titled submitted (prepare Report
on Implementation of general purpose using VHDL.) by Khushi D. Tembare
of IV semester towards the partial fulfilment of requirement for the award of
diploma in electronics and telecommunication.
DATE:
YEAR: 2023-24
I would like to place on record of our deep sense of gratitude to Prof. R. B. Sathe
sir. lecturer, Dept. of Electronics & Telecommunication for her generous guidance,
help and useful suggestions.
I express our sincere gratitude to Prof. A. A. Ali, Head of Dept. of Electronics &
telecommunication, for his stimulating guidance, continuous encouragement and
supervision throughout the course of present work.
I am extremely thankful to Prof. S. P. Lambhade, Principal, for providing me
infrastructural facilities to work in, without which this work would not have been
possible.
THANK YOU
1 Introduction
2 Abstract
[2]. It is shown and proved that the PWM technique is widely used in most of the
industrial power controls. The developments of high frequency PWM generator
architecture for power converter control using FPGA/ CPLD ICs are more versatile
and easy to implement. The resulting PWM frequency depends on the target FPGA
or CPLD device speed grade and the duty cycle resolution.
[3].Requirement was studied and presented that the PLD (FPGA) based digital
controllers are far better than Digital Signal Processors based as they have better
dynamic performance and control capabilities[4]. In many market segments, such as
handheld devices, PLDs have found acceptance due to new product architectures that
reduce power consumption. feature new packaging options, lower unit cost and
shorter design cycle. Present work describes the design and development of Generic
Complex Programmable Device. (CPLD) board for various applications explained
in preceding paragraph
Need of CPLD.
• The Programmable Logic Devices (PLDs) such as PLAs and PALS have
limited number of inputs, product terms and outputs. These devices can
support up to about 32 total number of inputs and outputs only.
• For implementation of circuits that require more inputs and outputs than that
are available in a single SPLD chip, either multiple SPLD chips can be
employed. But this has also some limitations.
Concepts of CPLD.
• A typical PAL has 8 macro cells, if each macro cell represents about 20
equivalent gates, than the PAL can accommodate a circuit that needs up to
about 160 gates.
• For a circuit requiring very large number of gates, CPLDs having large
number of macrocells (say 512 macro cells) can implement circuits of up to
about 10 thousand equivalent gates i.e. they are similar to SPLDs except that
the CPLD is equivalent of 2 to 64 SPLDs.
• They are as fast as PLAs but more They are digital ICs that are just like a
large number of PALs in a single silicon chip connected to each other
through a cross point switch.
• They are digital ICs that are just like a large number of PALs in a single
silicon chip connected to each other through a cross point switch.
Conclusion :-
References :-
• WWW.geeksfforgeeks.org>VSAT
• WWW.birdsat-vsat.com>application
• WWW.investopedia.com>term>vsat
• WWW.vsatantenna.net>post