Motherboard Repair Tutorial (3)

Study:South Maintenance ... Source: Hits:12871 Update Time :2005-7-26

Main board the total line frame structure

Use a variety of devices to exchange data with a single bus, mutual interference between
the signals. Therefore, the actual design of the motherboard bus, in theCPU, system
memory,I / Oexpansion slots, and peripheral interface chip between the added buffer (whose
role is to transmit the signal isolation, shaping, delay), these buffers will a single bus
into the different levels of bus.
1, CPUbus will beCPU(through the address buffers and data buffers)and peripheral chips
connected together to achieve the memory,I / Ochannels and peripheral interfaces, data
access.
2, the system memory bus for connecting the memory controller and memory (through buffers),
to achieve the memory data access.
3, I / Ochannel bus (also known as the expansion bus) to connectI / Oexpansion slots on a
variety of expansion cards,CPUand system memory through theI / Ochannel bus expansion
boards with a variety of data exchange. For the various board manufacturers
compatibility,I / Ochannel bus must have a unified standard, differentI / Ochannel bus of
the data bus, address bus bit width is different from the work of different
frequencies.
4, the peripheral interface bus is connected to the external interface controller on the
motherboard and the keyboard controller bus, peripheral interface bus connecting the
main interrupt controller chip,DMAcontroller, timer/counter, parallel port, keyboard
interface.

Notes:
1" ISAbus

ISAbus is the industry standardIBMCorporationin 1984for the launch ofPC / ATmachines and
establishment of the16-bit system bus standard, also calledATbus.ISAbus slot, a total
of98pins, the data lines are16articles, the address lines are27articles, the other for the
control signal lines, ground lines, power lines and clock lines. Data transfer rate of8MB /
S, but now the motherboard has been phasing outISAbus support, such as810,815EPmotherboard
generally not withISAslot.ISA-bus controlled by the Southbridge.

ISA at the end , as the graph

Aside Bside
Aside comment Bside notes
I/ 1 1 GND Ground
0 CHCKready5Vlevel
★lower eight data 2 2 ★ ★reset pin, jump and
lines, there is any jump down
way open or short 3 3 +5 Vpower supply pin
circuit will not 4 4 Empty legsNC, for the soft
boot. interrupt
5 5 -5Vpower supply pin
6 6 DRQ2request, active high
7 7 -12Vpower supply pin
8 8 OWSwaiting for the signal,
active low
9 9 +12 Vpower supply pin
I / Ochannel ready 10 10 GNDGround
AENAddress enable 11 11 ★SMEMWdata memory write
signal data on the bus, or do not
readA.
★20address lines, 12 12 ★SMEMRcommand output to
to latch the the data memory data bus, or
address, for memory do not readA
andI / Odevice 13 13 I / OW write
address. 14 14 I / OR Reading
15 15 DACK3 #active low response
16 16 DRQ3request
17 17 DACK1 #active low
18 18 DRQ1request
19 19 REFRESH #indicates a
refresh cycle
20 20 ★ ★ ★SYSCLKSystem Clock
21 21 ★IRQ7control the printer
port2
22 22 ★IRQ6control of the floppy
disk
23 23 ★IRQ5control the printer
port1
24 24 ★IRQ4controlCOM2
25 25 ★IRQ3controlCOM1
26 26 DACK2 #Otherwise, do not
readA
27 27 TCPulse
28 28 BALEaddress latch enable
signal
29 29 +5 Vpower supply pin
30 30 OSC CLKbasic clock
 31 31 GND
ISA at the end , as the graph
Cside Dsurface
CSurface comment Dsurface annotations
SBHEhigh byte 1 1 MEM CS16 # ★ ★ ★Bsurface an
enable signal 16-bit chip select signal important test points:
★7address lines, 2 2 I / O CS16 #chip select ■B2:RESET Reset (up
non-latched address and down, start an
3 3 IRQ10 NC
instant measurement)
4 4 IRQ11 NC ■ no reset:PG, gates,
5 5 IRQ12 with the coprocessor resistors and capacitors
6 6 ★IRQ15controlIDE2 around the South Bridge
7 7 ★IRQ14controlIDE1 or South Bridge bad bad
8 8 DACK0 #responses ■B20:SYS CLK system
MEMRMemory Read 9 9 DRQ0request clock
■B30:OSC CLK basic
MEMWmemory write 10 10 DACK5 #responses
clock; noB30crystal bad
★High eight data 11 11 DRQ5request or no power generator
lines 12 12 DACK6 #responses ■ThereOSC(the basic
13 13 DRQ6request clock) withoutSYS
14 14 DACK7 #responses CLK(system clock):
15 15 DRQ7request South Bridge or South
16 16 ★+5 V Bridge peripheral
17 17 resistance of the bad
MASTER #control line
bad.
18 18 GND
2, PCI bus
PCIbus is not attached to a specific processor local bus. In terms of structure,PCIis
theCPUand peripheral inserted between the level of bus,CPUbus and thePCIbus is connected by
a bridge circuit,PCIbus can be attached graphics controller,IDEdevices, networks and other
high-speed device controller .
PCIbus operating clock frequency of33Mhz, bit width is32bits (can be extended to64bits),
bandwidth of133MB / S, can support multiple peripheral devices, and can remain at high clock
frequency performance.PCIbus supports bus-mastering technology that allows intelligent
devices to obtain the necessary control over the bus.
As technology advances, the traditional32-bit33MHZthePCIbus, the system has been unable
to meet the needs of all equipment to transmit data, so the motherboard chip plants are
on the board's overall structure has been transformed, mainly in the following
modification of the case:
1) increase the system memory bus and front side bus bandwidth.
2) The originalPCIbus, the transfer of management of South Bridge chips, only used
to connectPCIexpansion slot on the device.
3) increase in North and South Bridges bridge between the bus (the originalPCIbus)
bandwidth.
 4) will require large amounts of data display interface toAGPbus in the form from
the originalPCIbus independent, articulated in the North Bridge chip, provides
data separately for the video card.
★ Special Note:PCIbus is32-bit bus, and can be extended to64-bit,124pins (in fact
removed the4a locator card has120pins),ADlines are32articles,operating
frequency33MHZ/66MHZ, the largest transfer rate of133MB / S. Bus Width32-bit
(5V),64-bit3.3V.PCIhas four voltage:3.3V,5V,+12V ,-12V. There is a clock, a
reset.4aC / BEline, if the problem will not boot.
PCIbus (32bit) Bottom view

1● ● -
12V
2● +12 ● ●1
V ●
+5 ● ● +5 ●2
V 3● V
4● ● ● ●3
+5 V
5● +5 ● ●4
V ●
6● +5 ● ●5
V ●
GND 7 ● ● ●6
●
RESET 8 ● ● ●7
●
9● +5 ● ●8 CLK
V ●
10● ● ● +5 ●9
V
+3.3 V AD ● AD ●10 A
11● ● D
AD 12 AD ● AD ●11
● ●
AD 13 ● ● 3.3 ●12 AD
● V
+3.3 V ● ● AD ●13 C /
14● BE
AD 15 AD ● AD ●14
● ●
AD 16 ● ● 3.3 ●15 A
● V D
 +3.3 V AD ● C / ●16 A
17● ● BE D
18● ● ● ●17
19● ● ● ●18
+3.3 V ● ● ●19
20●
21● ● ● 3.3 ●20
V
22● ● ● 3.3 ●21
V
+3.3 V AD ● AD ●22 C /
23● ● BE
AD 24 AD ● AD ●23
● ●
AD 25 ● ● ●24 AD
●

C / BE ●
● AD
3.3V 26 AD ● AD ● 3
● ● .3V
AD 27 ● ● ● AD ●
AD
AD 28 ● AD ● GND ●
● AD
+5 ● ● +5 ●
V 29 V
●
+5 +5 ● +5 ● +
V 30 V ● V 5 V
●
Data transfer rate= bus frequency (33.333MHZ) * data bandwidth (32bit) / 8
= 133MB / S
PCI reset signal is actually the signal from the power supply through a resistor PG,
direct supply of PCI reset, IDE reset. PCI Reset (A8, 5V level) only go up not down.
PCI clock is generated by the clock generator, or a single resistor leads through the
exclusion Road, PCI clock, but also by such a small number of IC PG
Signal initialization.

1, AGP bus
AGP (Accelerated Graphics Port) is designed to improve the video bandwidth of a bus
specification, first appeared in the 440LX chipset. In a system with AGP, video card through
the AGP bus, chipset and main memory is connected directly to read the display data in main
memory, improved graphics chip and data transfer between main memory speed, PCI bus, reducing
the load, conducive to full performance of other PCI devices.
AGP bus has experienced AGP1X, AGP2X, 4X, 8X phases. AGP bus operating clock frequency
is 66MHZ, bit width is 32 bits. 1X mode bandwidth of 266MB / S (66MHZ * 32bit / 8); 2X mode
dual-pulse along the data transmission technology, can be transmitted per clock cycle 2 data,
the bandwidth increase to 533MB / S (2 * 66MHZ * 32bit / 8); 4X and 8X mode with the
transmission in each clock cycle 4 times and 8 times the way of data (equivalent to increase
the AGP bus frequency), bandwidth increased to 1GB / S (4 * 66MHZ * 32bit / 8) and 2.1GB / S
(8 * 66MHZ * 32bit / 8).
INTEL Corporation AGP8X is a new release of the graphics port specifications, has been
ATI, NVIDIA, Matrox graphics card chips such as the world's major supplier and manufacturer
of graphics card support. AGP8X memory is needed to provide large amounts of data, will be
mainly used in the Pentium4 system, because Pentium4 motherboard supports Rambus or DDR high
speed memory, the memory bus can provide 3.2GB / S of bandwidth, the performance AGP8X able
to play to the limit.

Special Note: ▲AGP has a reset pin, a clock pin, 8 A line (address line), 32 D line (data line). Power is: 3.3V, 5V, 12V.
▲AGP-to-ground resistance data line error range of each other can be 15 ohms.
▲AGP-to-ground resistance of the address line of the error range of each other can
be 10 ohms.
▲Northbridge AGP clock is output.
▲ AGP and PCI reset Reset connected.
▲ checkingAGP, note the choice of AGP graphics cards are a fewX's.
▲ 1X, 2X voltage is 3.3V, pin is 124PIN; 4X voltage is 3.3V (individual to 1.5V),
pin is 132PIN; 8X voltage is 1.5V, pin is 132PIN, (each a 124PIN). 12V
auxiliary voltage.
4 , the memory
Short memory, internal memory for storing information to be processed and the current
general information of semiconductor chips. Small capacity, but access quickly.
★memory includingRAM, ROM and Cache.
RAM: Random Access Memory
RAM is the computer's main memory, people used to be known as RAM memory. RAM is
the most important feature of the data will be shut down or power loss. (The larger the
computer memory, can deal with the greater amount of information.)
The RAM 586 used computers have EDO RAM (dynamic memory) and SDRAM (synchronous
dynamic RAM).
DDR SDRAM (SDRAM Ⅱ) for the dual-rate memory.
R DRAM (RAM BUS DRAM)
Note: 72 lines of memory 5V, 168 line memory 3.3V, 184 line is 2.5V.
168 lines of memory is not bad only the clock voltage.

Line 168 pin DIMM (Bottom View)

1 GND Data line GND Data line
2 Data line Data line Data line Data line
3 Data line VCC Data line VCC
4 Data line Data line Data line Data line
5 Data line Data line Data line Data line

1 Data line GND Data line GND

2 Data line Data line Data line Data line
3 Data line Data line Data line Data line
4 Data line VCC Data line VCC
5 Data line Data line Data line Data line
6 CB4 CB5 CB0 CB1
7 GND No GND No
connection connection
8 NC VCC No VCC
connection
9 CAS DQM4 / WE DQM0
10 DQM5 CS1 DQM1 CS0
11 RAS GND D / C GND
12 Address Address Address Address
Line Line Line Line
13 Address Address Address Address
Line Line Line Line
14 Address BA0 Address A10/AP
Line Line
15 Address VCC BA1 VCC
Line

1 CLK Address VCC CLK

Line
2 GND CKE0 GND DC
3 CS3 DQM6 CS2 DQM2
4 DQM7 GND DQM3 DC
5 VCC No VCC No
connection connection
6 No CB6 No CB2
connectio connection
n
7 CB7 GND CB3 GND
8 Data line Data line Data line Data line
9 Data line Data line Data line Data line
10 VCC Data line VCC Data line
11 No VREF No VREF
 connectio connection
n
12 No GND CKE1 GND
connectio
n
13 Data line Data line Data line Data line
14 Data line GND Data line GND
15 Data line Data line Data line Data line
16 Data line Data line Data line Data line
17 VCC Data line VCC Data line
18 Data line Data line Data line Data line
19 Data line GND Data line GND
20 CLK No CLK No
connection connection
21 SA0 SA1 No CDA
connection
22 SA2 VCC = 3.3V SCL VCC