SN54/74LS112A

DUAL JK NEGATIVE
EDGE-TRIGGERED FLIP-FLOP
The SN54 / 74LS112A dual JK flip-flop features individual J, K, clock, and
asynchronous set and clear inputs to each flip-flop. When the clock goes
HIGH, the inputs are enabled and data will be accepted. The logic level of the DUAL JK NEGATIVE
J and K inputs may be allowed to change when the clock pulse is HIGH and EDGE-TRIGGERED FLIP-FLOP
the bistable will perform according to the truth table as long as minimum set-up
and hold time are observed. Input data is transferred to the outputs on the LOW POWER SCHOTTKY
negative-going edge of the clock pulse.

LOGIC DIAGRAM (Each Flip-Flop) J SUFFIX

CERAMIC
CASE 620-09
16
1

Q Q
5(9) 6(7)

N SUFFIX
PLASTIC
CLEAR (CD) SET (SD) CASE 648-08
16
15(14) 4(10)
J K 1
3(11) 2(12)
1(13)
CLOCK (CP) D SUFFIX
SOIC
16
1 CASE 751B-03

ORDERING INFORMATION
SN54LSXXXJ Ceramic
MODE SELECT — TRUTH TABLE SN74LSXXXN Plastic
SN74LSXXXD SOIC
INPUTS OUTPUTS
OPERATING MODE
SD CD J K Q Q
Set L H X X H L
LOGIC SYMBOL
Reset (Clear) H L X X L H
*Undetermined L L X X H H 4 10
Toggle H H h h q q
Load “0” (Reset) H H l h L H SD SD
11
Load “1” (Set) H H h l H L 3 J Q 5 J Q 9
Hold H H l l q q
1 CP 13 CP
* Both outputs will be HIGH while both SD and CD are LOW, but the output states
are unpredictable if SD and CD go HIGH simultaneously. 2 K CD Q 6 12 K C Q 7
D
H, h = HIGH Voltage Level
L, I = LOW Voltage Level
15 14
X = Don’t Care
l, h (q) = Lower case letters indicate the state of the referenced input (or output)
l, h (q) = one set-up time prior to the HIGH to LOW clock transition. VCC = PIN 16
GND = PIN 8

FAST AND LS TTL DATA

5-1
 SN54/74LS112A

GUARANTEED OPERATING RANGES

Symbol Parameter Min Typ Max Unit
VCC Supply Voltage 54 4.5 5.0 5.5 V
74 4.75 5.0 5.25
TA Operating Ambient Temperature Range 54 – 55 25 125 °C
74 0 25 70
IOH Output Current — High 54, 74 – 0.4 mA
IOL Output Current — Low 54 4.0 mA
74 8.0

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)

Limits
S b l
Symbol P
Parameter Min Typ Max U i
Unit T
Test C di i
Conditions
Guaranteed Input HIGH Voltage for
VIH Input HIGH Voltage 2.0 V
All Inputs
54 0.7 Guaranteed Input
p LOW Voltage
g for
VIL Input LOW Voltage V
74 0.8 All Inputs

VIK Input Clamp Diode Voltage – 0.65 – 1.5 V VCC = MIN, IIN = – 18 mA
54 25
2.5 35
3.5 V VCC = MIN
MIN,, IOH = MAX,
MAX, VIN = VIH
VOH O
Output HIGH Voltage
V l
74 2.7 3.5 V or VIL per Truth Table

54, 74 0.25 0.4 V IOL = 4.0 mA VCC = VCC MIN,

VOL Output LOW Voltage VIN = VIL or VIH
74 0.35 0.5 V IOL = 8.0 mA per Truth Table

J, K 20
Set, Clear 60 µA VCC = MAX, VIN = 2.7 V
Clock 80
IIH Input HIGH Current
J, K 0.1
Set, Clear 0.3 mA VCC = MAX, VIN = 7.0 V
Clock 0.4
Input LOW Current J, K – 0.4
IIL mA VCC = MAX, VIN = 0.4 V
Clear, Set, Clk – 0.8
IOS Short Circuit Current (Note 1) – 20 – 100 mA VCC = MAX
ICC Power Supply Current 6.0 mA VCC = MAX
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.

AC CHARACTERISTICS (TA = 25°C, VCC = 5.0 V)

Limits
S b l
Symbol P
Parameter Min Typ Max U i
Unit T
Test C
Conditions
di i
fMAX Maximum Clock Frequency 30 45 MHz
VCC = 5.0
50V
tPLH Propagation
p g Delay,
y, Clock 15 20 ns
CL = 15 pF
tPHL Clear, Set to Output 15 20 ns

AC SETUP REQUIREMENTS (TA = 25°C, VCC = 5.0 V)

Limits
S b l
Symbol P
Parameter Min Typ Max U i
Unit T
Test C
Conditions
di i
tW Clock Pulse Width High 20 ns
tW Clear, Set Pulse Width 25 ns
VCC = 5
5.0
0V
ts Setup Time 20 ns
th Hold Time 0 ns

FAST AND LS TTL DATA

5-2