Apb Uvm TB

@shraddha_pawankar
Date:24/07/2023
@shraddha_pawankar
DESIGN.SV
module apb_ram (
input presetn,
input pclk,
input psel,
input penable,
input pwrite,
input [31:0] paddr, pwdata,
output reg [31:0] prdata,
output reg pready, pslverr
);
reg [31:0] mem [32];

typedef enum {idle = 0, setup = 1, access = 2, transfer = 3} state_type;
state_type state = idle;
always@(posedge pclk)
begin
if(presetn == 1'b0) //active low

begin
state <= idle;
prdata <= 32'h00000000;
pready <= 1'b0;
pslverr <= 1'b0;

for(int i = 0; i < 32; i++)
begin
@shraddha_pawankar
Date:24/07/2023
mem[i] <= 0;
end
end
else
begin
case(state)
idle :
begin
prdata <= 32'h00000000;

pready <= 1'b0;
pslverr <= 1'b0;
state <= setup;
end
setup: ///start of transaction

begin
if(psel == 1'b1)
state <= access;
else
state <= setup;

end
access:
begin
if(pwrite && penable)
begin
if(paddr < 32)
begin
mem[paddr] <= pwdata;
state <= transfer;
pslverr <= 1'b0;
@shraddha_pawankar
Date:24/07/2023
pready <= 1'b1;

end
else
begin
state <= transfer;
pready <= 1'b1;
pslverr <= 1'b1;
end
end
else if (!pwrite && penable)
begin
if(paddr < 32)
begin
prdata <= mem[paddr];

state <= transfer;
pready <= 1'b1;
pslverr <= 1'b0;
end
else
begin
state <= transfer;
pready <= 1'b1;
pslverr <= 1'b1;
prdata <= 32'hxxxxxxxx;

end
end
else
state <= setup;
end
@shraddha_pawankar
Date:24/07/2023
transfer: begin
state <= setup;
pready <= 1'b0;
pslverr <= 1'b0;

end
default : state <= idle;
endcase
end
end
endmodule
///////////////////////////////////////////////////////////////////////////////////////////////
apb_intf.sv
interface apb_if ();
// Signals
logic pclk;
logic presetn;
logic [31:0] paddr;
logic pwrite;
logic [31:0] pwdata;

logic penable;
logic psel;
logic [31:0] prdata;
logic pslverr;
logic pready;
endinterface
///////////////////////////////////////////////////////////////////////////////////////////
apb_seq_item.sv
typedef enum bit [1:0] {readd = 0, writed = 1, rst = 2} oper_mode;
class apb_seq_item extends uvm_sequence_item;
@shraddha_pawankar
Date:24/07/2023
ùvm_object_utils(apb_seq_item)
rand oper_mode op;
rand logic PWRITE;

rand logic [31 : 0] PWDATA;
rand logic [31 : 0] PADDR;
logic PREADY;
logic PSLVERR;
logic [31: 0] PRDATA;

constraint addr_c { PADDR <= 31; }
function new(string name = "apb_seq_item");

super.new(name);
endfunction
endclass
//////////////////////////////////////////////////////////////////////////////////////////////
apb_seq.sv
class write_data extends uvm_sequence#(apb_seq_item);
ùvm_object_utils(write_data)
apb_seq_item tx;
function new(string name ="write_data");
super.new(name);
endfunction
virtual task body();

repeat(15)
begin
tx = apb_seq_item::type_id::create("tx");
@shraddha_pawankar
Date:24/07/2023
start_item(tx);
tx.randomize();
tx.op = writed;
finish_item(tx);
end
endtask
endclass
///////////////////////////////////////////////////////////////////
class read_data extends uvm_sequence#(apb_seq_item);
ùvm_object_utils(read_data)
apb_seq_item tx;
function new(string name ="read_data");
super.new(name);
endfunction

repeat(15)
begin
start_item(tx);
tx.randomize();
tx.op = readd;
@shraddha_pawankar
Date:24/07/2023
finish_item(tx);
end
endtask
endclass
////////////////////////////////////////////////////////////////////
class write_read extends uvm_sequence#(apb_seq_item); //////read after write
ùvm_object_utils(write_read)
apb_seq_item tx;
function new(string name = "write_read");
super.new(name);
endfunction

repeat(15)
begin
start_item(tx);
tx.randomize;
tx.op = writed;
finish_item(tx);
start_item(tx);
tx.randomize();
tx.op = readd;
finish_item(tx);
end
@shraddha_pawankar
Date:24/07/2023
endtask
endclass
////////////////////////////////////////////////////////////////////////////////////
apb_sqr.sv
class apb_sqr extends uvm_sequencer#(apb_seq_item);
ùvm_component_utils(apb_sqr)
function new(string name="",uvm_component parent);

super.new(name,parent);
endfunction
endclass
////////////////////////////////////////////////////////////////////////////////////////////
apb_drv.sv
class apb_drv extends uvm_driver #(apb_seq_item);
ùvm_component_utils(apb_drv)
virtual apb_if vif;

apb_seq_item tx;

endfunction
function void build_phase(uvm_phase phase);

super.build_phase(phase);
uvm_config_db#(virtual apb_if)::get(this,"","intf",vif);
@shraddha_pawankar
Date:24/07/2023
endfunction
task run_phase(uvm_phase phase);

forever
begin
seq_item_port.get_next_item(tx);
if(tx.op == rst)
begin
vif.presetn <= 1'b0;
vif.paddr <= 'h0;
vif.pwdata <= 'h0;
vif.pwrite <= 'b0;
vif.psel <= 'b0;

vif.penable <= 'b0;
@(posedge vif.pclk);
end
else if(tx.op == writed)

begin
vif.psel <= 1'b1;
vif.paddr <= tx.PADDR;
vif.pwdata <= tx.PWDATA;

vif.pwrite <= 1'b1;
vif.penable <= 1'b1;
@(negedge vif.pready);
@shraddha_pawankar
Date:24/07/2023
end
else if(tx.op == readd)
begin
vif.psel <= 1'b1;
vif.paddr <= tx.PADDR;
vif.pwrite <= 1'b0;
end
seq_item_port.item_done();
end
endtask
endclass
///////////////////////////////////////////////////////////////////////////////////////////////
apb_mon.sv
class apb_mon extends uvm_monitor;
ùvm_component_utils(apb_mon)
uvm_analysis_port#(apb_seq_item) mon_ap;
apb_seq_item tx;
virtual apb_if vif;

@shraddha_pawankar
Date:24/07/2023

endfunction

tx=apb_seq_item::type_id::create("tx");
mon_ap=new("mon_ap",this);
if(!uvm_config_db#(virtual apb_if)::get(this,"","intf",vif))
ùvm_error("MON","Unable to access Interface");
endfunction

forever
begin
if(!vif.presetn)
begin
tx.op = rst;
mon_ap.write(tx);
end
else if (vif.presetn && vif.pwrite)

begin
tx.op = writed;
tx.PWDATA = vif.pwdata;
@shraddha_pawankar
Date:24/07/2023
tx.PADDR = vif.paddr;
tx.PSLVERR = vif.pslverr;
mon_ap.write(tx);
end
else if (vif.presetn && !vif.pwrite)

begin
tx.op = readd;
tx.PADDR = vif.paddr;
tx.PRDATA = vif.prdata;
tx.PSLVERR = vif.pslverr;
mon_ap.write(tx);
end
end
endtask
endclass
///////////////////////////////////////////////////////////////////////////////////////
apb_agent.sv
class apb_agent extends uvm_agent;
ùvm_component_utils(apb_agent)

endfunction
apb_sqr sqr;
apb_drv drv;
@shraddha_pawankar
Date:24/07/2023
apb_mon mon;
sqr=apb_sqr::type_id::create("sqr",this);
drv=apb_drv::type_id::create("drv",this);
mon=apb_mon::type_id::create("mon",this);
endfunction
function void connect_phase(uvm_phase phase);

super.connect_phase(phase);
drv.seq_item_port.connect(sqr.seq_item_export);
endfunction
endclass
///////////////////////////////////////////////////////////////////////////////////////////////
apb_scb.sv
class apb_scb extends uvm_scoreboard;
ùvm_component_utils(apb_scb)
uvm_analysis_imp#(apb_seq_item,apb_scb) scb_ip;
bit [31:0] array[32] = '{default:0};

bit [31:0] addr = 0;
bit [31:0] data_rd = 0;

endfunction
@shraddha_pawankar
Date:24/07/2023

scb_ip=new("scb_ip",this);
endfunction
function void write(apb_seq_item tx);

//////////////////////////////////////////////
if(tx.op == rst)
begin
ùvm_info("SCB", "SYSTEM RESET DETECTED", UVM_NONE);
end
////////////////////////////////////
else if (tx.op == writed)

begin
if(tx.PSLVERR == 1'b1)
begin
ùvm_info("SCB", "SLV ERROR during WRITE OP", UVM_NONE);
end
else
begin
array[tx.PADDR] = tx.PWDATA;
ùvm_info("SCB", $sformatf("DATA WRITE OP addr:%0d, wdata:%0d
arr_wr:%0d",tx.PADDR,tx.PWDATA, array[tx.PADDR]), UVM_NONE);
end
end
/////////////////////////////////////////////////////////
else if (tx.op == readd)

@shraddha_pawankar
Date:24/07/2023
begin
if(tx.PSLVERR == 1'b1)
begin
ùvm_info("SCO", "SLV ERROR during READ OP", UVM_NONE);

end
else
begin
data_rd = array[tx.PADDR];
if (data_rd == tx.PRDATA)
ùvm_info("SCO", $sformatf("DATA MATCHED : addr:%0d,
rdata:%0d",tx.PADDR,tx.PRDATA), UVM_NONE)
else
ùvm_info("SCB",$sformatf("TEST FAILED : addr:%0d, rdata:%0d
data_rd_arr:%0d",tx.PADDR,tx.PRDATA,data_rd), UVM_NONE)
end
end
endfunction
endclass
//////////////////////////////////////////////////
apb_env.sv
class apb_env extends uvm_env;
ùvm_component_utils(apb_env)

endfunction
apb_agent agent;
apb_scb scb;
@shraddha_pawankar
Date:24/07/2023

agent = apb_agent::type_id::create("agent",this);
scb = apb_scb::type_id::create("scb",this);
endfunction
function void connect_phase(uvm_phase phase);
super.connect_phase(phase);
agent.mon.mon_ap.connect(scb.scb_ip);
endfunction
endclass
////////////////////////////////////////////////////////////////////
apb_test.sv
class apb_test extends uvm_test;
ùvm_component_utils(apb_test)

endfunction
apb_env env;
write_data seq1;
read_data seq2;
write_read seq3;

@shraddha_pawankar
Date:24/07/2023
env = apb_env::type_id::create("env",this);
seq1 = write_data::type_id::create("seq1");
seq2 = read_data::type_id::create("seq2");
seq3 = write_read::type_id::create("seq3");
endfunction
function void end_of_elaboration_phase(uvm_phase phase);

super.end_of_elaboration_phase(phase);
ùvm_info("TEST",sprint(),UVM_LOW)
endfunction

phase.raise_objection(this);
seq1.start(env.agent.sqr);
#20
phase.drop_objection(this);
endtask
endclass
////////////////////////////////////////////////////////////////////////////////////////
testbench.sv
ìnclude "uvm_macros.svh"
import uvm_pkg::*;
ìnclude "apb_intf.sv"
ìnclude "apb_seq_item.sv"
ìnclude "apb_seq.sv"
ìnclude "apb_sqr.sv"
ìnclude "apb_drv.sv"
@shraddha_pawankar
Date:24/07/2023
ìnclude "apb_mon.sv"
ìnclude "apb_agent.sv"
ìnclude "apb_scb.sv"
ìnclude "apb_env.sv"
ìnclude "apb_test.sv"
module tb;
apb_if pif();
apb_ram dut (.presetn(pif.presetn),

.pclk(pif.pclk),
.psel(pif.psel),
.penable(pif.penable),
.pwrite(pif.pwrite),
.paddr(pif.paddr),
.pwdata(pif.pwdata),
.prdata(pif.prdata),
.pready(pif.pready),
.pslverr(pif.pslverr));
initial begin
pif.pclk <= 0;
end
always #10 pif.pclk <= ~pif.pclk;
initial begin
uvm_config_db#(virtual apb_if)::set(null, "*", "intf", pif);
run_test("apb_test");
@shraddha_pawankar
Date:24/07/2023
end
initial begin
$dumpfile("dump.vcd");
$dumpvars;
end
endmodule
OUTPUT:
# KERNEL: UVM_INFO /home/runner/apb_scb.sv(36) @ 10: uvm_test_top.env.scb [SCB]
DATA WRITE OP addr:29, wdata:3518879974 arr_wr:3518879974
TEST FAILED : addr:12, rdata:x data_rd_arr:0
# KERNEL: UVM_INFO /home/runner/apb_scb.sv(52) @ 1090: uvm_test_top.env.scb [SCO]
DATA MATCHED : addr:19, rdata:3667410626
@shraddha_pawankar
Date:24/07/2023
# KERNEL: UVM_INFO /home/build/vlib1/vlib/uvm-1.2/src/base/uvm_objection.svh(1271)
@ 3570: reporter [TEST_DONE] 'run' phase is ready to proceed to the 'extract' phase
# KERNEL: UVM_INFO /home/build/vlib1/vlib/uvm-
1.2/src/base/uvm_report_server.svh(869) @ 3570: reporter [UVM/REPORT/SERVER]
# KERNEL: --- UVM Report Summary ---
@shraddha_pawankar
Date:24/07/2023
# KERNEL:
# KERNEL: ** Report counts by severity
# KERNEL: UVM_INFO : 64
# KERNEL: UVM_WARNING : 0
# KERNEL: UVM_ERROR : 0
# KERNEL: UVM_FATAL : 0
https://www.edaplayground.com/x/dMch

Apb Uvm TB

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Apb Uvm TB

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@shraddha_pawankar

reg [31:0] mem [32];

if(presetn == 1'b0) //active low

pslverr <= 1'b0;

prdata <= 32'h00000000;

setup: ///start of transaction

state <= setup;

pready <= 1'b1;

prdata <= mem[paddr];

prdata <= 32'hxxxxxxxx;

pslverr <= 1'b0;

logic [31:0] pwdata;

rand oper_mode op;

rand logic PWRITE;

logic [31: 0] PRDATA;

function new(string name = "apb_seq_item");

virtual task body();

virtual task body();

virtual task body();

function new(string name="",uvm_component parent);

virtual apb_if vif;

function new(string name="",uvm_component parent);

function void build_phase(uvm_phase phase);

task run_phase(uvm_phase phase);

vif.psel <= 'b0;

else if(tx.op == writed)

vif.presetn <= 1'b1;

else if(tx.op == readd)

virtual apb_if vif;

function new(string name="",uvm_component parent);

function void build_phase(uvm_phase phase);

task run_phase(uvm_phase phase);

else if (vif.presetn && vif.pwrite)

else if (vif.presetn && !vif.pwrite)

function new(string name="",uvm_component parent);

function void build_phase(uvm_phase phase);

function void connect_phase(uvm_phase phase);

bit [31:0] array[32] = '{default:0};

bit [31:0] data_rd = 0;

function new(string name="",uvm_component parent);

function void build_phase(uvm_phase phase);

function void write(apb_seq_item tx);

else if (tx.op == writed)

else if (tx.op == readd)

`uvm_info("SCO", "SLV ERROR during READ OP", UVM_NONE);

function new(string name="",uvm_component parent);

function void build_phase(uvm_phase phase);

function void connect_phase(uvm_phase phase);

function new(string name="",uvm_component parent);

function void build_phase(uvm_phase phase);

function void end_of_elaboration_phase(uvm_phase phase);

task run_phase(uvm_phase phase);

apb_ram dut (.presetn(pif.presetn),

always #10 pif.pclk <= ~pif.pclk;

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