library ieee;

use ieee.std_logic_1164.all;

entity fsm_counter4 is
port (
clock : in std_logic;
resetn : in std_logic;
ce : in std_logic;
y : out std_logic;
q : out std_logic_vector(1 downto 0)
);
end fsm_counter4;

architecture Behavior of fsm_counter4 is

type State_type is (S0, S1, S2, S3);
signal s_present, s_next : State_type;
begin
process (ce, s_present)
begin
case s_present is
when S0 =>
if ce = '0' then
s_next <= S0;
else
s_next <= S1;
end if;
when S1 =>
if ce = '0' then
s_next <= S1;
else
s_next <= S2;
end if;
when S2 =>
if ce = '0' then
s_next <= S2;
else
s_next <= S3;
end if;
when S3 =>
if ce = '0' then
s_next <= S3;
else
s_next <= S0;
end if;
end case;
end process;

process (clock, resetn)

begin
if resetn = '1' then
s_present <= S0;
elsif rising_edge(clock) then
s_present <= s_next;
end if;
end process;

process (s_next)
begin
case s_next is
 when S0 => q <= "00";
when S1 => q <= "01";
when S2 => q <= "10";
when S3 => q <= "11";
end case;
if s_next = S3 then
y <= '1';
else
y <= '0';
end if;
end process;
end Behavior;