Dr.

Lamiaa Abdel-Hamid, Fall2021

Updated by Prof. Medhat Hussein, Fall 2023
BASIC 16-BIT PROCESSOR
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5.1 Basic Architecture
5.2 Instruction Format
5.3 Common Bus System
5.4 Computer Instructions
A. Instruction Cycle
B. Register Instructions
C. Memory Instructions
D. I/O Instructions
5.5 Summing Up
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5.1 BASIC ARCHITECTURE

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Memory is typically determined using two parameter:
 Number of memory locations >> 8
 Size of each memory location >> 4
Address:
0000 0: 000B
1100 1: 001B
Example: 8x4 1111 2: 010B
Databus= 4 bits 3: 011B
Address bus = 3 bits 4 :100B
5: 101B
6:110B
7: 111B 5
Data Bus: 16

Address Bus: 12

MEMORY
4096 x 16

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The processor memory stores _____________.

a) data
b) instructions
c) both

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 Reg.
Reg. Name Description #bits
Symbol
AC
DR
TR
IR
AR
PC
INPR
OUTR

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9
10
5.2 INSTRUCTION FORMAT

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 PC: stores the address (12 bits) of the next
instruction

 IR: stores the instruction (16 bits) currently

executed by the processor.

Note: Each instruction can be translated into one or more

microoperations e.g. ADD: (1) DR M[AR] (2) DR DR+ AC

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 Instructions are – 16 bits.

 There are three type of instructions:

 Memory
 Register
 Input/Output

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 IR

D7 D0…D6 : MEMORY

I=0 I=1 I=0 I=1

>> >> >> >>

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 IR

D7 D0…D6 : MEMORY

I=0 I=1 I=0 I=1

>> REGISTER >> I/O >> DIRECT >> INDIRECT
ADDRESSING ADDRESSING

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Direct addressing: address in IR is the EA.

Indirect Addressing: address in IR is the address of the EA.

Effective Address (EA): the actual address of the data

(operand)

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17
Given that the instructions below are stored in the
instruction register, indicated for each the effective address
and operand.

a) 0 AND 155 Memory

>> EA= 0X155 ..

0166 0x155
2011 0x156
b) 1 ADD 157 8020 0x157
>> EA=8020 0154 0x158
0406 0x159
..
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Assume a processor has a memory of 2MB. Given that its
IR has 32 bits, show the instruction format such that it
includes three parts: indirect bit – opcode- address.
SOLUTION
Address = 21 bits (bit0-bit20) Indirect bit is always included in the opcode so
the opcode is from 21-31 bits

Op code = 10 bits (bit21-bit31)

Indirect = 1 bit (bit 31)

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5.3 COMMON BUS SYSTEM

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 S2
S1 Bus
S0
Memory unit 7
4096 x 16
Address
Write Read
AR 1

LD INR CLR
PC 2

LD INR CLR

DR 3

LD INR CLR

E
ALU AC 4

LD INR CLR

INPR
IR 5
LD
TR 6

LD INR CLR
OUTR
Clock
LD
16-bit common bus
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Complete the following table Considering the basic
computer shown in the previous figure.
Source Destination
Microinstruction
Name Read S2 S1 S0 Name Write LD INR CLR
DR  TR
AR  PC
IR  M[AR]
AC  AC+1
M[AR]  DR
TR  0

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Complete the following table Considering the basic
computer shown in the previous figure.
Source Destination
Microinstruction
Name Read S2 S1 S0 Name Write LD INR CLR
DR  TR TR 0 1 1 0 DR 0 1 0 0
AR  PC PC 0 0 1 0 AR 0 1 0 0
IR  M[AR] M 1 1 1 1 IR 0 1 0 0
AC  AC+1 AC 0 0 0 0 AC 0 0 1 0
M[AR]  DR DR 0 0 1 1 M 1 0 0 0
TR  0 TR 0 0 0 0 TR 0 0 0 1

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5.4 COMPUTER INSTRUCTIONS
A. Instruction Cycle
B. Register Instructions
C. Memory Instructions
D. I/O Instructions

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 BASIC COMPUTER INSTRUCTIONS
Hex Code
Symbol I = 0 I=1 Description
AND 0xxx 8xxx AND memory word to AC
ADD 1xxx 9xxx Add memory word to AC
LDA 2xxx Axxx Load AC from memory
MEMORY STA 3xxx Bxxx Store content of AC into memory
BUN 4xxx Cxxx Branch unconditionally
BSA 5xxx Dxxx Branch and save return address
ISZ 6xxx Exxx Increment and skip if zero

CLA 7800 Clear AC

CLE 7400 Clear E
CMA 7200 Complement AC
CME 7100 Complement E
CIR 7080 Circulate right AC and E
CIL 7040 Circulate left AC and E
REGISTER INC 7020 Increment AC
SPA 7010 Skip next instr. if AC is positive
SNA 7008 Skip next instr. if AC is negative
SZA 7004 Skip next instr. if AC is zero
SZE 7002 Skip next instr. if E is zero
HLT 7001 Halt computer

INP F800 Input character to AC

OUT F400 Output character from AC
SKI F200 Skip on input flag
I/O SKO F100 Skip on output flag
ION F080 Interrupt on
IOF F040 Interrupt off

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1. Programs run sequentially:
 START: S1 //manually
 END: S 0 //HALT

2. For any instruction, the following steps take place:

a) Fetch
b) Decode
c) Read EA //in case of memory indirect
d) Execute

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a)Fetch:

T0: AR  PC

T1: IR  M[AR] , PC PC+1

b) Decode:

T2: D7 D6 … D0  Decode(IR[12:14]), I 
IR[15],

AR  IR[0:11]

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a)Memory:
I’D7’: Memory Direct
I D7’: Memory Indirect

b)Register
I’ D7

c) I/O:
I D7

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 We requires the fetch – decode – execute to be
performed in sequence.

 A timing control signal is used to assure proper sequential

operation.

 This timing signal is generated using a 4-bit counter

(sequence counter) and a decoder (T0,T1,T2….T15).

 The timing control starts counting with every new

instruction

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INSTRUCTION
DECODING

TIMING
SEQUENCE
SC >> Decoder
0000
0001
0010
0011
..
1111 30
 T0 T1 T2 T3 T4 T0
Clock

T0

T1

T2

T3

T4

D3

CLR
SC

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32
 r = I‘ D7T3 = (common to all register – reference instructions)

r: SC ← 0
CLA rB11: AC ← 0
CLE rB10: E←0
CMA rB9: AC ← AC’
CME rB8: E ← E’
CIR rB7: AC ← shr AC, AC(15) ← E, E ← AC(0)
CIL rB6: AC ← shl AC, AC(0) ← E, E ← AC(15)
INC rB5: AC ← AC + 1
SPA rB4: if (AC(15) = 0) then (PC ← PC+1)
SNA rB3: if (AC(15) = 1) then (PC ← PC+1)
SZA rB2: if (AC = 0) then (PC ← PC+1)
SZE rB1: if (E = 0) then (PC ← PC+1)
HLT rB0: S ← 0 (S is a start-stop flip-flop)

..
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PC= 300h E=0 AC=A840h DR=4444h M[111]= 0005 h
M[A23]=7111h M[A88]= FFFFh, For the basic computer, complete
the table after the given independent instructions are executed.
Instruction Description PC AR AC DR

7800 Clear AC 301h 300h 0 4444h

7020 Increment AC 301h 300h A841h 4444h
Skip next instr. if AC 301h 300h A840h 4444h
7004
is zero
Skip next instr. if AC 302h 300h A840h 4444h
7008 is negative

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 BASIC COMPUTER INSTRUCTIONS
Hex Code
Symbol I = 0 I=1 Description
AND 0xxx 8xxx AND memory word to AC
ADD 1xxx 9xxx Add memory word to AC
LDA 2xxx Axxx Load AC from memory
MEMORY STA 3xxx Bxxx Store content of AC into memory
BUN 4xxx Cxxx Branch unconditionally
BSA 5xxx Dxxx Branch and save return address
ISZ 6xxx Exxx Increment and skip if zero

CLA 7800 Clear AC

CLE 7400 Clear E
CMA 7200 Complement AC
CME 7100 Complement E
CIR 7080 Circulate right AC and E
CIL 7040 Circulate left AC and E
REGISTER INC 7020 Increment AC
SPA 7010 Skip next instr. if AC is positive
SNA 7008 Skip next instr. if AC is negative
SZA 7004 Skip next instr. if AC is zero
SZE 7002 Skip next instr. if E is zero
HLT 7001 Halt computer

INP F800 Input character to AC

OUT F400 Output character from AC
SKI F200 Skip on input flag
I/O SKO F100 Skip on output flag
ION F080 Interrupt on
IOF F040 Interrupt off

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 MEMORY INSTRUCTIONS
D0. AND // AC  AC ^ M[AR]
 T0: AR  PC

 T1: IR  M[AR] , PC PC+1

 T2: D7 D6 … D0  Decode(IR[12:14]), I  IR[15], AR  IR[0:11]

 𝑫𝑫𝟕𝟕 𝑰𝑰 𝑻𝑻𝑻𝑻: AR  M[AR]

 𝑫𝑫𝟕𝟕 𝑰𝑰� 𝑻𝑻𝑻𝑻: Nothing

 D0 T4: DR ← M[AR]

 D0 T5: AC ← AC ˄ DR, SC ← 0
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 MEMORY INSTRUCTIONS
D1. ADD // AC  AC + M[AR]
 D1 T4: DR ← M[AR]

 D1 T5: AC ← AC + DR, E=Cout, SC ← 0

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 MEMORY INSTRUCTIONS

D2. LDA // AC  M[AR]

 D2 T4: DR ← M[AR]

 D2 T5: AC ← DR, SC ← 0

D3. STA // M[AR]  AC

 D3 T4: M[AR] ← AC, SC ← 0

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 MEMORY INSTRUCTIONS

D6. ISZ //
 D6 T4: DR ← M[AR]

 D6 T5: DR ← DR + 1

 D6 T6: M[AR] ← DR, If (DR = 0) then (PC ← PC + 1), SC ← 0

 This instruction increments the word specified by

the effective address, and if the result is zero,
PC is incremented by one.
When PC is incremented by one,
the next instruction in the sequence is skipped.
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 MEMORY INSTRUCTIONS

D4. BUN // GO TO EA

 D4 T4: PC ← AR, SC ← 0

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 MEMORY INSTRUCTIONS

D5. BSA //BRANCH & SAVE RETURN ADDRESS

 D5 T4: M[AR] ← PC, AR ← AR+1

 D5 T5: PC ← AR, SC ← 0 MEORY

0x020 0 BSA 135
PC=0x021 NEXT INSTN
.. ..
AR= 0x135
0x136 SUBROTUNE
..
1 BUN 135
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 MEMORY INSTRUCTIONS

D5. BSA //BRANCH & SAVE RETURN ADDRESS

D5T4: M[AR]  PC , AR AR+1

D5T5: PC AR MEMORY
0x020 0 BSA 135
0x021 NEXT INSTN
.. ..
 After execution 0x135 0x21
PC= 0x136 EXECUTE
THE SUBROTUNE
..1 BUN 135
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..
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PC= 300h E=0 AC=A840h DR=4444h M[7111]= 0005 h
M[A23]=7111h M[A88]= FFFFh, For the basic computer, complete
the table after the given independent instructions are executed.
Instruction Description PC AR AC DR
Load AC from memory,
2A23 direct 301 A23 7111h 7111h

Branch 345 345 A840 4444

4345
unconditionally
Increment and skip if
6A88 zero 302 A88 A840 0000

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 BASIC COMPUTER INSTRUCTIONS
Hex Code
Symbol I = 0 I=1 Description
AND 0xxx 8xxx AND memory word to AC
ADD 1xxx 9xxx Add memory word to AC
LDA 2xxx Axxx Load AC from memory
MEMORY STA 3xxx Bxxx Store content of AC into memory
BUN 4xxx Cxxx Branch unconditionally
BSA 5xxx Dxxx Branch and save return address
ISZ 6xxx Exxx Increment and skip if zero

CLA 7800 Clear AC

CLE 7400 Clear E
CMA 7200 Complement AC
CME 7100 Complement E
CIR 7080 Circulate right AC and E
CIL 7040 Circulate left AC and E
REGISTER INC 7020 Increment AC
SPA 7010 Skip next instr. if AC is positive
SNA 7008 Skip next instr. if AC is negative
SZA 7004 Skip next instr. if AC is zero
SZE 7002 Skip next instr. if E is zero
HLT 7001 Halt computer

INP F800 Input character to AC

OUT F400 Output character from AC
SKI F200 Skip on input flag
I/O SKO F100 Skip on output flag
ION F080 Interrupt on
IOF F040 Interrupt off

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Considering only the indicated THREE instructions of the basic
computer, design the control circuits to generate the four control
signals: INR (PC) - LD (AC) - CLR (AC) - Read (Memory)

Direct AND (I=0), Indirect ADD (I=1), CLA

Solution: next page

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INC(PC) = R’ T1
LD(AC) = D0 T5 + D1 T5
CLR(AC) = D7 I’ T3 B11
READ(MEM)=R’ T1 + D0 T4 + D1 T4
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Any interface between the PC and an I/O device must be
through the AC.

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 Polling: continuously asking the
students whether they have any
question.
 wastes a lot of time
>>human: 10 char/sec
>>processor: fclk 5kHz == 5000inst./sec

 Interrupts: handling a student

question only when they raise their
hand.
 better use of time
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50
INPUT :
 FGI=1 >> input character is ready in the INPR
 FGI is cleared>> when AC(0-7)  INPR

OUTPUT :
 FGO=1>> character ready in AC to be transferred to OUTR
 FGO is cleared >> when OUTR  AC(0-7)

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 Instruction cycle =0 Interrupt cycle
R =1

Fetch and decode Store return address in

instructions location 0
M[0] ← PC

=0
Execute IEN
instructions Branch to location 1
=1
PC ← 1
=1
FGI
=0

=1 IEN ← 0
FGO R←0
=0
R←1

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Interrupt Cycle:

T0’T1’T2’ (IEN) (FGI + FGO): R←1

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Assume an interrupt occurs during the execution of the
instruction in address 0x255 (i.e. PC= ?? ).
1) A hardware BSA 0 operation is performed (PC = ?? )
2) Typically, address 0x001 has a BUN inst. to the I/O program.
3) Last line in I/O program is a indirect BUN to 0

1- M[0]  PC
2- PC=1
3. IEN = 0, R=0

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Interrupt Cycle:

T0’T1’T2’ (IEN) (FGI + FGO): R←1

RT0: AR ← 0, TR ← PC
RT1: M[AR] ← TR, PC ← 0
RT2: PC ← PC + 1, IEN ← 0, SC ← 0
1- M[0]  PC
2- PC=1
3. IEN = 0, R=0
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 S2
S1 Bus
S0
Memory unit 7
4096 x 16
Address
Write Read
AR 1

LD INR CLR
PC 2

LD INR CLR

DR 3

LD INR CLR

E
ALU AC 4

LD INR CLR

INPR
IR 5
LD
TR 6

LD INR CLR
OUTR
Clock
LD
16-bit common bus
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5.5 SUMMING UP

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 S2
S1 Bus
S0
Memory unit 7
4096 x 16
Address
Write Read
AR 1

LD INR CLR
PC 2

LD INR CLR

DR 3

LD INR CLR

E
ALU AC 4

LD INR CLR

INPR
IR 5
LD
TR 6

LD INR CLR
OUTR
Cloc
LD k
16-bit common bus

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 start
SC ← 0, IEN ← 0, R ← 0

(Instruction Cycle) =0 R =1 (Interrupt Cycle)

R’T0 RT0
AR ← PC AR ← 0, TR ← PC
R’T1 RT1
IR ← M[AR], PC ← PC + 1 M[AR] ← TR, PC ← 0
R’T2 RT2
AR ← IR(0~11), I ← IR(15) PC ← PC + 1, IEN ← 0
D0...D7 ← Decode IR(12 ~ 14) R ← 0, SC ← 0

=1(Register or I/O) D7 =0(Memory Ref)

=1 (I/O) =0 (Register) =1(Indir) =0(Dir)

I I

D7IT3 D7I’T3 D7’IT3 D7’I’T3

Execute Execute AR <- M[AR] Idle
I/O RR
Instruction Instruction
Execute MR
D7’T4
Instruction

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