CSARCH1 – Design Exercise #01

Group 72
Members: Section: S12
Biacora, Luis
Valenzuela, Shanley

I. Truth Tables
To efficiently produce an accurate truth table,
we first listed down all the numbers that will
have a bit value of 1 in the 7-segment display.

Figure 1.1

Then, we created a 24 - truth table for the input

and assigned each row to its equivalent decimal
number. The 2-digit numbers 10 and 11 are
shaded to note that they are invalid inputs.

Figure 1.2
For each cell in the output, we used an IF-
COUNTIF formula checking if the number in
column A (Figure 1.2) exists in the set of
numbers that outputs 1 in each segment (Figure
1.1). The sample formula is given below:

The resulting table of outputs is shown in Figure

1.3.

Some rows are shaded to easily identify which

minterms (blue) and maxterms (gray) are
common to all outputs.

Figure 1.3
II. Boolean Expressions
We assigned the minterm and the maxterm for each row of the truth table and did trial and error in
deciding which to use. Eventually, we settled with using minterms because redundant terms are more
easily spotted and it occupies less space due to less number of plus signs. Using minterms also became
useful later on when we resorted to using Karnaugh Maps.

Figure 2.1

Initially, we tried simplifying using the laws of Boolean algebra, but the process took too long and is
prone to a lot of errors so we resorted to other methods such as the Karnaugh Maps. We used an online
tool (www.boolean-algebra.com) to easily and correctly generate the mappings.
Output variable K-map Boolean Expression

a WY' + W'X' + W'Z + XYZ'

Figure 2.2

b W’Y + WY’ + X’Z’ + XY’

Figure 2.3

c Y’Z + XZ’ + W’Z + W’Y’ + WYZ’

Figure 2.4

d W’Y + WY’ + X’Y’ + XYZ’

Figure 2.5

e W’X’ + X’Y’

Figure 2.6
 f W’X’Y’ + WY’Z + W’YZ + WYZ’

Figure 2.7

g WY’ + W’Y + WZ’ + W’X’Z

Figure 2.8

We then counted the number of gates that each expression will use. Upon listing down all unique terms,
we subtracted the redundant terms and arrived at 24 gates.

Figure 2.9

By using the distributive law and De Morgan’s Theorem, we were able to further reduce the gates into
22.

Figure 2.10
 III. Logic Circuit

Figure 3.1 – Logic Circuit

Figure 3.1 shows our final circuit which we made and simulated on Circuitverse.
Figure 3.2 and 3.3 below are snap shots of our test cases which we ran on circuitverse.

Figure 3.2 – Circuitverse Testbench

 Figure 3.3 – Testbench details

IV. Running in Iverilog

We exported the Verilog code from Circuitverse and ran it on iverilog. Figures 4.1 and 4.2 shows our
Verilog codes for the main module and the testbench. Figure 4.3 shows the iverilog result when run on
command prompt.

Figure 4.1 - Main module

Figure 4.2 - Testbench module

Figure 4.3 - Results