1a )Demonstrate the nonassociativity of the NOR gate

NOR Gate Non-associativity Explanation:

Consider three inputs: x, y, and z. We'll demonstrate that the NOR gate doesn't follow the associative property.

1. (x ↓ y) ↓ z:

- First, we NOR x and y.

- Then, we NOR the result with z.

2. x ↓ (y ↓ z):

- First, we NOR y and z.

- Then, we NOR the result with x.

Let's compute both:

1. (x ↓ y) ↓ z:

- x NOR y gives us (x' * y').

- Then, NOR with z gives us ((x' * y')' + z).

2. x ↓ (y ↓ z):

- y NOR z gives us (y' * z').

- Then, NOR with x gives us ((y' * z')' + x).

Comparing the results:

- (x ↓ y) ↓ z gives ((x' * y')' + z).

- x ↓ (y ↓ z) gives ((y' * z')' + x).

These results are not always the same. Therefore, the NOR gate doesn't follow the associative property
because changing the order of operations affects the outcome.

1b) Design a car safety alarm circuit diagram. The system considers four inputs: door (D), key (K), seat
pressure (P) and seat belt (B). The input is considered HIGH (1) if the door is closed, the key is in, the driver is
on the seat, or the seat belt is fastened. The alarm (A) should sound with two conditions as stated below: The
door is not closed, and the key is in. The door is closed, the key is in the driver's seat, and the seat belt is not
closed.

(a) Construct a truth table for the system based on input arrangement D, K, P, B with A as an output

(b)Design a Karnaugh map to verify the simplified expression

(c) Draw the simplified circuit using NOR gates only

1c) With an example explain the working of Test Bench in Verilog.

A testbench is a simulation environment used in hardware description languages like Verilog or VHDL to verify
the functionality of a digital design by applying stimulus to the inputs and observing the responses at the
outputs.

Example: Suppose we want to verify the functionality of the AND gate for all possible input combinations. The
testbench applies different input combinations (0,0), (0,1), (1,0), and (1,1) sequentially to the AND gate and
observes the output y. After applying all the test cases, it terminates the simulation. This example demonstrates
how the testbench interacts with the Verilog module to verify its functionality under different scenarios.
VERILOG CODE:

module and_gate(

input wire a,

input wire b,

output wire y );

assign y = a & b; // Logic for AND gate

endmodule

-This Verilog module defines an AND gate, which takes two input wires a and b, and produces one output wire
y.

-The logic for the AND gate is implemented using the assign statement, where y is assigned the result of the
logical AND operation between inputs a and b.

TestBench:-

module and_gate_tb;

reg a, b;

wire y;

and_gate dut (

.a(a),

.b(b),

.y(y)

);

initial begin

a = 0; b = 0; #10;

a = 0; b = 1; #10;

a = 1; b = 0; #10;

a = 1; b = 1; #10;

$finish;

end

endmodule

Explanation: This Verilog module serves as a testbench for the AND gate module.

It defines input a and b as reg and output y as wire.

The AND gate module and_gate is instantiated within the testbench, connecting its inputs and output.

Within the initial block, stimulus is applied to inputs a and b for different test cases.

Each test case waits for a short delay (#10) before moving to the next one.

After all test cases are executed, the simulation is terminated using $finish.
2a) Demonstrate the positive and negative logic signal

- Signals in binary digital circuits can have two values: high (H) and low (L).

- These values represent logic 1 and logic 0, respectively.

- In positive logic, H represents logic 1 and L represents logic 0.

- In negative logic, L represents logic 1 and H represents logic 0.

- Users can choose whether H or L represents logic 1 based on their preference.

- This choice defines the system as positive or negative logic.

- Gates operate based on their truth tables, which specify behavior for H and L.

- Symbols for gates reflect their behavior and can change based on logic polarity.

- Converting between positive and negative logic involves swapping 1's and 0's.

- This conversion results in taking the dual of the function.

- When switching between positive and negative logic, AND operations become OR operations, and vice versa.

- The symbols for positive logic AND gates look similar to positive logic OR gates.

- In negative logic, the truth table entries are flipped compared to positive logic.

- A single gate can act as either a positive logic AND gate or a negative logic OR gate.

- Graphic symbols for gates may include polarity indicators for negative logic.

- Polarity indicators clarify whether a gate operates in positive or negative logic.

2b) A digital system is to be designed in which the month of the year is given as I/P in four-bit form. The month
of January is represented as '0000', February as "0001" and so on. The output of the system should correspond to
the input of the month containing 31 days, or otherwise, it is '0'. Consider the excess number in the I/P beyond
1011' as don't care condition:(i) Write truth table, SOP Em and POSIIM form(ii) Simplify for SOP using K-
map(iii) Realize using basic gates

(i) Truth Table, SOP, and POS Forms:

Truth Table:

| Month (Input) | Output |

| 0000 (January) | 0 |

| 0001 (February) | 1 |

| 0010 (March) | 0 |

| 0011 (April) | 0 |

| 0100 (May) | 0 |

| 0101 (June) | 0 |

| 0110 (July) | 0 |

| 0111 (August) | 0 |

| 1000 (September)| 0 |

| 1001 (October) | 0 |
| 1010 (November) | 0 |

| 1011 (December) | 1 |

| 1100 (Don't care) | X |

| 1101 (Don't care) | X |

| 1110 (Don't care) | X |

| 1111 (Don't care) | X |

SOP Expression:

Output = ~A & ~B & ~C & D

POSIIM Expression:

Output = (A + B + C + ~D)

(ii) Simplification for SOP using K-map:

\ CD\AB | 00 | 01 | 11 | 10 |

--------+----+----+----+----+

00 | 0 | 0 | 0 | 0 |

--------+----+----+----+----+

01 | 1 | 0 | 0 | 0 |

--------+----+----+----+----+

11 | 0 | 0 | 0 | 0 |

--------+----+----+----+----+

10 | 0 | 0 | 0 | 1 |

Simplified SOP expression: Output = ~A & ~B & D

(iii) Realization using Basic Gates:

You can implement the simplified expression (~A & ~B & D) using AND, NOT gates as follows:

- A = Input bit representing January

- B = Input bit representing February

- C = Input bit representing March

- D = Input bit representing December

Output = ~(A + B + C) * D
2c) What is User-Defined Primitives in Verilog? What are the general rules for UDP? Explain with an example
HDL for user defined primitive. Draw the Schematic for the Circuit with UDP_02467

- Verilog logic gates like AND, OR, etc., are predefined by the system and are known as system primitives.

- User-defined primitives (UDPs) can be created by defining them in tabular form, often using a truth table.

- UDPs are declared using the keyword pair `primitive ... endprimitive`, unlike modules in Verilog which use
`module ... endmodule`.

- Example 3.4 in Verilog defines a UDP using a truth table.

- General rules for defining UDPs include:

1. Declare the UDP using the keyword `primitive`, followed by a name and port list.

2. The output must be listed first in the port list and declared using the keyword `output`.

3. Any number of inputs can be specified, listed in the input declaration in the order they are given values in
the truth table.

4. Enclose the truth table within the keywords `table` and `endtable`.

5. List the values of inputs in order, followed by a colon (`:`).

6. The output value is always the last entry in a row, followed by a semicolon (`;`).

Verilog Example (User-Defined Primitive)

// Verilog model: User-defined Primitive

primitive UDP_02467 (D, A, B, C);

output D; // Declare output port D

input A, B, C; // Declare input ports A, B, C

// Truth table for D = f (A, B, C) = ∑(0, 2, 4, 6, 7);

table

// A B C : D // Column header comment

0 0 0 : 1; // Output D is 1 when inputs are 000

0 0 1 : 0; // Output D is 0 when inputs are 001

0 1 0 : 1; // Output D is 1 when inputs are 010

0 1 1 : 0; // Output D is 0 when inputs are 011

1 0 0 : 1; // Output D is 1 when inputs are 100

1 0 1 : 0; // Output D is 0 when inputs are 101

1 1 0 : 1; // Output D is 1 when inputs are 110

1 1 1 : 1; // Output D is 1 when inputs are 111

endtable

endprimitive
// Instantiate primitive

// Verilog model: Circuit instantiation of Circuit_UDP_02467

module Circuit_with_UDP_02467 (e, f, a, b, c, d);

output e, f; // Declare output ports e, f

input a, b, c, d; // Declare input ports a, b, c, d

UDP_02467 (e, a, b, c); // Instantiate UDP_02467 with inputs a, b, c and output e

and (f, e, d); // Perform AND operation between e, d and assign to output f

endmodule

Note that the variables listed at the top of the table are part of a commentand are shown only for clarity.

The system recognizes the variables by the order in which they are listed in the input declaration.

A user-defined primitive can be instantiated in the construction of other modules (digital circuits), just as the
system primitives are used. For example, the declaration Circuit_with_UDP_02467(E,F,A,B,C,D); will produce a
circuit that implements the hardware shown in Fig
3a) Differentiate Latches and Flip-Flop
3b) Explain the working of Four-bit adders using 4-full Adders.

Four-bit adders using 4-full Adders (Binary Adder)

-A binary adder computes the sum of two binary numbers.

-It's built using full adders connected in a chain.

-Each full adder's output carry is connected to the input carry of the next.

-For n-bit numbers, it requires n full adders.

-Each full adder adds one bit of the numbers, and carries propagate through the adder chain.

-An n-bit adder needs n full adders, with carries cascaded.

Binary Addition Example:

A = 1011

B = 0011

Sum S = 1110

Subscript i: 3 2 1 0

Input carry: 0 1 1 0 Ci

Augend (A): 1 0 1 1 Ai

Addend (B): 0 0 1 1 Bi

Sum (S): 1 1 1 0 Si

Output carry: 0 0 1 1 Ci+1

We add binary numbers A and B to get the sum S.

Starting from the right (least significant) bit, we add each pair of bits along with the input carry.

The input carry at the least significant bit is 0.

The output carry from each addition becomes the input carry for the next addition.

The sum bits are generated from right to left.

All the carries must be generated for the correct sum to appear.

3 c)Implement Y (A, B, C, D) = ∑m (0, 1, 6, 7, 8, 9, 10, 11, 12, 14) using 16- to-1 multiplexer and 8-to-1
multiplexer.

4a) Explain different modeling styles used to write the code in VERILOG with an example

Verilog and VHDL support three common styles of modeling combinational circuits:
1. Structural Modeling (Gate-level Modelling)
2. Dataflow Modeling
3. Behavioral Modeling:

1. Structural Modeling:
-Gate-level modeling creates complex circuits by connecting basic logic circuits.
-It describes circuits by specifying the gates used and how they're connected
- Example:

module AND_Structural(output y, input a, input b);

and gate(y, a, b);
endmodule

2. Dataflow Modeling:
-Dataflow modeling represents circuit functionality using operators and assignment statements.
-It focuses on describing how inputs are processed to produce outputs.
- Example:

module AND_Dataflow(output y, input a, input b);

assign y = a & b;
endmodule

3. Behavioral Modeling:
-Behavioral modeling creates an abstract model of a circuit using procedural statements.
-It describes circuit behavior without detailing its internal structure.
- Example:

module AND_Behavioral(output y, input a, input b);

always @(*) begin
y = a & b;
end
endmodule

4b) Design a BCD-to-excess-3 code converter.

- BCD and excess-3 codes use four bits for a decimal digit representation.

- A code converter needs four input (A, B, C, D) and four output (W, X, Y, Z) variables.

- The truth table for the converter is derived from the codes, showing input-output mappings.

- Despite 16 possible combinations for four variables, the truth table lists only 10 relevant combinations.

- Unlisted combinations are considered don't-care values, as they have no meaning in BCD.

- Output variables can be assigned 1 or 0 for simplicity, based on circuit requirements.

TRUTH TABLE
4c) Define decoder. Describe the working principle of a 3:8 decoder. Draw the logic diagram of the 3:8 decoder
with enabled input. Realize the following Boolean expressions using a 3:8 decoder and multi-input OR
gates:F1(A, B, C) = ∑ m(1, 3, 7) F2(A, B, C) = ∑m(2, 3, 5)

A decoder is a combinational circuit that converts binary information from n input lines to maximum of 2^n
unique output lines

5a) Write one address, two address, and three address instructions to carry out C← [A] + [B].

The operation of adding 2 numbers is a fundamental capability in any computer. The statement
C=A+B
In a high level language program is a command to the computer to add the current values of the
2 variables called A & B and to assign the sum to third variable, C.
Same in high level language statement requires the action to takes place in the computer
C ← [A] + [B]
Instruction formats with examples:

5b) Explain the basic operation concepts of the computer with a neat diagram.

The activity in a computer is governedby instructions. A typical instruction may be

 ADD LOCA, R0
• Add the operand at memory location LOCA to the operand in a register R0 in the processor.
• Place the sum into register R0.
• The original contents of LOCA are preserved.
• The original contents of R0 is overwritten.
• The following are the steps to execute the instruction:

Step 1: Fetch the instruction from main-memory into the processor.

Step 2: Fetch the operand at location LOCA from main-memory into the processor.
Step 3: Add the memory operand (i.e. fetched contents of LOCA) to the contents of register
R0.
Step 4: Store the result (sum) in R0.

Processor Components:

a) Instruction Register (IR): Stores the currently executed instruction.

b) Program Counter (PC): Holds the memory address of the next instruction.

c) General-Purpose Registers: Used for storing temporary data.

d) Memory Address Register (MAR): Holds the address of the memory location to be accessed.

e) Memory Data Register (MDR): Stores data for read or write operations.
f) Arithmetic Logic Unit (ALU): Executes arithmetic and logical operations.

Memory Communication Process:

1. Programs are stored in memory , programs consists of set of instructions.

2. Program execution begins with the PC pointing to the first instruction.

3. The content of the PC is transferred to the MAR, initiating a read operation to memory.

4. The addressed instruction (word) is read from memory into the MDR.

5. The content of the MDR is then transferred to the IR for decoding and execution.

6. If the instruction involves an ALU operation, operands are retrieved from memory.

7. Operand addresses are sent to the MAR, initiating read operations by the MDR.

8. The operands are transferred from the MDR to the ALU.

9. The ALU performs the specified operation.

10. If the result needs to be stored in memory, it is sent to the MDR.

11. The address where the result is to be stored is sent to the MAR, initiating a write operation by the MDR.

12. During instruction execution, the PC's contents are incremented, pointing to the next instruction.

13. This process allows for the fetching of the next instruction once the current one completes.

14. Overall, this system ensures accurate and efficient execution of instructions by coordinating the activities
between the processor and memory.

5C) Explain a) Processor Clock, b) Basic performance equation, c) Clock rate d) Performance measurement

A) Processor Clock :-

- The processor clock is a timing signal controlling processor and system components.

- It divides tasks into clock cycles, each representing a fixed unit of time.

- Clock rate, measured in hertz, determines processor speed.

- Higher clock rate implies faster processing.

- Modern processors have rates ranging from millions to billions of cycles per second.

- Clock rate formula: R = 1 / P, where R is clock rate and P is length of one cycle.

- A higher clock rate means shorter cycles and faster processing.

- Example: A 3.2 GHz processor performs over 3 billion cycles per second, indicating high speed.

b) Basic Performance Equation:-

- The basic performance equation, T = N × S / R, governs program execution time.

- T represents the processor time for program execution.

- N is the actual number of instruction executions.

- S denotes the average number of basic steps per instruction.

- R signifies the clock rate (cycles per second).

- To improve performance, designers aim to minimize T by reducing N and S, and increasing R.

- Decrease N: Compile into fewer instructions.

- Decrease S: Use instructions with fewer steps.

- Increase R: Use a higher frequency clock.

- Changes in one parameter may affect others.

c) Clock Rate:-

- Clock rate, measured in hertz (Hz), determines processor speed.

- Higher clock rate means faster processing.

- Improved integrated-circuit (IC) technology enables faster logic circuits.

- Faster logic circuits reduce time for each clock cycle.

- Reducing workload per cycle can also cut clock period.

- Maintaining instruction complexity may require more cycles despite shorter clock period.

D) performance measurement

Performance Measurement:

- Performance measurement evaluates the efficiency and effectiveness of a computer system.

- Metrics include execution time, throughput, response time, and resource utilization.

- Benchmarks and profiling tools assess system performance under different workloads.

- Identifying bottlenecks and optimizing configurations enhance system performance.

- The SPEC (System Performance Evaluation Corporation) selects and publishes benchmarks.

- Benchmarks cover various applications from gaming to scientific computing.

- Programs are compiled and run on real computers for performance evaluation.

- The SPEC rating compares the performance of a computer under test to a reference computer.

- For example, a SPEC rating of 50 indicates the computer is 50 times faster than the reference.

6a) Write ALP of adding a list of n numbers using indirect addressing mode

- In figure (a), Add instruction uses R1's value as the operand's address.

- Memory read operation retrieves operand from location B.

- Operand is added to R0.

- Figure (b) shows indirect addressing via memory location.

- Processor reads A's contents first.

- Then another read operation using B's value as address retrieves the operand.

- Program Explanation:

1. R2 serves as a pointer to list numbers.

2. Initialization: Load n from N, place NUM1 address in R2, clear R0.

3. Loop starts unspecified block at LOOP.

4. First iteration: Add (R2) to R0.

5. Second Add instruction increments R2 by 4 for next iteration.

6b) What is an addressing mode? Explain the different addressing modes. With an example for each

The different ways in which the location of an operand is specified in an instruction are referred
to as addressing modes.”

EA=Effective Address , Value= a signed Number & LOC= Memory Location

1. Immediate Addressing Mode:

- In immediate mode, the operand value is directly specified within the instruction.

- Example: `Move #10, R1` (Load immediate value 10 into register R1).

2. Register Addressing Mode:

 - Operand data is stored in a register specified by its name or address in the instruction.

- Example: `Load R2, R3` (Load contents of register R2 into register R3).

3. Absolute (Direct) Addressing Mode:

- The operand's memory address is directly specified in the instruction.

- Example: `Store R1, LOC` (Store contents of register R1 at memory location LOC).

4. Indirect Addressing Mode:

- The instruction provides the address of a register or memory location, which contains the actual operand
address.

- Example: `Add (R2), R3` (Add contents of memory address stored in R2 to R3).

5. Index Addressing Mode:

- An offset value (X) is added to the contents of a register to calculate the effective address.

- Example: `Add 20(R5), R2` (Add value at memory address (R5 + 20) to R2).

6. Base with Index Addressing Mode:

- Combines two registers to form the effective address.

- Example: `Subtract (R1, R2), R3` (Subtract contents of memory address formed by R1 and R2 from R3).

7. Base with Index and Offset Addressing Mode:

- Uses two registers and an additional offset value to calculate the effective address.

- Example: `Jump 100(R1, R2)` (Jump to the memory address 100 plus the sum of contents of R1 and R2).

8. Relative Addressing Mode:

- Calculates the operand's address relative to the program counter (PC).

- Example: `Branch > 0 50(PC)` (Branch to the memory address 50 locations ahead of the current PC).

9. Autoincrement Addressing Mode:

- Retrieves the operand from the memory location pointed to by a register and increments the register
afterward.

- Example: `Load (R2)+, R3` (Load contents of memory location pointed to by R2 into R3 and increment R2).

10. Autodecrement Addressing Mode:

- Retrieves the operand from the memory location pointed to by a register and decrements the register
afterward.
 - Example: `Store -(R1), R2` (Store contents of R2 into the memory location pointed to by R1 and decrement
R1).

6c) Explain the following: (i) Byte addressability (ii) Big-endian assignment (i) Little-endian assignment.

(i) Byte Addressability:

- Byte-addressable memory allows each byte in memory to have a unique address.

- Successive addresses correspond to successive byte locations in memory.

- For example, if the word-length is 32 bits, each word consists of 4 bytes, and successive words are located at
addresses 0, 4, 8, etc.

(ii) Big-Endian Assignment:

- In Big-Endian assignment, the most significant byte (MSB) of a multi-byte data type is stored at the lowest
memory address.

- Subsequent bytes are stored at higher memory addresses in ascending order of significance.

- For example, considering a 32-bit integer (e.g., 0x12345678), when stored in Big-Endian:

Memory Address: Value:

1000: 12

1001: 34

1002: 56

1003: 78

(iii) Little-Endian Assignment:

- In Little-Endian assignment, the least significant byte (LSB) of a multi-byte data type is stored at the lowest
memory address.

- Subsequent bytes are stored at higher memory addresses in descending order of significance.

- For example, considering the same 32-bit integer (0x12345678), when stored in Little-Endian:

Memory Address: Value:

1000: 78

1001: 56

1002: 34

1003: 12
7a) Draw a neat block diagram of memory hierarchy in a computer system. Discuss the variation of size, speed
and cost per bit in the hierarchy

1. Disk Storage:

- Size: Disk devices offer the largest storage capacity among the memory hierarchy.
 - Speed: They provide a cost-effective solution for storing large volumes of data but are slower in access
speed compared to semiconductor memory.

- Cost per Bit: Disk storage provides the lowest cost per bit of storage due to its large capacity, but it has the
slowest access speed.

2. Main Memory:

- Size: Main memory, implemented using dynamic memory components, offers a significant storage capacity
but is smaller than disk storage.

- Speed: It serves as a bridge between cache memory and disk storage, providing more storage capacity at a
lower cost per bit compared to cache memory.

- Cost per Bit: Main memory has a moderate cost per bit, offering a balance between storage capacity and
access speed.

3. Secondary Cache (L2 Cache):

- Size: Secondary cache, or L2 cache, is larger than primary cache and offers a larger storage capacity
compared to primary cache.

- Speed: It provides faster access than main memory but slower than primary cache, offering a balance
between speed and size.

- Cost per Bit: The cost per bit of secondary cache is higher than main memory but lower than primary cache,
reflecting its intermediate position in terms of speed and size.

4. Primary Cache (L1 Cache):

- Size: Primary cache, also known as L1 cache, is smaller in size but faster in access speed compared to
secondary cache.

- Speed: It is located on the processor chip and offers faster access to frequently accessed instructions and
data.

- Cost per Bit: Primary cache has the highest cost per bit among the memory hierarchy due to its smaller size
and faster access speed.

5. Registers:

- Size: Registers provide the smallest storage capacity but offer the fastest access speed among the memory
hierarchy.

- Speed: They are located directly on the processor chip and are used for temporary storage of frequently
accessed data and instructions.

- Cost per Bit: Registers have the highest cost per bit due to their limited storage capacity and extremely fast
access speed.
7b) What is DMA Bus arbitration? Explain different bus arbitration techniques.

Bus Arbitration:-

❖ The device that is allowed to initiate data transfers on the bus at any given time is called the bus
master. When the current master relinquishes control of the bus, another device can acquire this
status.
❖ Bus arbitration is the process by which the next device to become the bus master is selected and
bus mastership is transferred to it.
❖ The selection of the bus master must take into account the needs of various devices by
establishing a priority system for gaining access to the bus.
❖ There are two approaches to bus arbitration: centralized and distributed. In centralized
arbitration, a single bus arbiter performs the required arbitration.
❖ In distributed arbitration, all devices participate in the selection of the next bus master.

Centralized Arbitration:-

❖ The bus arbiter may be the processor or a separate unit connected to the bus. A basic
arrangement in which the processor contains the bus arbitration circuitry.
❖ In this case, the processor is normally the bus master unless it grants bus mastership to one of the
DMA controllers.
❖ A DMA controller indicates that it needs to become the bus master by activating the Bus-
Request line, BR.
❖ The signal on the Bus-Request line is the logical OR of the bus requests from all the devices
connected to it. When Bus-Request is activated, the processor activates the Bus-Grant signal,
BG1, indicating to the DMA controllers that they may use the bus when it becomes free.
❖ This signal is connected to all DMA controllers using a daisy-chain arrangement. Thus, if DMA
controller 1 is requesting the bus, it blocks the propagation of the grant signal to other devices.
❖ Otherwise, it passes the grant downstream by asserting BG2. The current bus master
indicates to all device that it is using the bus by activating another open-controller line called
Bus-Busy, BBSY.
❖ Hence, after receiving the Bus-Grant signal, a DMA controller waits for Bus-Busy to become
inactive, then assumes mastership of the bus.

Distributed Arbitration:-

❖ Distributed arbitration means that all devices waiting to use the bus have equal
responsibility in carrying out the arbitration process, without using a central arbiter.
❖ A simple method for distributed arbitration is illustrated in figure 6.
❖ Each device on the bus assigned a 4-bit identification number. When one or more
 devices request the bus, they assert the
❖ Start Arbitration signal and place their 4-bit ID numbers on four-open-collector lines, ARBO
through ARB3.
❖ A winner is selected as a result of the interaction among the signals transmitted over those
liens by all contenders.
❖ The net outcome is that the code on the four lines represents the request that has the
highest ID number.

8a) With neat sketches, explain various methods for handling multiple interrupt requests raised by multiple
devices.

1. Polling:

- Processor sequentially checks each device's status register to identify the one requesting an interrupt.

- First device encountered with its interrupt request bit set is serviced.

- Easy to implement but may result in wasted processing time if many devices are polled unnecessarily.

2. Vectored Interrupts:

- Devices directly identify themselves to the processor by sending a special code over the bus when requesting
an interrupt.

- Processor immediately executes the corresponding interrupt-service routine based on the device's
identification.
 - Reduces polling time but requires additional hardware support for interrupt vectoring.

3. Interrupt Nesting:

- Interrupts are disabled during the execution of an interrupt-service routine to prevent multiple interruptions.

- Ensures one interrupt is serviced at a time, but may lead to delays for critical tasks.

4. Priority-Based Handling:

- Devices organized into priority levels, with the processor accepting interrupts only from devices with higher
priorities.

- Ensures critical interrupts are addressed promptly while lower-priority interrupts are queued.

- Priority level dynamically controlled by the processor.

5. Daisy Chaining:

- Devices connected in a chain-like fashion, sharing a common interrupt line.

- Processor services interrupts based on device position in the chain, with closest device having highest
priority.

- Reduces wire complexity but may not prioritize interrupts based on device importance.

6. Simultaneous Requests Handling:

- Processor selects highest priority interrupt request when multiple devices raise simultaneous interrupts.

- Priority determined by polling order, vectored interrupts, or daisy chaining.

- Ensures critical interrupts are addressed promptly while providing fair handling for multiple devices.
8b) What is cache memory? Explain the different mapping functions used in cache memory

Cache memory is a high-speed, volatile memory used to store frequently accessed data and instructions,
reducing the time it takes for the CPU to retrieve information from the slower main memory.

Mapping functions

There are 3 techniques to map main memory blocks into cache memory –

1. Direct mapped cache

2. Associative Mapping

3. Set-Associative Mapping

1) DIRECT MAPPING

• The simplest way to determine cache locations in which to store memory blocks

is the direct mapping technique as shown in the figure.

• If there are 128 blocks in a cache, the block-j of the main-memory maps onto block-j modulo 128 of the cache
. When the memory-blocks 0, 128, & 256 are loaded into cache, the block is stored in cache-block 0. Similarly,
memory blocks 1, 129, 257 are stored in cache-block 1.(eg:1mod 128=1, 129 mod 128=1)

• The contention may arise

1) Even when the cache is full.

2) But more than one memory-block is mapped onto a given cache-block position.

• The contention is resolved by allowing the new blocks to overwrite the currently resident-block.

Memory-address determines placement of block in the cache.

The main memory block is loaded into cache block by means of memory address. The main memory

address consists of 3 fields as shown in the figure.

• Each block consists of 16 words. Hence least significant 4 bits are used to select one of the 16 words.

• The 7bits of memory address are used to specify the position of the cache block, location. The most

significant 5 bits of the memory address are stored in the tag bits. The tag bits are used to map one of

2^5 = 32 blocks into cache block location (tag bit has value 0-31).

• The higher order 5 bits of memory address are compared with the tag bits associated with cache

location. If they match, then the desired word is in that block of the cache.

• If there is no match, then the block containing the required word must first be read from the main memory.

2) Associative Mapping:

• It is also called as associative mapped cache. It is much more flexible.

• In this technique main memory block can be placed into any cache block position.

• In this case , 12 tag bits are required to identify a memory block when it is resident of the cache memory.

• The Associative Mapping technique is illustrated as shown in the fig.

• In this technique 12 bits of address generated by the processor are compared with the tag bits of each block
of the cache to see if the desired block is present. This is called as associative mapping technique.
 3) Set Associative Mapping:

• It is the combination of direct and associative mapping techniques.

• The blocks of cache are divided into several groups. Such a groups are called as sets.

• Each set consists of number of cache blocks. A memory block is loaded into one of the cache sets.

• The main memory address consists of three fields, as shown in the figure.

• The lower 4 bits of memory address are used to select a word from a 16 words.

• A cache consists of 64 sets as shown in the figure. Hence 6 bit set field is used to select a cache set from 64
sets.

• As there are 64 sets, the memory is divided into groups containing 64 blocks, where each group is given a tag
number.

• The most significant 6 bits of memory address is compared with the tag fields of each set to determine
whether memory block is available or not.

• The following figure clearly describes the working principle of Set Associative Mapping technique.
9a) Explain the single-bus organization of computers and fundamental concepts with a neat diagram.

Single bus organization of computers:-

- ALU and registers are connected via a Single Common Bus.

- External memory-bus data and address lines connect to the internal processor-bus via MDR (Memory Data
Register) and MAR (Memory Address Register) respectively.

- MDR can load data from either the memory-bus or the processor-bus.

- MAR's input is connected to the internal-bus, while its output is connected to the external-bus.

- Instruction Decoder & Control Unit issues control signals to all processor units and implements actions
specified by the loaded instruction (in IR).

- Registers R0 through R(n-1) are accessible for general-purpose use by the programmer.

- Registers Y, Z, and Temp are used for temporary storage during program execution and are only accessible by
the processor.

- ALU's "A" input is from the multiplexer output, while the "B" input comes directly from the processor-bus.

- MUX selects between the output of Y and a constant value 4 (used for incrementing PC content) for the "A"
input of the ALU.

- Instructions involve transferring data between registers, performing arithmetic/logic operations, fetching
memory contents, and storing data into memory.

- Disadvantage: Only one data-word can be transferred over the bus in a clock cycle.

- Solution: Implement multiple internal paths to allow parallel data transfers.

Fundamental Concepts:-

To execute an instruction, processor has to perform following 3 steps:

1) Fetch contents of memory-location pointed to by PC. Content of this location is an instruction to be executed.
The instructions are loaded into IR, Symbolically, this operation is written as:
IRß [[PC]]
2) Increment PC by 4. PCß [PC] +4
3) Carry out the actions specified by instruction (in the IR).
• The first 2 steps are referred to as Fetch Phase. Step 3 is referred to as Execution Phase.
• The operation specified by an instruction can be carried out by performing one or more of the following
actions:
1) Read the contents of a given memory-location and load them into a register.
2) Read data from one or more registers.
3) Perform an arithmetic or logic operation and place the result into a register.
4) Store data from a register into a given memory-location.
5) The hardware-components needed to perform these actions are shown in Figure 5.1
9b) Write and explain the control sequence for execution of the instruction Add(R3), R1

Execution Steps for Instruction Add(R3), R1:

1. Fetch Instruction:

- Load the Program Counter (PC) value into the Memory Address Register (MAR).

- Send a read request to memory to fetch the instruction.

- Set the Mux to select the constant 4, adding it to the PC's content and storing the result in Z.

2. Update Program Counter:

- Move the updated value from Z back to the PC, incrementing it to point to the next instruction.

3. Fetch Operand:

- Transfer the fetched instruction from the Memory Data Register (MDR) to the Instruction Register (IR).

4. Decode Instruction:

- Interpret the contents of the IR using the instruction decoder.

- Activate control signals for subsequent steps based on the decoded instruction.

5. Load Operand from Memory:

- Load the contents of Register R3 into the MAR.

- Issue a read signal to memory to fetch the operand from the memory location pointed to by R3.

6. Prepare for Addition:

- Transfer the contents of Register R1 to the input Y to prepare for the addition operation.

7. Perform Addition:

- When the read operation is completed, the memory operand is available in the MDR.

- Perform the addition operation using the ALU.

8. Store Result:

- Store the sum obtained from the addition operation in Z.

- Transfer the sum from Z to Register R1.

9. End of Execution:

- The End signal triggers the start of a new instruction fetch cycle by returning to step 1.
10a) Explain with an example the different types of hazards that occur during pipelining.

There are three types of Hazards:-

1. Data hazard
2. Instruction or control hazard
3. Structural hazard

1) A data hazard: is any condition in which either the source or the

destination operands of an instruction are not available at the time
expected in the pipeline. As a result some operation has to be
delayed, and the pipeline stalls.

Let us consider an example of, one of the pipeline stages may not be able to complete its processing
task for a given instruction in the time allotted as in Figure 5.13.

Figure 5.13: Execution unit takes more than one cycle for execution

Here instruction I2 requires three cycles to complete, from cycle 4 through cycle 6. Thus, in cycles 5
and 6, the Write stage must be told to do nothing, because it has no data to work with. Meanwhile, the
information in buffer B2 must remain intact until the Execute stage has completed its operation. This means
that stage 2 and, in turn, stage1 are blocked from accepting new instructions because the information in B1
cannot be overwritten. Thus, steps D4 and F5 must be postponed.

Pipelined operation in Figure 5.13 is said to have been stalled for two clock cycles. Normal pipelined
operation resumes in cycle 7. Any condition that causes the pipeline to stall is called a hazard.

2) Control hazards or instruction hazards: The pipeline may also be stalled

because of a delay in the availability of an instruction. For example, this may be a result of a miss in
the cache .

. Figure 5.14 has instruction hazard with it.

Instruction I1 is fetched from the cache in cycle1, and its execution proceeds normally. However, the
fetch operation for instruction I2, which is started in cycle 2,results in a cache miss. The instruction fetch unit
must now suspend any further fetch requests and wait for I2 to arrive. We assume that instruction I2 is received
and loaded into buffer B1 at the end of cycle 5. The pipeline resumes its normal operation at that point.
 Figure 5.14 Instruction Hazard

3) Structural hazard: This is the

situation when two instructions require the use of a given hardware
resource at the same time.

Example: Load X(R1),R2

The memory address, X+[R1], is computed in step E2 in cycle4, then memory access takes place in cycle5.The
operand read from memory is written into register R2 in cycle 6. This means that the execution step of this
instruction takes two clock cycles (cycles 4 and 5). It causes the pipeline to stall for one cycle, because both
instructions I2 and I3 require access to the register file in cycle 6 which is shown in Figure 5.15.

Figure 5.15: Structural hazard

 Even though the instructions and their data are all available, the pipeline stalled because one hardware
resource, the register file, cannot handle two operations at once. If the register file had two input ports, that is,
if it allowed two simultaneous write operations, the pipeline would not be stalled. In general, structural hazards
are avoided by providing sufficient hardware resources on the processor chip.

The most common case in which this hazard may arise is in access to memory. One instruction may
need to access memory as part of the Execute or Write stage while another instruction is being fetched. If
instructions and data reside in the same cache unit, only one instruction can proceed and the other instruction
is delayed.

10b) Write and explain the control sequence for the execution of an unconditional branch instruction.

Control Sequence for an Unconditional Branch Instruction:

1. Start and Fetch Phase:

- Processing begins, and the fetch phase ends.
- Steps 1 to 3.

2. Extract Offset:
- Offset value is extracted from the Instruction Register (IR) through instruction decoding.
- Step 4.

3. Calculate Branch Address:

- The offset value is added to the current value of the Program Counter (PC).
- Resulting branch address is loaded into the PC.
- Step 5.

Explanation:
- The branch instruction directs the PC to fetch the next instruction from a specific branch target address.
- Typically, the branch target address is obtained by adding the offset to the current PC value.
- The offset represents the difference between the branch target address and the address immediately
following the branch instruction.
- In the case of a conditional branch, the status of condition codes needs to be checked before updating the PC.
- If the condition is met (e.g., N = 0), the processor returns to step 1.
- If the condition is not met (e.g., N = 1), a new value is loaded into the PC in step 5.