232 IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 33, NO.
2, MAY 2020
Resistance Measurement Platform for Statistical
Analysis of Emerging Memory Materials
Takeru Maeda , Yuya Omura, Rihito Kuroda , Akinobu Teramoto , Tomoyuki Suwa, and Shigetoshi Sugawa
Abstract—A resistance measurement platform for the statisti-
cal evaluation of emerging memory materials is presented. We
developed two types of platforms, depending on the resistance
range of memory materials. The high resistance (HR) mea-
surement typemeasures the resistance of 490,000 cells in
the range of 2.85 k − 10 M within 497 ms. The low
resistance (LR)measurement type measures the resistance of
10,000 cells in the range of 390  − 10 M within11 ms. Various
memory materials can be commonly tested only by forming mate-
rials on top of the platform. We measured the resistance of
N+ Poly-Si resistors formed by the platform fabrication process to
verify the circuit operation. We also measured the on-resistance
of selectors (RON ) by shorting each cell to GND for the con-
firmation of the background resistance. Moreover, we formed
α-Si on the platform by PE-CVD to test the process of forming
materials on the platform. Then the resistance of α-Si and its
temporal variation showing random telegraph noise behaviors
were measured statistically.
Index Terms—Resistance, measurement, memory testing.
I. I NTRODUCTION
N RECENT years, emerging memories are receiving much
I attention which is expected to be applied to various applica-
tions such as in-memory computing [1], [2] for neuromorphic
applications [3], [4], embedded memories for microcontrollers
unit (MCU) [5], [6], storage-class memories (SCMs) [7]–[11],
and system on a chip (SoC) [6], [12]. There are various emerg-
ing memories such as Resistive Random-Access Memory
(ReRAM) [13]–[21], Magnetic RAM (MRAM) [22]–[27],
Phase Change Memory (PCM) [28]–[35], Ferroelectric
Tunnel Junction (FTJ) memory [36], [37], and ionic
memory [38]–[40]. These emerging memory technologies
commonly make use of resistance changes to record data,
Manuscript received November 5, 2019; revised December 18, 2019;
February 15, 2020; and March 10, 2020; accepted March 20, 2020. Date
of publication March 26, 2020; date of current version May 5, 2020.
(Corresponding author: Takeru Maeda.)
Takeru Maeda and Yuya Omura are with the Graduate School
of Engineering, Tohoku University, Sendai 980-8579, Japan (e-mail:
takeru.maeda.s8@dc.tohoku.ac.jp).
Rihito Kuroda and Shigetoshi Sugawa are with the Graduate School of
Engineering, Tohoku University, Sendai 980-8579, Japan, and also with the
New Industry Creation Hatchery Center, Tohoku University, Sendai 980-8579,
Japan (e-mail: rihito.kuroda.e3@tohoku.ac.jp).
Akinobu Teramoto is with the New Industry Creation Hatchery
Center, Tohoku University, Sendai 980-8579, Japan, and also with the
Research Institute for Nanodevice and Bio Systems, Hiroshima University,
Higashihiroshima 739-8527, Japan.
Tomoyuki Suwa is with the New Industry Creation Hatchery Center, Tohoku
University, Sendai 980-8579, Japan.
Color versions of one or more of the figures in this article are available
online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TSM.2020.2983100
0894-6507 
c 2020 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See https://www.ieee.org/publications/rights/index.html for more information.
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although each has a different operating principle. Therefore,
various memory materials can be commonly tested by mea-
suring their resistance. It is essential to measure the resistance
of memory materials on a large scale, at high speed with high
accuracy for the statistical evaluation of memory materials.
However, it takes a large amount of cost and a long time
to design and fabricate custom evaluation circuits. Also, it is
difficult to statistically test the new memory materials with-
out circuit technologies, fabrication capability of integrated
circuits or evaluation and analysis techniques of memories.
In order to overcome these challenges, we developed resis-
tance measurement platforms for statistical evaluation of
new memory materials with a very easy process. Various
memory materials can be commonly tested only by form-
ing materials on the bottom electrode (BE) of the top of the
platform. The platform contributes to shortening turnaround
time from the fabrication to the evaluation of new memory
materials and providing opportunities for R&D of emerg-
ing memory materials. In this work, two types of resistance
measurement platforms are described, which can be utilized
depending on the resistance range of memory materials,
i.e., high resistance (HR) platform, and low resistance (LR)
platform.
In the 32nd IEEE International Conference on
Microelectronic Test Structures (ICMTS), we presented
the verification of circuit operations of the HR platform [41]
by measuring the resistance of 234 N+ Poly-Si devices-
under-test (DUTs), and also presented measurement results of
α-Si formed by PE-CVD on top of the HR platform. In this
paper, we additionally measured the effect of series resistance
arising from selector transistors. Also, the resistance of
100N+ Poly-Si DUTs of the LR platform was measured in
order to verify its circuit operation. Moreover, we formed α-Si
on both HR and LR platforms and evaluated its resistance
and the temporal variation statistically.
II. E XPERIMENTAL M ETHODS
A. Design Concept of the Platform
Figure 1 shows the cross-sectional diagrams of the platform.
The lower layers up to 5-layer-metal (M5) are the common
array test circuit part, and the top layers above M5 are the DUT
part formed by simple process steps. The lower array test cir-
cuit can be used in common regardless of the DUT. Moreover,
only by changing processes of the DUT part, we can measure
various memory materials using the common array test cir-
cuit. The platform facilitates statistical evaluations of various
 MAEDA et al.: RESISTANCE MEASUREMENT PLATFORM FOR STATISTICAL ANALYSIS OF EMERGING MEMORY MATERIALS
Fig. 1. Cross-sectional diagrams of the resistance measurement platform.
Fig. 2. A cell circuit schematic diagram of the platform.
memory materials and shortens the turnaround time thanks
to the simplicity of the process steps required to evaluate new
memory materials. In the common array test circuit part, there
are test cells that consist of N+ Poly-Si DUTs. By measur-
ing the resistance of N+ Poly-Si DUTs, we can verify the
resistance measurement operation.
B. Cell Circuit Operation
Figure 2 shows acell circuit diagram of the platform.
There are two kinds of cell circuit operations; resistance
measurement operation and stress application operation.
During the resistance measurement operation, the current
(ICS ) is applied to the DUT through the selector by operating
the PMOS current source (PCS), then a potential difference
occurs across the DUT. The resistance of the DUT is calcu-
lated by dividing the voltage difference between the top and
bottom electrodes (VTE and VBE ) by ICS . The current range
of the PCS is 100 nA − 100 μA on the HR platform and
100 nA − 700 μA on the LR platform. The operating voltage
range of the PCS is 0 − 1 V on both HR and LR platforms.
From these current and voltage ranges of the PCS, the max-
imum measurement range is determined to be 10 M. The
potential difference also occurs across the selector due to its
on-resistance (RON ). The sum resistance value of RDUT + RON
is calculated by measuring the voltage of the column sig-
nal line (COL). The measured resistance includes the RON
in addition to the RDUT , and the RON varies from cell to cell.
Therefore, the RON determines the lower limit of the measure-
ment range. The RON depends on the size of the selector, and
the selector is designed to be W/L = 23.7/0.32 μm on the HR
platform and W/L = 1725.84/0.32 μm on the LR platform in
this work by using a 0.18 μm CMOS technology.
During the stress application operation, current stress can
be applied to the DUT using PCS as in the resistance mea-
surement operation. Also, by turning on the stress switch
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233
Fig. 3. A circuit schematic diagram of the platform.
and setting the stress switch voltage (VST ) and VTE , a stress
voltage (VTE − VST ) can be applied to the DUT.
C. Readout Operation
Figure 3 shows a circuit schematic diagram of the plat-
form. The platform employs the architectures of an array test
circuit [42]–[47] to achieve a high-speed measurement with
a large number of DUTs. The arrayed DUTs are selected by
vertical and horizontal shift resisters (VSR and HSR). During
the resistance measurement operation, the output voltage of
each cell is readout by two kinds of measurement modes;
frame mode and fixed-cell mode. The frame mode is for
high-speed measurement of a large number of DUTs, and
the fixed-cell mode is for a measurement of a dedicated time
waveform of a specific cell with a high-speed sampling.
In the frame mode, as shown in Fig. 4(a), when the start
pulse of VSR (φVS ) is applied externally, selectors in each row
turn on one by one. Then the output voltages of the selected
row are stored in analog memories (AMs) by applying AM
switch pulse (φAM). Then HSR scans AMs, and stored volt-
ages in AMs are readout to the horizontal signal line (HLINE)
by charge sharing between the capacitance of AM (CAM ) and
the parasitic capacitance of HLINE (CH ). Finally, output volt-
ages are readout to the outside of the platform through the
output buffer one after another. During the HSR scanning
period, DUTs in the next row are selected by incrementing
the state of VSR, then the parasitic capacitance of COL is
charged to the output voltage of the selected DUTs in the next
row. This parallel operation of scanning HSR and selecting
the next DUTs reduces the measurement time. The measure-
ment time on frame mode depends on the AM charging time
and HSR scanning time. In this work, we temporarily set the
AM charging time to 10 μs, and HSR scanning frequency to
1MHz, as shown in Fig. 4(a). Then, the resistance measure-
ment of one row is conducted in 710 μs on the HR platform
(700 cells/row) and 110 μs on the LR platform (100 cells/row).
Therefore, the whole cells are measured with 497 ms on the
HR platform (700H × 700V cells), and with 11 ms on the LR
platform (100H × 100V cells).
In the fixed-cell mode, as shown in Fig. 4(b), VSR and
HSR increment to one specific cell by applying clock signals
(VCLK and HCLK ), and select a cell. Then, the output voltage
of the selected cell is continuously readout with the sampling
frequency of up to 20 MHz. The fixed-cell mode is suitable
 234 IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 33, NO. 2, MAY 2020
Fig. 4. Pulse timing diagrams of (a) frame mode and (b) fixed-cell mode.
Fig. 5. Photographs of (a) high-resistance (HR) platform and (b) low-
resistance (LR) platform.
Fig. 6. A process flow to short the bottom and top electrodes for the
measurement of RON .
for the measurement of detailed time waveforms such as fluc-
tuations of random noise and transient response when setting
and resetting memory state.
We can reduce the temporal background noise by measur-
ing each cell multiple times and averaging multi-samplings on
both frame and fixed-cell modes.
D. Design Specification and Performance Summary
Figure 5 shows the photographs of (a) HR platform
and (b) LR platform. The platforms were fabricated by
a 0.18 μm 1-Poly-Si 5-metal layers CMOS technology. The
chip size is 5,000H μm × 5,000V μm. On the HR plat-
form, there are 700H × 700V primary cells with the size of
5.6H μm × 5.6V μm for the measurement of memory mate-
rials, and 234 test cells with the same size that contain N+
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Fig. 7. I-V characteristics of 32H × 32V selectors of (a) HR platform
and (b) LR platform.
Fig. 8. Normal quantile plots of on-resistance of (a) 700H × 700V selectors
of the HR platform and (b) 100H × 100V selectors of the LR platform.
Poly-Si for the verification of the circuit operation. On the LR
platform, there are 100H × 100V primary cells with the size
of 40H μm × 40V μm and 100 test cells with the same size.
III. R ESULTS AND D ISCUSSION
A. RON Measurements
Figure 6 shows a process flow to short the bottom and
top electrodes (BE and TE) for the measurement of RON .
A 500 nm thick top SiO2 was removed across the entire sur-
face of BEs by dry etching process, then 500 nm thick Al TE
was sputtered on the TiN BEs. We can measure the RON by
shorting BE and TE as this structure.
Figure 7 shows the typical I-V characteristics of center
32H × 32V shorted cells of (a) HR platform and (b) LR
 MAEDA et al.: RESISTANCE MEASUREMENT PLATFORM FOR STATISTICAL ANALYSIS OF EMERGING MEMORY MATERIALS 235

TABLE I
A P ERFORMANCE S UMMARY OF THE P LATFORM

Fig. 10. I-V characteristics of N+ Poly-Si discrete TEGs with the same size
of N+ Poly-Si as (a) HR platform and (b) LR platform.

Fig. 9. I-V characteristics of (a) 234 N+ Poly-Si DUTs of the HR platform

and (b) 100 N+ Poly-Si DUTs of the LR platform.

platform. In this measurement, the frame mode is used, and

each plot uses the average value of 106 frames.
Figure 8 shows the normal probability plots of the
RON of (a) HR platform and (b) LR platform calculated from
the slopes of the I-V characteristics. The distributions were
curved, indicating the resistance variations do not follow
the normal distribution. Assuming the parasitic resistance is
smaller than RON , on the HR platform, the average RON was
285  with the standard deviation (σ ) of 5.24 , and on the
LR platform, the average RON was 39  with the σ of 0.63 .
From these results, we defined the lower limit of the measure-
ment range of the platform to 2.85 k on the HR platform,
and 390  on the LR platform supposing the allowable error
due to the RON is 10%.
The design specifications and measurement range of the
developed two kinds of platforms are summarized in Table I.
B. N+ Poly-Si Measurements
Figure 9 shows the I-V characteristics of (a) 234 N+ Poly-
Si DUTs of the HR platform and (b) 100 N+ Poly-Si DUTs
of the LR platform. In this measurement, the frame mode is
used, and each plot uses the average value of 106 frames. The
resistance measured by HR and LR platforms includes RON .
Figure 10 shows the I-V characteristics of (a) 52 N+ Poly-
Si discrete TEGs with the same size of N+ Poly-Si as the HR
platform and (b) 28 N+ Poly-Si discrete TEGs with the same
size of N+ Poly-Si as the LR platform. A source-measure-unit
Fig. 11. Normal quantile plots of the resistance of (a) 234 N+ Poly-Si DUTs
of the HR platform and (b) 100 N+ Poly-Si DUTs of the LR platform.
(SMU, HP 4156B) was used to measure these discrete TEGs.
The resistance of discrete TEGs does not include RON .
Figure 11 shows the comparison of the normal probability
plots of the resistance of N+ Poly-Si between platform array
and discrete TEGs. The resistance distributions of HR and LR
platformsrepresent the resistance value calculated by subtract-
ing RON from the measured value. As shown in Fig. 11(a),
The resistance distributions of the HR platform and discrete
TEGs were linear, indicating the resistance variations follow
the normal distribution. The average resistance value of the
HR platform after subtracting RON was 5.30 k, with the σ of
19.3 . Also, the average resistance value of the discrete TEGs
was 5.29 k, with the σ of 103 . As shown in Fig. 11(b),
The resistance distributions of the LR platform and discrete
TEGs were not linear, and the resistance variations did not
follow the normal distribution. The average resistance value

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 236 IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 33, NO. 2, MAY 2020

TABLE II
T HE S UMMARY OF M EASUREMENT R ESULTS OF F IGS . 7–12

Fig. 13. I-V characteristics of 32H × 32V α-Si DUTs formed on (a) HR
platform and (b) LR platform.

Fig. 12. A Process flow to form α-Si on the platform.

of the LR platform after subtracting RON was 266 , with the

σ of 8.38 . Also, the average resistance value of the discrete
TEGs was 265 , with the σ of 11.6 .
Comparing the distributions of the platform and discrete
TEGs, while the average values almost matched, the σ differed
on both HR and LR platforms. The slight difference in the
average value and the clear difference in σ are considered
to be caused by the fact that the DUTs on the platform are
integrated in a 5 mm × 5 mm chip, while discrete TEGs are
distributed over the entire surface of an 8-inch wafer.
Since linear I-V plots were measured and average values of
the platform and discrete TEGs were well agreed on both HR
and LR platforms, it is considered that the circuit operation of
the platforms was verified.
The average resistance values and the standard deviations
(σ ) of the resistance of selectors (RON ) and N+ Poly-Si DUTs
(RPoly ) of the HR platform, LR platform, and discrete TEGs
are summarized in Table II.
C. α-Si Measurements
Figure 12 shows a process flow to form α-Si on the plat-
form. The 500 nm thick top SiO2 was removed partly inside
each cell by a wet etching process. The opening area of the BE
was φ900 nm. After opening the SiO2 , a 200 nm thick α-Si
doped with phosphorus was formed on TiN BEs by plasma-
enhanced chemical vapor deposition (PE-CVD), and 500 nm
thick Al TE was sputtered on top of it. The α-Si was formed on
the HR and LR platforms simultaneously in the same chamber.
Fig. 14. Normal quantile plots of the resistance of α-Si DUTs on (a) HR
platform and (b) LR platform.
Figure 13 shows the typical I-V characteristics of center
32H × 32V cells of (a) HR platform and (b) LR platform. In
this measurement, the frame mode is used, and each plot uses
the average value of 106 frames.
Figure 14 shows the normal probability plots of the resis-
tance of α-Si on (a) HR platform and (b) LR platform
calculated from the slopes of I-V characteristics. The dis-
tributions were roughly linear, and the resistance variations
followed the normal distribution. On the HR platform, the
average resistance was 336.3k with the σ of 993.4 , and
on the LR platform, the average resistance was 339.7k with
the σ of 409.6. The volume resistivity of α-Si calculated by
dividing the multiplication of average resistance and opening
area (φ900 nm) by the film thickness (200 nm) was 107 ·cm
on the HR platform and 108 ·cm on the LR platform. The
volume resistivities on both platforms showed almost the same

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 MAEDA et al.: RESISTANCE MEASUREMENT PLATFORM FOR STATISTICAL ANALYSIS OF EMERGING MEMORY MATERIALS
TABLE III
T HE S UMMARY OF M EASUREMENT R ESULTS OF F IGS . 13–15
Fig. 15. Resistance maps of α-Si DUTs of (a) HR platform and (b) LR
platform.
value. From these results, it was confirmed that the resistance
of the material formed on the platform could be measured.
The summary of the measurement results of Figs. 7–14 are
shown in Table III.
Figure 15 shows the resistance maps of α-Si DUTs
of (a) HR platform and (b) LR platform. In the HR plat-
form, wavy patterns were observed in the right part and upper
right to lower left parts of the cell array, which seems to be
attributed to the fabrication process. In the LR platform, the
resistance distribution appeared to have a horizontal corre-
lation, and the cause is under investigation. Although some
results need additional verification, it was shown that the plat-
form could visualize the spatial distribution of the resistance
of materials.
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237
Fig. 16. Cumulative probability of the VRMS of α-Si DUTs formed on (a) HR
platform and (b) LR platform in Gumbel plots.
Equation (1) shows the root-mean-square of the output
voltages in the time domain (VRMS ). Xi shows a measured
voltage at each time (i), μ shows the average value of
whole measured voltages, and n shows the number of ele-
ments. VRMS represents the standard deviation of the output
voltages and suitable for expressing a noise level, such as
random-telegraph-noise (RTN) [48], [49].

 n
 (Xi − μ)2
VRMS =  (1)
n
i=1
Figure 16 shows the cumulative probability of the VRMS
of α-Si DUTs on (a) HR platform and (b) LR platform in
Gumbel plots. The VRMS is large in cells where RTN occurs.
In this measurement, the fixed-cell mode is used, and each
plot represents the VRMS of 106 voltages measured with the
sampling frequency of 10 MHz.
Figure 17 shows the typical time waveforms of the out-
put voltage at each cumulative probability shown in Fig. 16.
The random telegraph signal in measured temporal resistance
characteristics with various time constants and amplitude were
observed. It was shown that the platform could statistically
measure the fluctuations of the random noise of materials.
Figure 18 shows the relationship between averaging times
and noise. The Y-axis shows the standard deviation of the
moving average of 106 measurement data when the number
of terms is changed from 1 to 106 . In this work, we measured
each cell 106 times temporarily. In practice, the averaging
times can be flexibly changed depending on the required noise
level. As shown in Fig. 18, for example, the measurement of
 238
Fig. 17. Typical time waveforms of the output voltage shown in Fig. 17.
Fig. 18. The relationship between average count and noise.
20 frames has a noise level of 21 μVRMS , and this noise value
is smaller than the highest resolution value of the high-speed-
ADC of the general SMU (e.g., 25 μV for Agilent B1500A).
Therefore, averaging about 20 times on the platform is enough
for the measurement with the noise level similar to general
SMU. Of course, more averaging leads to lower noise levels.
IV. C ONCLUSION
We developed two types of platforms, which can be utilized
depending on the resistance range of memory materials. The
HR platform measures the resistance of 2.85 k − 10 M on
a large scale of 490,000 cells within 497 ms by the frame mea-
surement mode, and the LR platform measures the resistance
of 390 −10 M on a large scale of 10,000 cells within 11 ms
by the frame measurement mode. We verified the circuit oper-
ation by measuring the resistance of shorted cells, N+ Poly-Si
test cells, and α-Si cells. The developed platform is useful for
the statistical evaluation of the electrical characteristics such
as I-V characteristics and the fluctuations of random noise of
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IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 33, NO. 2, MAY 2020
various memory materials. In this work, the lower limit of the
measurement range depended on the RON . We are now work-
ing on developing an accuracy improved platform [50] that
can exclude RON and confirming the circuit operation. The
platform contributes to providing research and development
opportunities for emerging memory materials and shortening
turnaround time from trial production to evaluation of new
memory materials.
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