Digital System Design and Implementation

Homework #1
(Due on 03/15 PM 8:00)
Note: Please upload your codes to eeClass and hand in the hardcopy of this experiment
including
a. Verilog Codes (60%)
b. Test bench (20%)
c. Input/Output waveforms.(20%)

1. For even-numbered students,

Fig. 1 Block diagram of type 1

a. Please use Verilog to describe the digital circuits in Fig. 1.

b. Write a test bench to test your design.
c. The input waveforms are given as the following patterns. For students of lab time
on Thursday, the “Sel” signal is low for 5 clock cycles and high for 5 clock cycles.
For students of lab time on Friday, the “Sel” signal is high for 5 clock cycles and
low for 5 clock cycles.
50ns

Sel
(Thursday)

Sel
(Friday)

O1 ?

Fig. 2. Test pattern for type-1 block.

2. For odd-numbered students,

Fig. 3 Block diagram type 2

a. Please use Verilog to describe the digital circuits in Fig. 3.

b. Write a test bench to test your design.
c. The input waveforms are given as in Fig.3. For students of lab time on Thursday,
the “Sel” signal is low for 5 clock cycles and high for 5 clock cycles. For students
of lab time on Friday, the “Sel” signal is high for 5 clock cycles and low for 5
clock cycles.

50ns

Sel
(Thursday)

Sel
(Friday)

O2 ?

Fig. 4. Test pattern for type-2 block.