MPS - Ch02 - AVR Architecture and Assembly Language Programming

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Chapter 2
AVR Architecture and
Assembly Language Programming
The AVR microcontroller

and embedded
systems
using assembly and c
AVR Microcontroller and Embedded System Using Assembly and C © 2011 Pearson Higher Education,
Mazidi, Naimi, and Naimi Upper Saddle River, NJ 07458. • All Rights Reserved.
Topics
❖ AVR Architecture
• ATMega32 Pin out & Descriptions
• ATMega32 Architecture
❑ Memories: Flash, Data EEPROM, and internal SRAM
❑ Registers (GP, I/O , special: SP, PC, and SREG)
❑ ISA – AVR instructions
❑ Addressing modes
❑ Some simple instructions
❖ Assembly Language Programming

• Structure of Assembly language
• Assembling an AVR program
• Assembler directives and operators
❖ Pipelining and RISC architecture
2
ATMega32 Pin out & Descriptions
Clears all the

Port B Port A
registers supply
Provides and
restart the
voltage to the Reference voltage
These
chip. Itpins
execution are
of be
should for ADC
Supply voltage
used to connect
program
connected to +5 for ADC and
external crystal
portA. Connect it
or RC oscillator
to VCC
Port C
Port D
3
ATMega32 Pin out & Descriptions (2/10)
C  22 pF
f = 1/(3RC)
4
5
Digital IO is the most fundamental mode of connecting a MCU to external
world. The interface is done using what is called a PORT. A port is the
point where internal data from MCU chip comes out or external data
goes in. They are present is form of PINs of the IC. Most of the PINs are
dedicated to this function and other pins are used for power supply, clock
source etc . ATMega32 ports are named PORTA, PORTB, PORTC, and
PORTD.
6
ATMega32 Pin out & Descriptions (5/10) - GPIO
7
Mega32/Mega16
(XCK/T0) PB0 PA0 (ADC0)
(T1) PB1 PA1 (ADC1)
(INT2/AIN0) PB2 PA2 (ADC2)
(OC0/AIN1) PB3 PA3 (ADC3)
(SS) PB4 PA4 (ADC4)
(MOSI) PB5 PA5 (ADC5)
(MISO) PB6 PA6 (ADC6)
(SCK) PB7 PA7 (ADC7)
PINA
PORTB
DDRB
PINB
RESET DDRA AREF
PORTA
VCC AGND
PORTC
GND DDRC AVCC
PINC
XTAL2 PC7 (TOSC2)
XTAL1 PC6 (TOSC1)
(RXD) PD0 PC5 (TDI)
(TXD) PD1 PC4 (TDO)
(INT0) PD2 PC3 (TMS)
(INT1) PD3 PC2 (TCK)
(OC1B) PD4 PC1 (SDA)
(OC1A) PD5 PC0 (SCL)
(ICP) PD6 PD7 (OC2)
8
❑ ATMega32 I/O Port Registers
There are three registers associated with Input/ Output Ports in AVR.
• DDRx - Data Direction Register for Port x (x = A, B, C, D).

• PORTx - Output Data Register for Port x.
• PINx - Port Input Pins Register for Port x.
❑ Register Addresses for ATmega32 Ports
IO SRAM
Port Usage
Address Address
PORTA $1B $3B Output
DDRA $1A $3A Direction
PINA $19 $39 Input
PORTB $18 $38 Output
DDRB $17 $37 Direction
PINB $16 $36 Input
PORTC $15 $35 Output
DDRC $14 $34 Direction
PINC $13 $33 Input
PORTD $12 $32 Output
DDRD $11 $31 Direction
PIND $10 $30 Input
❑ The structure of IO pins Mega32/Mega16
(XCK/T0) PB0 0 00 00 0 PA0 (ADC0)
(T1) PB1 1 11 11 1 PA1 (ADC1)
(INT2/AIN0) PB2 2 22 22 2 PA2 (ADC2)
(OC0/AIN1) PB3 3 33 33 3 PA3 (ADC3)
(SS) PB4 4 44 44 4 PA4 (ADC4)
(MOSI) PB5 5 55 55 5 PA5 (ADC5)
(MISO) PB6 DDRx:
6
7
6 66 5 4 3
6 26 61 0 PA6 (ADC6)
(SCK) PB7PORTx:
7
7
7 67 5 4 3
7 27 71 0 PA7 (ADC7)
DDRA
DDRB
PINB
PORTB
RESETPINx: 7 6 5 PORTA
4 3 2 1 0 AREF
PINA
VCC AGND
GND Px7 Px6 Px5 Px4 Px3 Px2 Px1 Px0 AVCC
XTAL2 PC7 (TOSC2)
XTAL1 PC6 (TOSC1)
(RXD) PD0 PC5 (TDI)
(TXD) PD1 PC4 Input
(TDO) Output
(INT0) PD2 PC3 (TMS)
DDRx
DDRx.n
0 1
(INT1) PD3 PORTx
PC2 (TCK)
PORTx.n
(OC1B) PD4 PC1
0 high
(SDA)impedance Out 0
(OC1A) PD5 PINx.n PC0
1 (SCL)pull-up Out 1
(ICP) PD6 PD7 (OC2)
LDI R20,0x75 ;R20 = 0b01110101 (binary)
// Configuring I/O pins of port A OUT PORTA,R20 ;PORTA = R20
DDRA = 0b01110101; OUT DDRA,R20 ;DDRA = R20
Pull-up resistors are used in electronic logic circuits to ensure
that inputs to logic systems settle at expected logic levels if
external devices are disconnected or high-impedance
vcc
1 = Close
PORTx.n 0 = Open
pin n of
port x PINx.n
Outside the Inside the

AVR chip AVR chip
12
Topics

13
AVR MCU
• The AVR is a Harvard architecture CPU.
• Harvard Architecture
❑ Computer architectures that used physically separate storage
and signal pathways for their instructions and data.
❑ CPU can read both an instruction and data from memory at the
same time that makes it faster.
Harvard Architecture diagram

14
AVR MCU
▪ A series of 8-bit RISC microcontrollers from Atmel.
▪ All AVR microcontrollers share same instruction set and a basic CPU
(Harvard) architecture.
▪ It has 32 8-Bit general purpose registers.
▪ Mostly instruction Execute in Single clock cycle. Which makes it

faster among 8 bit microcontrollers.
▪ AVR was designed for efficient execution of compiled C code.
▪ AVR is a family of 8-bit microntrollers with a large range of variants

differing in:
- size of program-memory (flash)
- size of EEPROM memory
- number of I/O pins
- number of on-chip features such as UART and ADC
15
ATMega32 Architecture I/O Ports
• Native data size is 8 bits (1 byte).

• Uses 16-bit data addressing
allowing it to address 216 = 65536
unique addresses.
• Has three separate on-chip
memories
• 2KB SRAM: 8 bits wide used
to store data
• 1KB EEPROM: 8 bits wide
used for persistent data
storage
• 32KB Flash: 16 bits wide
used to store program code
• I/O ports A-D
• Digital input/output
• Analog input
• Serial/Parallel
• Pulse accumulator
I/O Ports
16
Block Diagram of the AVR MCU Architecture
I/O and special functions

ALU Instructions
Instruction Fetch
and Decode
17
ATMega32 – Memory
1. 2KB SRAM
– For temporary data storage
– Memory is lost when power is shut
off (volatile)
– Fast read and write
2. 1KB EEPROM
– For persistent data storage
– Memory contents are retained when
power is off (non-volatile)
– Fast read; slow write
– Can write individual bytes
3. 32KB Flash Program Memory

– Used to store program code
– Memory contents retained when
power is off (non-volatile)
– Fast to read; slow to write
– Can only write entire “blocks” of
memory at a time
– organized in 16-bit words
(16KWords)
18
ATMega32 – Memory
• AVR microcontrollers are Harvard architecture. This
means, that in this architecture are separate memory
types (program memory and data memory) connected
with distinct buses. Such memory architecture allows
processor to access program memory and data memory
at the same time. This increases performance of MCU
comparing to CISC architecture, where CPU uses same
bus for accessing program memory and data memory.
• Each memory type has its own address space:

Type Flash RAM EEPROM
F_END Size, kB RAMEND Size, kB E_END Size, kB
Atmega8 $0FFF 8 $045F 1 $1FF 0.5
Atmega32 $3FFF 32 $085F 2 $3FF 1
Atmega64 $7FFF 64 $10FF 4 $7FF 2
Atmega128 $FFFF 128 $10FF 4 $FFF 4
m32def.inc
; ***** DATA MEMORY DECLARATIONS
.equ FLASHEND = 0x3fff ; Note: Word address
.equ RAMEND = 0x085f
19
.equ EEPROMEND = 0x03ff
ATMega32 – Program Memory
Flash Memory Layout
20
ATMega32 – Data Memory: EEPROM
EEPROM
• ATmega32 contains 1024 bytes of data EEPROM memory.
• It is organized as a separate data space, in which single bytes
can be read and written.
• The EEPROM has an endurance of at least 100,000 write/erase
cycles.
• Different chip have different size of EEPROM memory
Chip Bytes Chip Bytes Chip Bytes
ATmega8 512 ATmega16 512 ATmega32 1024

ATmega64 2048 ATmega128 4096 ATmega256RZ 4096
ATmega640 4096 ATmega1280 4096 ATmega2560 4096
21
ATMega32 – Data Memory: SRAM
The data memory is composed
of three parts:
• GPRs (general purpose
registers) (or GP registers),
• Special Function Registers

(SFRs), and
• Internal data SRAM

(SRAM).
22
ATMega32 – Internal SRAM
• Internal data SRAM is widely used for storing data and

parameters by AVR programmers and C compilers.
• Each location of the SRAM can be accessed directly by

its address.
• Each location is 8 bit wide and can be used to store any

data we want.
• Size of SRAM is vary from chip to chip, even among

members of the same family.
23
On-chip Data SRAM Access Cycles
Notes:
• Tn = 1 MC (Machine Cycle) = 1/XTAL
• XTAL = Crytal Frequency in the oscillator of AVR. 24
Review Number Notation
• The AVR documentation and assembler use several notations
for numbers, and we will follow these in the lecture notes.
• By default, numbers are decimal. Thus “10” means “ten,
decimal”.
• Hexadecimal numbers are written as 0xAB, or 0xaB, or
0xAb. The leading character is a zero. Sometimes
hexadecimal number are written as $AB.
• Binary numbers are written as 0b10101011. The leading
character is a zero.
• Octal numbers begin with “0” (zero). For example: 0253
25
Little endian vs. big endian
(Part I, Chapter 4, Gulliver’s Travels)
• Byte Ordering: How should bytes within multi-byte
word be ordered in memory?
• Conventions
– Big Endian: Sun, PPC Mac, . . .
❑ Least significant byte has highest address
– Little Endian: x86 (Intel), AVR, . . .
❑ Least significant byte has lowest address
• Example
– Variable x has 4-byte representation 0x01234567
– Address given by &x is 0x100
Big Endian
0x100 0x101 0x102 0x103
01 23 45 67
Little Endian 0x100 0x101 0x102 0x103

67 45 23 01 26
ATMega32 – Registers
27
ATMega32 – Registers (GPRs)
The fast-access Register file

contains 32 x 8-bit general
purpose working registers
with a single clock cycle
access time. This allows
single-cycle Arithmetic Logic
Unit (ALU) operation. In a
typical ALU operation, two
operands are output from the
Register file, the operation is
executed, and the result is
stored back in the Register
file –in one clock cycle.”
28
“Six of the 32 registers can be

used as three 16-bit indirect
address register pointers for
Data Space addressing –
enabling efficient address
calculations. One of the these
address pointers can also be
used as an address pointer for
look up tables in Flash Program
memory. These
added function registers are the
16-bit X-register, Y-register and
Z-register, described later.”
29
❑ The R26..R31 registers have some added functions to their general
purpose usage. These registers are 16-bit address pointers for indirect
addressing of the Data Space. The three indirect address registers X, Y,
and Z are shown above.
❑ In the different addressing modes these address registers have

functions as fixed displacement, automatic increment, and automatic
decrement
30
ATMega32 – I/O Registers (SFRs)
• The I/O memory is dedicated to
Address Name Address Name Address Name
specific functions such as status I/O Mem. I/O Mem. I/O Mem.
register, timers, serial $00 $20 TWBR $16 $36 PINB $2B $4B OCR1AH
$01 $21 TWSR $17 $37 DDRB $2C $4C TCNT1L
communication, I/O ports, ADC and $02 $22 TWAR $18 $38 PORTB $2D $4D TCNT1H
etc. $03 $23 TWDR $19 $39 PINA $2E $4E TCCR1B
$04 $24 ADCL $1A $3A DDRA $2F $4F TCCR1A
• Function of each I/O memory $05 $25 ADCH $1B $3B PORTA $30 $50 SFIOR
location is fixed by the CPU designer $06 $26 ADCSRA $1C $3C EECR OCDR
$1D $3D EEDR $31 $51
$07 $27 ADMUX OSCCAL
at the time of design. (because it is $08 $28 ACSR $1E $3E EEARL $32 $52 TCNT0
used for control of the $09 $29 UBRRL $1F $3F EEARH $33 $53 TCCR0
$0A $2A UCSRB UBRRC
microcontroller and peripherals) $0B $2B UCSRA
$20 $40
UBRRH
$34 $54 MCUCSR
$35 $55 MCUCR
• AVR I/O memory is made of 8 bit $0C $2C UDR $21 $41 WDTCR $36 $56 TWCR
$0D $2D SPCR $22 $42 ASSR $37 $57 SPMCR
registers. $0E $2E SPSR $23 $43 OCR2 $38 $58 TIFR
• All of the AVRs have at least 64 $0F $2F SPDR $24 $44 TCNT2 $39 $59 TIMSK
$10 $30 PIND $25 $45 TCCR2 $3A $5A GIFR
bytes of I/O memory location. (This $11 $31 DDRD $26 $46 ICR1L $3B $5B GICR
64 bytes section is called standard $12 $32 PORTD $27 $47 ICR1H $3C $5C OCR0
$13 $33 PINC $28 $48 OCR1BL $3D $5D SPL
I/O memory) $14 $34 DDRC $29 $49 OCR1BH $3E $5E SPH
• In other microcontrollers, the I/O $15 $35 PORTC $2A $4A OCR1AL $3F $5F SREG
registers are called SFRs (Special Corresponding memory address = I/O address + $20
Function Registers)
31
ATMega32 – Registers (SP)
32
ATMega32 – Registers (SP)
33
ATMega32 – Registers (PC)
Program counter (PC, 16-bit)
➢ Holds address of next program instruction to

be executed
➢ Automatically incremented when the ALU

executes an instruction
34
ATMega32 – Registers (SREG)
• The Status Register (SREG: 8-bit register) contains information
about the result of the most recently executed arithmetic
instruction. This information can be used for altering program flow
in order to perform conditional operations.
• SREG is updated after any of ALU operations by hardware.
MSB
(S = V  N)
35
LSB
Instruction Set Architecture (ISA)
❑ The ISA is the interface between hardware and software.

• Instructions: Encoding and semantics
• Registers
• Memory
❑ Each ISA has a set of instructions. Two main categories: CISC and RISC.
❑ AVR MCUs use RISC ISA.
36
AVR Instructions
• AVR MCU has 133 Powerful Instructions (Instruction Set)
• For AVR, almost all instructions are 16 bits long
– ADD Rd, Rr ; Rd = Rd + Rr
– SUB Rd, Rr
– MUL Rd, Rr
– BRGE k
• Few instructions are 32 bits long
– LDS Rd, k ( 0  k  65535 )
loads 1 byte from the SRAM to a register.
• All arithmetic operations are done on registers R0 - R31.
• Not all instructions are implemented in all AVR MCUs!
• Refer to the data sheet of a specific microcontroller
37
AVR [CPU] Instructions – “The Language of the Machine”
• The Instruction Set of AVR CPU can be functionally divided (or classified) into:
1. Data Transfer
2. Arithmetic and Logical
3. Bit and Bit-Test
4. Control Transfer (Branch Instructions) : “load the Program Counter”
5. MCU Control Ex: nop, sleep, wdr, break
• Data Transfer instructions are used to Load and Store data to the General Purpose
Registers, also known as the Register File.
– Exceptions are the push and pop instructions which modify the Stack Pointer,
– By definition these instructions do not modify the status register (SREG).
• “Arithmetic and Logic Instructions” plus “Bit and Bit-Test Instructions” use the ALU to
operate on the data contained in the general purpose registers.
– Flags contained in the Status Register (SREG) provide important information concerning the
results of these operations.
– For example, if you are adding two signed numbers together, you will want to know if the answer
is correct. The state of the overflow flag (OV) bit within SREG gives you the answer to this
question (1 = error, 0 no error).
• As the AVR processor fetches and executes instructions it automatically increments the
program counter (PC) so it always points at the next instruction to be executed. Control
Transfer Instructions allow you to change the contents of the PC either conditionally or
unconditionally.
– Continuing our example if an error results from adding two signed numbers together we may want
to conditionally (OV = 1) branch to an error handling routine.
38
Addressing modes
• Addressing modes specify the operand to be operated on
• The CPU can access data in various ways. The data could be in a register,
or in memory, or provided as an immediate value. These various ways of
accessing data are called addressing modes.
• The AVR provides a total of 13 distinct addressing modes, which can be
categorized into the following groups:
1. Register Direct, Single-Register (Immediate) Direct
➢ Single Register – Ex: DEC R1
➢ Single Register with Immediate – Ex: LDI R16, 15
2. Register Direct, Two Register direct – Ex: ADD R1, R2
3. (I/O and Data) Direct
➢ Data direct (SRAM) – Ex: LDS R1, 0x200
➢ I/O direct – Ex: OUT $50, R20
4. Data indirect (for SRAM access) (or Register indirect)
➢ Data indirect – Ex: LD R1, X
➢ Data indirect with pre-decrement – Ex: LD R1, -Y
➢ Data indirect with post-increment – Ex: ST Z+, R2
➢ Data indirect with displacement – Ex: LDD R2, Z + 5
6. Register Indirect Flash (for Program memory access)
➢ Register indirect Flash (implied operands) – Ex: LPM ; R0 (Z)
➢ Register indirect Flash – Ex: LPM R1, Z
➢ Register indirect Flash with auto-increment – Ex: LPM R1, Z+
The Program and Data Addressing Modes
• The AVR Enhanced RISC microcontroller supports powerful
and efficient addressing modes for access to the Program
memory (Flash) and Data memory (SRAM, Register file, I/O
Memory, and Extended I/O Memory).
• This section describes the various addressing modes

supported by the AVR architecture. In the following figures,
OP means the operation code part of the instruction word.
• To simplify, not all figures show the exact location of the

addressing bits. To generalize, the abstract terms RAMEND
and FLASHEND have been used to represent the highest
location in data and program space, respectively.
40
• Register Direct, Single Register Rd
Rd ← OP Rd
Direct Register – Single Register Addressing
Example:
LDI R17, 12 ; R17 ← 12 (load a constant)
NEG R2 ; R2 ← $00 – R2 (2’s comp of R2)
41
• Register Direct, Two Registers Rd and Rr
Rd ← Rd OP Rr
Two-Register Direct Addressing
Example:
MOV R2, R3 ; R2 ← R3
ADD R3, R4 ; R3 ← R3 + R4
42
• I/O Direct
Rd ← Rd OP Rr
I/O Direct Addressing
Example:
IN R2, PINA ; R2 ← PINA
OUT PORTC, R4 ; PORTC ← R4
43
• Data Direct
Data Direct Addressing
Example:
LDS R2, 0 ; R2 ← (0) = R0
STS $60, R4 ; ($60) ← R4
44
• Data Indirect with Displacement
Data Indirect with Displacement
Example:
LDD R1, Y+5 ; R1 ← (Y + 5)
STD Z+10, R3 ; (Z+10) ← R3
45
• Data Indirect
Data Indirect Addressing
Example:
LD R1, X ; R1 ← (X)
ST Y, R2 ; (Y) ← R2
46
• Data Indirect with Pre-decrement
Data Indirect Addressing with Pre-decrement
Example:
LD R1, -X ; X← X–1
; R1 ← (X)
47
• Data Indirect with Post-increment
Data Indirect Addressing with Post-increment
Example:
LD R1, X+ ; R1 ← (X)
; X← X+1
48
Some simple instructions
1. Loading values into the general purpose registers
LDI (Load Immediate)
• LDI Rd, k ; d = 16..31, 0 ≤ K ≤ 255
– Its equivalent in high level languages:
Rd = k
• Example: R0
R1
ALU
– LDI R16,53 R2
…
• R16 = 53 SREG: I T H S V N Z C
R15
– LDI R19,132 CPU R16
R17
– LDI R23,0x27
…
PC
• R23 = 0x27 R30
Instruction decoder
R31
Instruction Register
registers
49
Classification of Data Transfer Instructions
SRAM FLASH
(Data memory) (Program memory)
st, std, sts lpm
ld, ldd, lds GPRs mov, movw

(General purpose
registers)
in
push pop
out
ldi
I/O space Stack
(I/O registers)
Constant
50
Data transfer instructions (1/2)
Mnemonics Operands Operation Words Clocks Note
MOV Rd, Rr Rd  Rr 1 1 0 ≤ d ≤ 31, 0 ≤ r ≤ 31
MOVW Rd+1:Rd, Rr+1:Rr Rd+1:Rd  Rr+1:Rr 1 1 d,r  {0,2,...,30}
K = constant
LDI Rd, K Rd  K 1 1
d = 16..31, 0 ≤ K ≤ 255
LDS Rd, k Rd  (k) 2 2 k = SRAM address
STS k, Rr (k)  Rr 2 2 0 ≤ k ≤ 65535
LD Rd, I_reg Rd  (I_reg) 1 2
LD Rd, I_reg+ Rd  (I_reg), I_reg  I_reg + 1 1 2
I_reg = X, Y, or Z
LD Rd, -I_reg I_reg  I_reg - 1, Rd  (I_reg) 1 2 0 ≤ d ≤ 31
ST I_reg, Rr (I_reg)  Rr
0 ≤ r ≤ 31
1 2
ST I_reg+, Rr (I_reg)  Rr, I_reg  I_reg + 1 1 2
ST -I_reg, Rr I_reg  I_reg - 1, (I_reg)  Rr 1 2
51
Data transfer instructions (2/2)
Mnemonics Operands Operation Words Clocks Note

LDD Rd, Y+q Rd  (Y+q) 1 2
0 ≤ d ≤ 31, 0 ≤ q ≤ 63
LDD Rd, Z+q Rd  (Z+q) 1 2
STD Y+q, Rr (Y+q)  Rr 1 2 0 ≤ r ≤ 31, 0 ≤ q ≤ 63
STD Z+q, Rr (Z+q)  Rr 1 2

LPM R0  (Z) in program memory 1 3 Z is program mem. pointer
LPM Rd, Z Rd  (Z) in program memory 1 3 0 ≤ d ≤ 31
LPM Rd, Z+ Rd  (Z), Z ← Z + 1 1 3
IN Rd, A Rd  SFR with addr of A 1 1 0 ≤ d, r ≤ 31, 0 ≤ A ≤ 63
OUT A, Rr SFR with addr of A  Rr 1 1 A is an I/O Address
PUSH Rr (SP)  Rr, SP  SP – 1 1 2 SP is Stack Pointer
POP Rd SP  SP + 1, Rd  (SP) 1 2
Note: A is an I/O Address, SP is Stack Pointer

52
2. Arithmetic calculation
• There are some instructions for doing Arithmetic
and logic operations; such as:
ADD, SUB, MUL, AND, etc.
• ADD Rd,Rs
– Rd = Rd + Rs R0
ALU R1
– Example: R2
…
– ADD R25, R9 SREG: I T H S V N Z C
R15
R25 = R25 + R9
•
– ADD R17,R30
CPU R16
R17
…
PC
• R17 = R17 + R30
R30
Instruction decoder
R31
registers
53
A simple program
• Write a program that calculates 19 + 95
LDI R16, 19 ;R16 = 19

LDI R20, 95 ;R20 = 95
ADD R16, R20 ;R16 = R16 + R20
R0
ALU R1
R2
…
SREG: I T H S V N Z C
R15
CPU R16
R17
…
PC
R30
Instruction decoder
R31
registers
54
A simple program
• Write a program that calculates 19 + 95 + 5
LDI R16, 19 ;R16 = 19
LDI R20, 95 ;R20 = 95
LDI R21, 5 ;R21 = 5
ADD R16, R20 ;R16 = R16 + R20
ADD R16, R21 ;R16 = R16 + R21
LDI R16, 19 ;R16 = 19

LDI R20, 95 ;R20 = 95
ADD R16, R20 ;R16 = R16 + R20
LDI R20, 5 ;R20 = 5
ADD R16, R20 ;R16 = R16 + R20
55
• SUB Rd,Rs
– Rd = Rd - Rs
• Example:
– SUB R25, R9
• R25 = R25 - R9 R0
ALU R1
– SUB R17,R30 R2
…
• R17 = R17 - R30 SREG: I T H S V N Z C
R15
CPU R16
R17
…
PC
R30
Instruction decoder
R31
registers
56
R0 thru R15
• Only registers in the range R16 to R31 can be loaded
immediately. We cannot load a constant into the registers
R0 to R15 directly. It would have to be loaded into a valid
register first then copied. To load the value of 10 into
register zero (R0):
R0  10
We decompose this operation into primary operations:
R16  10
R0  R16
Code:
LDI R16,10 ; Set R16 to value of 10
MOV R0, R16 ; Copy contents of R16 to R0
57
• INC Rd
– Rd = Rd + 1
• Example:
– INC R25
• R25 = R25 + 1 R0
ALU R1
R2
…
• DEC Rd SREG: I T H S V N Z C
R15
– Rd = Rd - 1 CPU R16
R17
• Example:
…
PC
– DEC R23 Instruction decoder

R30
R31
• R23 = R23 - 1 Instruction Register
registers
58
Data Address Space
Address Name Address Name Address Name
I/O Mem. I/O Mem. I/O Mem.
$00 $20 TWBR $16 $36 PINB $2B $4B OCR1AH
$01 $21 TWSR $17 $37 DDRB $2C $4C TCNT1L
$02 $22 TWAR $18 $38 PORTB $2D $4D TCNT1H
$03 $23 TWDR $19 $39 PINA $2E $4E TCCR1B
$04 $24 ADCL $1A $3A DDRA $2F $4F TCCR1A
$05 $25 ADCH $1B $3B PORTA $30 $50 SFIOR
$06 $26 ADCSRA $1C $3C EECR OCDR
$07 $27 ADMUX $1D $3D EEDR $31 $51 General RAM EEPROM Timers
OSCCAL
$08 $28 ACSR $1E $3E EEARL $32 $52 Purpose
TCNT0
$09 $29 UBRRL $1F $3F PROGRAM
EEARH $33 $53 Registers
TCCR0
$0A $2A UCSRB UBRRCROM $34 $54 MCUCSR
$20 $40
$0B $2B UCSRA UBRRH $35 $55 MCUCR
Program CPU
$0C $2C UDR $21 $41 WDTCR $36 $56 TWCRData
$0D $2D SPCR $22 $42 ASSR Bus
$37 $57 SPMCRBus address bus
$0E $2E SPSR $23 $43 OCR2 $38 $58 TIFR data bus
control bus
$0F $2F SPDR $24 $44 TCNT2 $39 $59 TIMSK Data
$10 $30 PIND $25 $45 TCCR2 $3A $5A GIFR
$11 $31 DDRD 8 bit
$26 $46 ICR1L $3B $5B GICR
Bus
Data Address
$12 $32 PORTD $27R0 $47 ICR1H $3C $5C OCR0
Space
$13 $33 PINC $28R1 $48 OCR1BL $3D $5D SPL
$14
$0000 $34 DDRC $29R2 $49 OCR1BH $3E $5E SPH Interrupt Other
$0001 $35
$15 General
PORTC OSC Ports
$2A $4A OCR1AL $3E $5E SREG Unit Peripherals
...
Purpose
...
Registers R31
$001F I/O Address I/O
$0020 Example:
TWBR
TWSR
$00Add contents of Example:
$01
location 0x90
Storeto0x53
contents of location
into the 0x95 and
SPH register.
PINS Thestore
Standard I/O Example:
the result in What does 0x313.
location the following
address
LDS
STS ofinstruction
SPH
(Load
(Storedirect
directdo?
is 0x5E
from data
to data space)
space)
Example: Write a program that stores 55 into location 0x80 of 0x80
RAM.of RAM
...
...
Registers Example: Write a program that copies the contents of location

$005F LDS
into
SPH
SREG R20,2
$3E
Solution:
location
$3F
0x81.
$0060 LDS Rd, addr ;[addr]=Rd
STS addr,Rd ;Rd = [addr]
General LDS R20, 0x90 Solution:;R20 = [0x90]
purpose Solution:
Answer:
...
RAM
LDS R20,
LDI R21, 55
0x95 LDI =;R21
Example:
;R20 R20,= 0x53
55 [0x95] ;R20 = 0x53
(SRAM) Solution:
It copies
ADD the contents
R20, R21 of R2
STSinto R20;= asR20
;R20
0x5E, 2 is+ the
R20 R21address
;SPHof= R2.
R20
STS 0x80, R20
LDS R20, 0x80 LDS ;[0x80] =
;R20
R1, R20 =
= [0x80]
0x60
STS 0x60,R15 55
; [0x60] = R15
STS 0x313, R20 ;[0x313] = R20
STS 0x81, R20 ;[0x81] = R20 = [0x80]
$FFFF
59
Data Address Space
General RAM EEPROM Timers
Purpose
PROGRAM
Registers
ROM
Program CPU Data

Bus Bus address bus
data bus
control bus
Data
8 bit Bus
Data Address
R0
Space
Example:
R1 Write a program that adds the contents of the PINC IO register to the
R2
$0000 Other
$0001 General the result inInterrupt
contents of PIND and storesOSC location 0x90Ports
of the SRAMPeripherals
Unit
...
Purpose OUT
IN (IN(OUT toIO
from IOlocation)
location)
...
Registers R31
$001F I/O Address I/O
$0020 TWBR Solution:
$00
OUT IOAddr,Rd
PINS
IN Rd,IOaddress of;[addr]=Rd
Using Names;Rd = registers
[addr]
TWSR $01
Standard I/O IO
...
...
Registers
SPH
IN
$3E
R20,PINC ;R20 = PINC
$005F SREG $3F
$0060
IN R21,PIND Example:
;R21 = PIND
General Example:
purpose
...
RAM ADD R20,R21 ;R20 SPH,R12

OUT = R20 + R21;OUT 0x3E,R12
(SRAM) OUT
IN R1,0x3F,R12
0x3F ;SREG
;R1 = R12
= SREG
STS 0x90,R20 ;[0x90]
IN = R20
R15,SREG ;IN R15,0x3F
OUT 0x3E,R15 ;R17
IN R17,0x3E ;SPH= =SPH
R15
$FFFF
60
IN vs LDS
The IN instruction has the following advantages:
1. The CPU executes the IN instruction faster than LDS ( the
IN instruction lasts 1 MC, whereas LDS lasts 2 MCs)
2. The IN is a 2-byte instruction, whereas LDS is a 4-byte
instruction. This means that the IN instruction occupies less
code memory.
3. When we use the IN instruction, we can use the names of
the I/0 registers instead of their addresses.
4. The IN instruction is available in all of the AVRs, whereas
LDS is not implemented in some of the AVRs.
Notice that in using the IN instruction we can access only

the standard I/0 memory, while we can access all parts of
the data memory using the LDS instruction.
61
Arithmetic instructions and SREG
Example: LDI R20,0x54
LDI R25,0xC4
ADD R20,R25
C CMSB H
Note:
• V = C  CMSB
• S = N  V (S is real sign of the result)
• Z = 1 if the result is zero, 0 otherwise
62
Status Register (SREG)
SREG: I T H S V N Z C
Carry
Interrupt oVerflow Zero
Temporary Negative
Sign
Data Address
Half carry N+V Space
Example:Show
Example:
Example:
Example: Showthe
Show
Show thestatus
the
the statusof
status
status ofthe
of
of theC,
the
the C,H,
C,
C, H,and
H,
H, and$0000
and
and Zflags
ZZ
Z flagsafter
flags
flags afterthe
after
after theaddition
the
the subtraction
subtraction
addition of
of of 0x23
of
0x9C
0x380x9C
0x73
from0x64
from
and
and 0x9C
0xA5
0x52
0x2F in in
ininthethe
the
the following
following
following
following instructions: $0001 General
instructions:
instructions:
instructions: Purpose
...
LDI LDI LDI 0x38
LDI
R16, R20, 0x9C
R20,
R20, 0x9C
0xA5
0x52
;R16 = 0x38 Registers
R0 $001F IO Address
ALU LDI LDI 0x2F
LDI
LDI
R17, R21,
R21,
R21, 0x9C
0x23
0x73
R1 0x64
;R17 = $0020
0x2F TWBR $00
TWSR $01
R2 Standard IO
ADD SUB R17R20,
SUB
ADD
R16, R20, R21
R20, R21;add R17;add
R21 ;subtract
;subtract
R21 toR21
to Registers
R16 R21 from R20
R20from R20
...
...
…
SPH $3E
SREG: I T H S V N Z C $005F
Solution:
Solution:
Solution: R15
SREG $3F
Solution: 11
CPU - $23
$52
$9C
$A5
$38
$9C
$73
0101
R16
0011
1001
0111
0010
10011100
1010 1100
0101
1000
R17 0011
$0060
General
purpose
...
+-- +$64
$9C
$2F 10010100
0010
0110 1100
0011
1111 RAM
$DF 1101 1111 R20 = $DF
…
PC $00
$82 1 0000
$67 0000
1000
0110 0000
0010R20 = 00 R20
0111 R20
R16 = $00
=(SRAM)
$82
0x67
$100 0000
C = 1 because R21 is bigger than R20 and there is a borrow from D8 bit.
C
CC===100because
becausethere
because R21 is
R21 is not
isnot bigger
bigger
a carry
R30 than R20
than
beyond R20D7
the and
and there is
there
bit. is no
no borrow
borrow from
from D8
D8 bit.
bit.
Z
C = 0 because
decoderthe
thereR20 hascarry
is no a value otherthe
beyond than
D7zero after the subtraction.
Instruction
ZZ =
H == 011 because
because
because the R20
the
thereR20 iscarry
is ahaszero after
a value
from the
other
R31 from than
D3 0bit.
the subtraction.
to theafter the subtraction.
D4 bit.
H = 1 because there is a borrowcarry from D4D3
the totoD3.
the D4 bit.
H
ZH =
= 0
0 because
because there
there is
is no
no borrow
borrow from
from D4
D4 to
to D3.
D3.
Z = 0 because the R16 (the result) has a value 0other
= 1 because
Instruction Register the R20 (the result)
registers
has a value in it than
after 0the addition.
after the addition.
$FFFF
63
Writing Immediate Value to SRAM
• You cannot copy immediate value directly into
SRAM location in AVR.
• This must be done via GPRs
• Example: The following program adds content of
location 0x220 to location 0x221
64
Exercise
Implement the program that calculates 19 + 95 +
5 on AVR Studio.
Use debug and watch the change of the respective

registers as you step over through the program.
Watch Contents of R16 and check if answer is

correct.
65
Example 2-1
Write the program in AVR Studio to verify that
Note: do not forget to add at the beginning of the program:

.include "M32DEF.inc"
66
Example 2- 2
Verify using AVR Studio
67
Example 2-3
Write a program to get data from the PINB and send it to the
I/O register of PORT C continuously.
Solution:
AGAIN:
IN R16, PINB ; bring data from Port B into R16
OUT PORTC,R16 ; send it to Port C
JMP AGAIN ; keep doing it forever
Example 2-4
Write a simple program to toggle the I/O register of PORT B
continuously forever.
Solution:
LDI R20,0x55 ; R20 = 0x55
OUT PORTB,R20 ; move R20 to Port B SFR (PORTB = 0x55)
L1:
COM R20 ; R20 = one's complement of old R20
OUT PORTB,R20 ; move R20 to Port B SFR
JMP L1 ; repeat forever (see Chapter 3 for JMP)
68
Example 2-5
Write the program in AVR Studio to verify that The Z flag is the
one when the result is zero. Verify:
Note: do not forget to add at the beginning of the program:

.include "M32DEF.inc"
69
Example 2-6
70
Example 2-7
71
Example 2-8
72
Topics

73
Reasons for using assembly
• More efficient use of computing power and
memory
• Closer to the hardware
• If mass production is the goal, then there will be

money saving by going to smaller cheaper parts
74
The AVR Assembler
• We use the AVRASM2 assembler that comes
with AVR studio.
• The Assembler performs the conversion from
English mnemonics to opcodes that are
programmed into the microcontroller.
• C compilers generate assembly language
mnemonics that are then assembled by an
assembler.
• Much confusion arises when one does not have
a conceptual understanding of the different
assembly phases.
75
Structure of Assembly language
• An Assembly language program consists of, among other
things, a series of lines of Assembly language
instructions.
• An Assembly language instruction consists of a
mnemonic, optionally followed by one or two operands.
• The operands are the data items being manipulated, and
the mnemonics are the commands to the CPU, telling it
what to do with those items.
• An Assembly language instruction consists of four fields:

[Label:] mnemonic [operand(s)] [;comment]
Note: Brackets indicate that a field is optional and not all lines have them.
76
• Label field
– Optional.
– Labels are used to identify memory locations in the programs
and data areas.
– Must starts with a letter (A-Z or a-z) and can be followed by
letters, digits, or special symbols (_)
– Can start from any column, it ended with ":".
• Comment field
– Optional.
– Explain the function of a single or a group of instructions
– For programmer - not for assembler or processor.
– Ignored by assembler and are not converted to machine code.
– Can improve a program readability - very important in assembly
– Any line starts with a ";" is a comment. 77
• Mnemonic field
– Mnemonic (or Opcode) is the operation and separated
from the label by at least one space.
– Opcode instructs the processor to do a sequence of
operations.
– converted to machine code.
• Operand(s) field
– Operands follow the opcode and is separated from the
opcode by at least one space
– Operands are separated by commas (if there is more than
one operand)
Assembler instructions or directives are not case sensitive.

78
Assembly language
Assembly language consists of, instructions referred to as
mnemonics, directives and labels.
.INCLUDE "M32DEF.INC" Directive
LDI R16, HIGH(RAMEND)
OUT
Mnemonic
SPH, R16
LDI R16, LOW(RAMEND)
OUT SPL, R16 ; initialize stack point
SBI DDRC, 0 Comment
HERE: Label
SBI PORTC, 0 ; set bit 0 of DDRC
CALL DELAY ; call DELAY subroutine
CBI PORTC, 0
CALL DELAY
RJMP HERE
DELAY:
LDI R20, 255
DL1: DEC R20
BRNE DL1
RET
79
Program 2-1: Sample of an Assembly Language Program
;; Program2_1.asm: The first AVR Assembly program that
; adds some data and stores SUM in SRAM location 0x300.
;; Created: 07/20/2017 07:26:35
; Author : Sepehr Naimi ;
.EQU SUM = 0x300 ; SRAM loc $300 for SUM
.ORG 0 ; start at address 0
LDI R16, 0x25 ; R16 = 0x25
LDI R17, $34 ; R17 = 0x34
LDI R18, 0b00110001 ; R18 = 0x31
ADD R16, R17 ; add R17 to R16: R16 = R16 + R17
ADD R16, R18 ; add R18 to R16: R16 = R16 + R18
LDI R17, 11 ; R17 = 0x0B
ADD R16, R17 ; add R17 to R16
STS SUM, R16 ; save the SUM in loc $300: S[$300] = R16
HERE: JMP HERE ; stay here forever
80
Assembling an AVR program
❑Assembler
EDITOR
PROGRAM
Assembly
myfile.asm
ASSEMBLER assembler
PROGRAM
Machine
myfile.eep myfile.hex myfile.map myfile.lst myfile.obj Language
DOWNLOAD TO DOWNLOAD TO
AVR’s EEPROM AVR ’s FLASH
• The asm file is also called the source file and must have the “asm” extension, this file is
created with a text editor.
• The assembler converts the asm file’s Assembly language instructions into machine
language and provides the obj (object) file.
• The object file has the “obj” extension. The object file is used as input to a simulator or
an emulator. 81
Map file and List file
• The map file shows the labels defined in the program together
with their values.
• The lst (list) file, which is optional, is very useful to the

programmer. The list shows the binary and source code; it also
shows which instructions are used in the source code, and the
amount of memory the program uses. See Figure 2-12.
82
Figure 2-12. List File of Program 2-1
83
Flash memory and PC register
00 E205
E205
LDI R16, 0x25 01 E314
LDI R17, $34 02 E321
LDI R18, 0x31
03 0F01
ADD R16, R17
ADD R16, R18 04 0F02
LDI R17, 11 0516-bit
E01B
ADD R16, R17
06 0F01
STS SUM, R16
HERE:JMP HERE 07 9300
9300
08 0300
0300 RAM EEPROM Timers
09 940C
940C
PROGRAM
0A
Flash0009
0009
ROM ALU
16bit
PC: 3
0
9
1
5
2
A
7
4
8
B
6 Data
16bit CPU Bus
Instruction dec.
Program
Bus
Interrupt Other
OSC Ports
Unit Peripherals
I/O
PINS
84
85
86
Assembler Directives
87
Pre-compiler Directives
Directive cseg dseg eseg Note:

.DB   .DEF Symbol = Register
.EQU Symbol = expression
.DW   .SET Symbol = expression
.BYTE 
❑ Example:
.DSEG
var1 : .BYTE 1 ; reserve 1 byte to var1
table: .BYTE 15 ; reserve 15 bytes
.CSEG
LDI R30,low(var1) ; Load Z register low: R30 = ZL
LDI r31,high(var1) ; Load Z register high: R31 = ZH
LD R1,Z ; Load VAR1 into register 1
90
91
92
93
94
95
96
97
98
99
100
101
.EQU and .SET
• .EQU name = value
– Example:
.EQU COUNT = 0x25
LDI R21, COUNT ;R21 = 0x25
LDI R22, COUNT + 3 ;R22 = 0x28
• .SET name = value

– Example:
.SET COUNT = 0x25
LDI R22, COUNT + 3 ;R22 = 0x28
.SET COUNT = 0x19
102
.INCLUDE
• .INCLUDE "filename.ext"
M32def.inc
.equ SREG = 0x3f
.equ SPL = 0x3d
.equ SPH = 0x3e
....
.equ INT_VECTORS_SIZE = 42 ; size in words
Program.asm
.INCLUDE "M32DEF.INC"
LDI R20, 10
OUT SPL, R20
103
.ORG
• .ORG address
00 E205
01 0000
Program.asm 02 0000
.ORG 0 03 0000
LDI R16, 0x25 04 0000

.ORG 0x7
assembler 05 0000
LDI R17, 0x34 06 0000
LDI R18, 0x31 07 E314
08 E321
09 0000
0A 0000
104
Arithmetic and logic expressions with constant values
• We can define constant values using .EQU.
• The AVR Studio IDE supports arithmetic operations between expressions.
Ex 1: .EQU ALFA = 50
.EQU BETA = 40
LDI R23,ALFA ;R23 = ALFA = 50
LDI R24, ((ALFA-BETA)*2)+9 ; R24 = ((50-40)*2)+9 = 29
Ex2 :
.EQU C1 = 0x50
.EQU C2 = 0x10
.EQU C3 = 0x04
LDI R21, (C1&C2) | C3 ;R21=(0x50 & 0x10) | 0x04 = 0x10 | 0x04= 0x14
Ex 3:
LDI R16,0b00000111<<1 ;R16 = 0b00001110
Some operators in AVR assembler
Flag names in m32def.inc
I T H S V N Z C
; SREG - Status Register

.equ SREG_C = 0 ;carry flag
.equ SREG_Z = 1 ;zero flag
.equ SREG_N = 2 ;negative flag
.equ SREG_V = 3 ;2's complement overflow flag
.equ SREG_S = 4 ;sign bit
.equ SREG_H = 5 ;half carry flag
.equ SREG_T = 6 ;bit copy storage
.equ SREG_I = 7 ; global interrupt enable
HIGH( ) and LOW( ) functions
Assembler Preprocessor
109
Topics

110
How to speed up the CPU
• Increase the clock frequency
– More frequency ➔ More power consumption & more
heat
– Limitations
• Change the architecture
– Pipelining
– RISC
111
Fetch and execute
• Old Architectures
00 E205
01 E314
02 E321
Instruct 4
03 0F01
Instruct 3
04 0F02
Instruct 2
0516-bit
E01B
Instruct 1
06 0F01
07 9300
08 0300 RAM EEPROM Timers
Fetch
09 940C
PROGRAM
0A
Flash0009
ROM ALU
PC: Data
CPU Bus
Execute
Instruction dec.
Program
Bus
Interrupt Other
OSC Ports
Unit Peripherals
I/O
PINS
112
Pipelining
• Pipelining
00 E205
01 E314
02 E321
Instruct 4 03 0F01
Instruct 3 04 0F02
Instruct 2 0516-bit
E01B
Instruct 1 06 0F01
07 9300
08 0300 RAM EEPROM Timers
Fetch 09 940C
PROGRAM
0A
Flash0009
ROM ALU
PC: Data
CPU Bus
Execute Program Instruction dec.
Bus
Interrupt Other
OSC Ports
Unit Peripherals
I/O
PINS
113
Changing the architecture
RISC vs. CISC
• CISC (Complex Instruction Set Computer)
– Put as many instruction as you can into the CPU
• RISC (Reduced Instruction Set Computer)
– Reduce the number of instructions, and use your
facilities in a more proper way.
114
RISC architecture
• Feature 1
– RISC processors have a fixed instruction size. It makes the
task of instruction decoder easier.
• In AVR the instructions are 2 or 4 bytes.
– In CISC processors instructions have different lengths
• E.g. in 8051
– CLR C ; a 1-byte instruction
– ADD A, #20H ; a 2-byte instruction
– LJMP HERE ; a 3-byte instruction
• Feature 2: reduce the number of instructions

– Pros: Reduces the number of used transistors
– Cons:
• Can make the assembly programming more difficult
• Can lead to using more memory
115
RISC architecture (2/3)
• Feature 3: The limited number of instructions  limit the
addressing mode
– Advantage
• hardwiring
– Disadvantage
• Can make the assembly programming more difficult
• Feature 4: Load/Store
more than 95% of instructions are executed with only one clock
cycle (1 MC) and the rest is executed with 2 MCs (Ex: Load/Store).
LDS R20, 0x200

LDS R21, 0x220
ADD R20, R21
STS 0x230, R20
116
RISC architecture (3/3)
• Feature 5: RISC processors have separate
buses for data and code (Harvard architecture).
• Feature 6: RISC instructions due to the small

set of instructions, are implemented using the
hardwire method.Hardwiring of RISC instructions
takes no more than 10% of the transistors.
• Feature 7
– RISC processors have at least 32 registers. Decreases
the need for stack and memory usages.
• In AVR there are 32 general purpose registers (R0 to R31)
117

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www. Micro Digital Ed.

The AVR microcontroller

❖ Assembly Language Programming

❖ Pipelining and RISC architecture

Clears all the

• DDRx - Data Direction Register for Port x (x = A, B, C, D).

Outside the Inside the

❖ Assembly Language Programming

❖ Pipelining and RISC architecture

Harvard Architecture diagram

▪ It has 32 8-Bit general purpose registers.

▪ Mostly instruction Execute in Single clock cycle. Which makes it

▪ AVR was designed for efficient execution of compiled C code.

▪ AVR is a family of 8-bit microntrollers with a large range of variants

• Native data size is 8 bits (1 byte).

I/O and special functions

3. 32KB Flash Program Memory

• Each memory type has its own address space:

Flash Memory Layout

Chip Bytes Chip Bytes Chip Bytes

ATmega8 512 ATmega16 512 ATmega32 1024

ATmega640 4096 ATmega1280 4096 ATmega2560 4096

• Special Function Registers

• Internal data SRAM

• Internal data SRAM is widely used for storing data and

• Each location of the SRAM can be accessed directly by

• Each location is 8 bit wide and can be used to store any

• Size of SRAM is vary from chip to chip, even among

Little Endian 0x100 0x101 0x102 0x103

The fast-access Register file

“Six of the 32 registers can be

❑ In the different addressing modes these address registers have

Program counter (PC, 16-bit)

➢ Holds address of next program instruction to

➢ Automatically incremented when the ALU

❑ The ISA is the interface between hardware and software.

• This section describes the various addressing modes

• To simplify, not all figures show the exact location of the

Direct Register – Single Register Addressing

Two-Register Direct Addressing

I/O Direct Addressing

Data Direct Addressing

Data Indirect with Displacement

Data Indirect Addressing

Data Indirect Addressing with Pre-decrement

Data Indirect Addressing with Post-increment

st, std, sts lpm

ld, ldd, lds GPRs mov, movw

Mnemonics Operands Operation Words Clocks Note

STD Z+q, Rr (Z+q)  Rr 1 2

Note: A is an I/O Address, SP is Stack Pointer

LDI R16, 19 ;R16 = 19

LDI R16, 19 ;R16 = 19

– DEC R23 Instruction decoder

Registers Example: Write a program that copies the contents of location

Program CPU Data

RAM ADD R20,R21 ;R20 SPH,R12

Notice that in using the IN instruction we can access only