__________________________________________________________________________________

AND GATE using IF ELSE Ladder

__________________________________________________________________________________

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entitylogic_gates is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
Y : out STD_LOGIC);
endlogic_gates;

architectureBehavioral of logic_gates is
begin
P1: PROCESS (A,B)
BEGIN
IF A = '0' AND B = '0' THEN
Y <= '0' ;
ELSIF A = '0' AND B = '1' THEN
Y <= '0' ;
ELSIF A = '1' AND B = '0' THEN
Y <= '0' ;
ELSE
Y <= '1';
END IF;
END PROCESS P1;
endBehavioral;
__________________________________________________________________________________
AND GATE using IF ELSE

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entitylogic_gates is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
Y : out STD_LOGIC);
endlogic_gates;

architectureBehavioral of logic_gates is

begin
P1: PROCESS (A,B)
BEGIN

IF A = '1' AND B = '1' THEN

Y <= '1' ;

ELSE

Y <= '0';

END IF;

END PROCESS P1;

endBehavioral;
__________________________________________________________________________________
AND GATE using WHEN ELSE

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entitylogic_gates is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
Y : out STD_LOGIC);
endlogic_gates;

architectureBehavioral of logic_gates is

begin

Y <= '1' when A = '1' AND B = '1' ELSE

'0';
endBehavioral;
__________________________________________________________________________________
AND GATE using WHEN ELSE

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entitylogic_gates is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
Y : out STD_LOGIC);
endlogic_gates;

architectureBehavioral of logic_gates is

begin

Y <= '0' when A = '0' AND B = '0' ELSE

'0' when A = '0' AND B = '1' ELSE
'0' when A = '1' AND B = '0' ELSE
'1';
endBehavioral;
 HALF ADDER using DATA FLOW (simple Logical Equations)

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity HALD_ADDER is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
S : out STD_LOGIC;
C : out STD_LOGIC);
end HALD_ADDER;

architectureBehavioral of HALD_ADDER is

begin

S <= A XOR B;

C <= A AND B;

endBehavioral;
 HALF ADDER using BEHAVIOURAL MODELLING (if else ladder)

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity HALD_ADDER is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
S : out STD_LOGIC;
C : out STD_LOGIC);
end HALD_ADDER;

architecture Behavioral of HALD_ADDER is

begin
P1: PROCESS ( A, B)
BEGIN
IF A ='0' AND B ='0' THEN
S <= '0';
C <= '0';
ELSIF A ='0' AND B ='1' THEN
S <= '1';
C <= '0';
ELSIF A ='1' AND B ='0' THEN
S <= '1';
C <= '0';
ELSE
S <= '0';
C <= '1';
END IF ;
END PROCESS P1;

End Behavioral;
 FULL ADDER using DATA FLOW (simple Logical Equations)

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity FULL_ADDER is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
Cin : in STD_LOGIC;
S : out STD_LOGIC;
C : out STD_LOGIC);
end FULL_ADDER;

architecture Behavioral of FULL_ADDER is

begin

S <= A XOR B XOR Cin ;

c <= (( A AND B) OR (B AND Cin) OR (A AND Cin));

end Behavioral;
 FULL ADDER using BEHAVIOUR MODELLING (if else ladder)
**********************************************************************************
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity FULL_ADDER is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
Cin : in STD_LOGIC;
S : out STD_LOGIC;
C : out STD_LOGIC);
end FULL_ADDER;

architecture Behavioral of FULL_ADDER is

begin
P1 : PROCESS ( A,B,Cin)
BEGIN
IF A ='0' AND B ='0' AND Cin ='0' THEN
S <= '0';
C <= '0';
ELSIF A ='0' AND B ='0' AND Cin ='1' THEN
S <= '1';
C <= '0';
ELSIF A ='0' AND B ='1' AND Cin ='0' THEN
S <= '1';
C <= '0';
ELSIF A ='0' AND B ='1' AND Cin ='1' THEN
S <= '0';
C <= '1';
ELSIF A ='1' AND B ='0' AND Cin ='0' THEN
S <= '1';
C <= '0';
ELSIF A ='1' AND B ='0' AND Cin ='1' THEN
S <= '0';
C <= '1';
 ELSIF A ='1' AND B ='1' AND Cin ='0' THEN
S <= '0';
C <= '1';

ELSE
S <= '1';
C <= '1';
END IF;
END PROCESS P1;
End Behavioral;
 HALF SUBTRACTOR using DATA FLOW ( Logical Equations)
**********************************************************************************
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity HALF_SUB is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
D : out STD_LOGIC;
BR : out STD_LOGIC);
end HALF_SUB;

architecture Behavioral of HALF_SUB is

begin

D <= A XOR B;
BR <= (NOT A) AND B ;

End Behavioral;
 HALF SUBTRACTOR using BEHAVIOURAL MODELLING (if else ladder)
**********************************************************************************
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity HALF_SUB is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
D : out STD_LOGIC;
BR : out STD_LOGIC);
end HALF_SUB;

architecture Behavioral of HALF_SUB is

begin
P1: PROCESS (A,B)
BEGIN
IF A ='0' AND B ='0' THEN
D <='0';
BR <='0';
ELSIF A ='0' AND B ='1' THEN
D <='1';
BR <='1';
ELSIF A ='1' AND B ='0' THEN
D <='1';
BR <='0';
ELSE
D <='0';
BR <='0';

END IF;
END PROCESS P1;
End Behavioral;

FULL SUBTRACTOR using DATA FLOW MODELLING (Logical Equations)

**********************************************************************************
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity FL_SB is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
Bin : in STD_LOGIC;
D : out STD_LOGIC;
Bout : out STD_LOGIC);
end FL_SB;

architecture Behavioral of FL_SB is

begin

D <= A XOR B XOR Bin;

Bout <= ( (NOT A AND B) OR (NOT A AND Bin) OR (B AND Bin));

End Behavioral;
 FULL SUBTRACTOR using BEHAVIOURAL MODELLING (if else ladder)
**********************************************************************************
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity FL_SB is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
Bin : in STD_LOGIC;
D : out STD_LOGIC;
Bout : out STD_LOGIC);
end FL_SB;

architecture Behavioral of FL_SB is

begin
P1 :PROCESS (A,B,Bin)
Begin
IF A ='0' AND B ='0' AND Bin ='0' THEN
D <= '0';
Bout <= '0';
ELSIF A ='0' AND B ='0' AND Bin ='1' THEN
D <= '1';
Bout <= '1';
ELSIF A ='0' AND B ='1' AND Bin ='0' THEN
D <= '1';
Bout <= '1';
ELSIF A ='0' AND B ='1' AND Bin ='1' THEN
D <= '0';
Bout <= '1';
ELSIF A ='1' AND B ='0' AND Bin ='0' THEN
D <= '1';
Bout <= '0';
 ELSIF A ='1' AND B ='0' AND Bin ='1' THEN
D <= '0';
Bout <= '0';

ELSIF A ='1' AND B ='1' AND Bin ='0' THEN

D <= '0';
Bout <= '0';

ELSE
D <= '1';
Bout <= '1';

END IF;
END PROCESS P1;

End Behavioral;
 8:1 MULTIPLEXER using DATA FLOW MODELLING ( When Else)
**********************************************************************************
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity MUX_81 is
Port ( D : in STD_LOGIC_VECTOR (7 downto 0);
SEL : in STD_LOGIC_VECTOR (2 downto 0);
Y : out STD_LOGIC);
end MUX_81;

architecture Behavioral of MUX_81 is

begin

Y <= D(0) WHEN SEL = "000" ELSE

D(1) WHEN SEL = "001" ELSE
D(2) WHEN SEL = "010" ELSE
D(3) WHEN SEL = "011" ELSE
D(4) WHEN SEL = "100" ELSE
D(5) WHEN SEL = "101" ELSE
D(6) WHEN SEL = "110" ELSE
D(7) ;

End Behavioral;
 8:1 MULTIPLEXER using DATA FLOW MODELLING (With Select)
**********************************************************************************
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity MUX_81 is
Port ( D : in STD_LOGIC_VECTOR (7 downto 0);
SEL : in STD_LOGIC_VECTOR (2 downto 0);
Y : out STD_LOGIC);
end MUX_81;

architecture Behavioral of MUX_81 is

begin

WITH SEL SELECT

Y <= D(0) WHEN "000" ,

D(1) WHEN "001" ,
D(2) WHEN "010" ,
D(3) WHEN "011" ,
D(4) WHEN "100" ,
D(5) WHEN "101" ,
D(6) WHEN "110" ,
D(7) WHEN OTHERS ;

End Behavioral;
 8:1 MULTIPLEXER using Behavioural Modelling (if elseif ladder)
**********************************************************************************

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity MUX_81 is
Port ( D : in STD_LOGIC_VECTOR (7 downto 0);
SEL : in STD_LOGIC_VECTOR (2 downto 0);
Y : out STD_LOGIC);
end MUX_81;

architecture Behavioral of MUX_81 is

begin
P1 : PROCESS (SEL)
BEGIN
IF SEL = "000" THEN
Y <= D(0);
ELSIF SEL = "001" THEN
Y <= D(1);
ELSIF SEL = "010" THEN
Y <= D(2);
ELSIF SEL = "011" THEN
Y <= D(3);
ELSIF SEL = "100" THEN
Y <= D(4);
ELSIF SEL = "101" THEN
Y <= D(5);
ELSIF SEL = "110" THEN
Y <= D(6);
 ELSE
Y <= D(7);
END IF;
END PROCESS P1;
End Behavioral;
8:1 MULTIPLEXER using Behavioural Modelling (Case statement)
**********************************************************************************
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity MUX_81 is
Port ( D : in STD_LOGIC_VECTOR (7 downto 0);
SEL : in STD_LOGIC_VECTOR (2 downto 0);
Y : out STD_LOGIC);
end MUX_81;

architecture Behavioral of MUX_81 is

begin

P1 : PROCESS (SEL)

BEGIN
CASE SEL IS

WHEN "000" => Y<= D(0);

WHEN "001" => Y<= D(1);
WHEN "010" => Y<= D(2);
WHEN "011" => Y<= D(3);
WHEN "100" => Y<= D(4);
WHEN "101" => Y<= D(5);
WHEN "110" => Y<= D(6);
WHEN OTHERS => Y <= D(7);

END CASE;
 END PROCESS P1;
End Behavioral;

1:8 DEMULTIPLEXER using Data Flow Modelling (When Else)

**********************************************************************************
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity DMUX_18 is
Port ( D : in STD_LOGIC;
SEL : in STD_LOGIC_VECTOR (02 downto 0);
Y : out STD_LOGIC_VECTOR (07 downto 0));
end DMUX_18;

architecture Behavioral of DMUX_18 is

begin
Y(0) <= D WHEN SEL = "000" ELSE '0';
Y(1) <= D WHEN SEL = "001" ELSE '0';
Y(2) <= D WHEN SEL = "010" ELSE '0';
Y(3) <= D WHEN SEL = "011" ELSE '0';
Y(4) <= D WHEN SEL = "100" ELSE '0';
Y(5) <= D WHEN SEL = "101" ELSE '0';
Y(6) <= D WHEN SEL = "110" ELSE '0';
Y(7) <= D WHEN SEL = "111" ELSE '0';

End Behavioral;
 1:8 DEMULTIPLEXER using Behavioural Modelling (Case statement)
**********************************************************************************
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity NEW1 is
Port ( D : in STD_LOGIC;
SEL : in STD_LOGIC_VECTOR (02 downto 0);
Y0 : out STD_LOGIC;
Y1 : out STD_LOGIC;
Y2 : out STD_LOGIC;
Y3 : out STD_LOGIC;
Y4 : out STD_LOGIC;
Y5 : out STD_LOGIC;
Y6 : out STD_LOGIC;
Y7 : out STD_LOGIC);
end NEW1;

architecture Behavioral of NEW1 is

begin
PI: PROCESS (SEL)
BEGIN
CASE SEL IS
WHEN "000" => Y0 <= D;
WHEN "001" => Y1 <= D;
WHEN "010" => Y2 <= D;
WHEN "011" => Y3 <= D;
WHEN "100" => Y4 <= D;
 WHEN "101" => Y5 <= D;
WHEN "110" => Y6 <= D;
WHEN OTHERS => Y7 <= D;
END CASE;
END PROCESS PI;
End Behavioral;

D Flip Flop using Behavioural Modelling

**********************************************************************************
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity D_FF is
Port ( D : in STD_LOGIC;
CLK : in STD_LOGIC;
RESET : in STD_LOGIC;
Q : out STD_LOGIC);
end D_FF;

architecture Behavioral of D_FF is

begin
-- D-FF USING BEHAVIOURAL (IF-ELSE)

P1 : PROCESS (RESET, CLK)

BEGIN
IF RESET ='1' THEN
Q<= '0' ;
ELSIF CLK'EVENT AND CLK = '1' THEN
Q<= D;
END IF;
END PROCESS P1;

End Behavioral;
 T Flip Flop using Behavioural Modelling
**********************************************************************************
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity TFF is
Port ( T : in STD_LOGIC;
CLK : in STD_LOGIC;
RESET : in STD_LOGIC;
DOUT : out STD_LOGIC);
end TFF;

architecture Behavioral of TFF is

begin
P1 : PROCESS (T, CLK, RESET)
VARIABLE M : STD_LOGIC := '0' ;

BEGIN
IF (RESET = '1') THEN M := '0';
ELSIF CLK'EVENT AND CLK = '1' THEN
IF (T = '1') THEN M := NOT M;
END IF;
 END IF;
DOUT <= M;

END PROCESS P1;

End Behavioral;

2:4 Decoder using Behavioural Modelling

**********************************************************************************
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity DECODER_2_4 is
Port ( I : in STD_LOGIC_VECTOR (01 downto 0);
Z : out STD_LOGIC_VECTOR (03 downto 0));
end DECODER_2_4;

architecture Behavioral of DECODER_2_4 is

begin
-- 2:4 DECODER USING CASE
PROCESS (I)
BEGIN
CASE I IS
WHEN "00" => Z<= "0001" ;
WHEN "01" => Z<= "0010" ;
WHEN "10" => Z<= "0100" ;
WHEN OTHERS => Z <= "1000";
END CASE;
END PROCESS;

End Behavioral;
 3:8 Decoder using Behavioural Modelling
**********************************************************************************
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity Decoder_8_3 is
Port ( I : in STD_LOGIC_VECTOR (02 downto 0);
Z : out STD_LOGIC_VECTOR (07 downto 0));
end Decoder_8_3;

architecture Behavioral of Decoder_8_3 is

begin
Process (I)
BEGIN
CASE I is
WHEN "000" => Z<= "00000001";
WHEN "001" => Z<= "00000010";
WHEN "010" => Z<= "00000100";
WHEN "011" => Z<= "00001000";
WHEN "100" => Z<= "00010000";
WHEN "101" => Z<= "00100000";
WHEN "110" => Z<= "01000000";
WHEN "111" => Z<= "10000000";
WHEN OTHERS => Z<= "ZZZZZZZZ";

END CASE;
END Process;
End Behavioral;

4:2 Encoder using Behavioural Modelling

**********************************************************************************
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity ENCODER_4_2 is
Port ( DIN : in STD_LOGIC_VECTOR (03 downto 0);
Q : out STD_LOGIC_VECTOR (01 downto 0));
end ENCODER_4_2;

architecture Behavioral of ENCODER_4_2 is

begin
PROCESS ( DIN )
BEGIN
CASE DIN IS

WHEN "0001" => Q <= "00";

WHEN "0010" => Q <= "01";
WHEN "0100" => Q <= "10";
WHEN "1000" => Q <= "11";
WHEN OTHERS => Q <= "ZZ";
END CASE;
END PROCESS ;

End Behavioral;
 8:3 Encoder using Behavioural Modelling
**********************************************************************************
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity ENCODER_8_3 is
Port ( Din : in STD_LOGIC_VECTOR (07 downto 0);
Q : out STD_LOGIC_VECTOR (02 downto 0));
end ENCODER_8_3;

architecture Behavioral of ENCODER_8_3 is

begin
PROCESS(Din)
BEGIN
CASE Din IS

WHEN "00000001" => Q<= "000";

WHEN "00000010" => Q<= "001";
WHEN "00000100" => Q<= "010";
WHEN "00001000" => Q<= "011";
WHEN "00010000" => Q<= "100";
WHEN "00100000" => Q<= "101";
WHEN "01000000" => Q<= "110";
WHEN "10000000" => Q<= "111";
WHEN OTHERS => Q<= "ZZZ";
 END CASE;
END PROCESS;
End Behavioral;

Binary to Gray Code Converter using Data Flow Modelling

**********************************************************************************
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity BIN2GRAY is
Port ( Bin : in STD_LOGIC_VECTOR (03 downto 0);
Gout : out STD_LOGIC_VECTOR (03 downto 0));
end BIN2GRAY;

architecture Behavioral of BIN2GRAY is

begin

Gout(3) <= Bin (3);

Gout(2) <= Bin (3) xor Bin (2);
Gout(1) <= Bin (2) xor Bin (1);
Gout(0) <= Bin (1) xor Bin (0);

End Behavioral;
 4 Bit ALU using Behavioural Modelling
**********************************************************************************
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity ALU4_BIT is
Port ( A : in STD_LOGIC_VECTOR (03 downto 0);
B : in STD_LOGIC_VECTOR (03 downto 0);
Y : out STD_LOGIC_VECTOR (03 downto 0);
SEL : in STD_LOGIC_VECTOR (02 downto 0));
end ALU4_BIT;

architecture Behavioral of ALU4_BIT is

begin
P1: PROCESS (A,B,SEL)
BEGIN
CASE SEL IS

WHEN "000" => Y <= A + B;

WHEN "001" => Y <= A - B;
WHEN "010" => Y <= A AND B;
WHEN "011" => Y <= A OR B;
WHEN "100" => Y <= A XOR B;
WHEN "101" => Y <= A XNOR B;
WHEN "110" => Y <= A NAND B;
WHEN "111" => Y <= A NOR B;
WHEN OTHERS => NULL;

END CASE;
END PROCESS P1;
End Behavioral;