Achieving High Gain Using Negative Resistance

Chembiyan T

Negative resistors have been in use in analog and RF design for many decades in several applications. In
RF circuits, negative resistances are commonly used to compensate for losses in LC oscillators to generate
sustained oscillations and in RF amplifiers to ’cancel’ out the losses incurred in inductors to provide high
gain at the resonant frequency. They also find applications in analog design in amplifiers to achieve high
gain. Low voltage CMOS devices suffer from poor intrinsic gain, making low voltage amplifier design
very challenging. Cascoding is a common technique used to increase the output impedance and thus
achieve high gain, but it is not an option due limited voltage headroom. Multiple stage amplification is
other viable option to achieve high gains but they come with stability problems due to multiple poles in
the amplifier. Negative resistances come in handy where high gains are desired with reasonable headroom
and not involve many stages for amplification. This article discusses and analyses the problem of realizing
high gain using negative resistance and provide intuition to understand such circuits.

I. H IGH GAIN IN CMOS AMPLIFIERS

vo
vo vi
M1 M2 Mn
Mn

M2 gmvi (gmro)n-1ro
(gmro)n-1gmvi ro
vi
M1
(a) (b)

Fig. 1. Achieving high gain using a) Cascode configuration and b) Cascade of common source amplifiers

To understand how it provides high gain amplifiers, we consider the general model of the CMOS
amplifier as a transconductor Gm driving an output resistor Rout . The gain can be expressed as
Av = Gm Rout (1)
To increase the gain of the amplifier, one can either increase the output resistor Rout or the transconductor
Gm . Cascoding is one popular technique used in realizing high gain by boosting the output impedance.
Shown in Fig.1.(a) is a n-tuple cascode amplifier where n devices are stacked on top of each other in
a totem-pole configuration as shown in the figure to realize a large output impedance. The short circuit
transconductance of the amplifier remains the same as that of a single stage common source amplifier, but
the output resistance is much larger and increases exponentially with n (number of stacked devices). The
n-tuple cascode amplifier can be seen as a single common source amplifier followed by n − 1 common
gate amplifiers in cascade. The output impedance gets multiplied by the intrinsic gain of the common gate
stage amplifier at every stage. Each common gate stage multiplies the source resistance by its intrinsic
gain gm r0 , so the final resistance seen at the output stage is ≈ (gm r0 )n−1 r0 . The gain of the amplifier
can be found by expressing the gain as the product of the short circuit transconductance and the output
resistance.
Av = Gm Rout ≈ −gm · (gm r0 )n−1 r0 = −(gm r0 )n (2)
The problem with cascoding to achieve high gain is that, cascode amplifiers need cascode loads to provide
high output impedance. Otherwise the load resistance will end up shunting out the total output resistance
and hence reduce the gain. Stacking devices for high gain results in a reduced voltage swing or said
other wide, to achieve high voltage swings, a large supply voltage is needed. Assuming that each device
requires at least a voltage of Vov to keep the devices in saturation region, the theoretical minimum supply
voltage needed for a proper operation of the n-tuple cascode amplifier is given by
VDD,min ≥ 2nVov +Vswing (3)
where Vswing is the total signal-dependent change in the output voltage in the presence of an input signal.
The higher the gain, the larger the supply voltage required and thus making this technique unsuited for
low voltage designs.
The other approach is to use cascading as shown in Fig.1.(b). This is one of the oldest techniques in high
gain amplifications where high gain is achieved by simply cascading many similar amplifiers till the desired
gain is met. For an n-stage cascaded common source amplifiers, the total output resistance seen at the nth
stage output is r0 which is same as the output resistance at every stage. The short circuit transconductance
however is much higher when measured at the final output stage. For an n-stage cascaded amplifier, the
output transconductance is −(gm r0 )n−1 gm . The overall gain of the cascaded amplifier is given by
Av = Gm Rout = −(gm r0 )n−1 gm r0 = (−gm r0 )n (4)
This approach does not have the problem of reduced voltage swing as the amplifiers can work with lower
output impedances at each stage, A simple double cascode current source will be sufficient to bias each
stage so as to achieve the gain close to Eq.(4). The theoretical minimum supply voltage necessary for the
proper operation of the cascaded amplifier can be shown to be
VDD,min ≥ 3Vov +Vswing (5)
The problem with this technique is that each stage adds a pole and having multiple poles in amplifiers
leads to stability problems which require compensation adding to further complexity and power.
To summarize, cascoding and multi-stage amplification increase the output resistance and output transcon-
ductance respectively to achieve high gain as shown in Fig.1. But as discussed in this section both these
techniques are not well suited for low voltage designs. Using negative impedances to achieve high gain
have been an attractive solution in such cases.

II. H IGH GAIN USING NEGATIVE RESISTANCE

Negative resistance can be used to achieve high gain amplification in case of low voltage designs
without resorting to multi-stage amplifiers. Negative resistance can be used to boost either the transcon-
ductance or the output impedance as shown in Fig.2 to achieve high gain. The transconductance of a
MOS amplifier degenerated by a resistor Rs at the source terminal is given by gm /(1 + gm Rs ), where gm
is the transconductance of the amplifier in a common source configuration. If the resistance is positive,
then the transconductance of the amplifier decreases by the factor 1 + gm Rs . If the resistance is negative,
then by choosing the product gm Rs very close to 1, the transconductance can be increased significantly.
Assuming the MOS amplifier with an output resistance Rout is degenerated by a negative resistance −Rn
as shown in Fig.2.(a), the gain of the amplifier is given by
gm Rout
Av = − =⇒ |Av | >> gm Rout if gm Rn ≈ 1 (6)
1 − gm Rn
 gmRout >> g R
m out vo
1-gmRn vi
vo Rout -Rn
vi
Rout

gmRoutRn >> g R
-Rn m out
Rn-Rout
(a) (b)

Fig. 2. Realizing high gain using negative resistance a) by boosting transconductance and b) by increasing the output resistance.

If the product gm Rn is chosen to be very lose to 1, then the gain of the amplifier can be increased
significantly. For example for gm Rn = 0.95, the gain of the amplifier is given by −20gm Rout , as twenty
fold increase in the gain compared to the common source amplifier.
Similarly by connecting a negative resistance in parallel to the output resistance, the overall output
resistance can be increased by choosing the negative resistance value very close to the output resistance.
Assuming that a negative resistance of value −Rn is connected in parallel to the load resistance as shown
in Fig.2.(b), the gain of the amplifier is given by
gm Rout Rn
Av = − =⇒ |Av | >> gm Rout if Rn ≈ Rout (7)
Rn − Rout
There are many ways in which a negative resistance can be realized. But the popular way of realizing a

vp -2/gm vn

Zin

vp Cn/2
vn
vp vn
C1 C1 -1/gm -1/gm

IB
Cn Cn
(a) (b) Cn=Cgs+Cdb+2Cgd+C1

Fig. 3. a) Circuit realization of a negative resistance and b) its equivalent small signal model.

differential negative resistance is to use a regenerative latch as shown in Fig.3.(a). This implementation
is commonly used in LC oscillators to achieve sustained oscillations. Assuming that the drain nodes of
the MOS devices have a load capacitor C1 , the impedance seen between the drain terminals of the MOS
devices in the regenerative latch shown in the figure can be shown to be
2 2
Zin (s) = − + (8)
gm sCn
where 0.5Cn is the total differential capacitor seen between the two drain terminals and its value can be
shown to be Cn = Cgs +Cdb + 2Cgd +C1 .
III. T RANSCONDUCTANCE BOOSTING USING A NEGATIVE RESISTANCE

VDD
gm1
Gm =
R v R 1-(gm1/gm3)
- out + R
vout
vip vin vi vi Gm
M1 M2

M4 M3 -1/gm3 -1/gm3

I0
(a) (b)

Fig. 4. a) A differential amplifier with Gm boosting using negative resistance, b) its equivalent differential half circuit small signal model

By degenerating a common source differential pair with a cross coupled latch as shown in Fig.4, the
MOS amplifier transconductance can be increased as explained earlier. Neglecting the output resistance
of the MOS devices (gds = 0), the gain of the amplifier is given by
vo gm1 R
Av = = (9)
vi 1 − gm1 /gm3
By choosing gm1 /gm3 very close to 1, the overall gain of the amplifier can be increased manifold. The
transconductance of the device can be expressed as
gm1
Gm = (10)
1 − (gm1 /gm3 )
Fig.5.(a) shows the variation of the transconductance of the amplifier as a function of the negative
transconductance gm3 . If the negative resistance is zero or transconductance gm3 is infinite, then there is no
source degeneration and the transconductance of the amplifier is simply equal to gm1 as shown illustratively
in the same figure. As the value of gm3 is decreased, the transconductance of the amplifier starts to increase
reaching very high values when gm3 → gm1 , eventually reaching infinity when gm1 = gm3 . At this point the
amplifier behaves like an ideal comparator with an infinite gain with a transfer characteristics as shown in
Fig.5.(b). When the transconductance is increased further, the output transconductance changes polarity
as shown in the Fig.5.(a) and the value is still very high when the value of gm3 is still closer to gm1 . The
corresponding amplifier transfer characteristics is shown in Fig.5.(b), where it behaves like a comparator
with an opposite polarity. Eventually as gm3 is reduced to zero, the resistance becomes infinite and thus
the transconductance goes to zero as illustratively shown in the figure.
 Gm → + ∞
Gm vi
vout vout
gm1 Gm = gm1 gm1 gm1
Gm = -1/(gm1+∆)
gm3 << 1 gm3 = 1-∆
1-(gm1/gm3) vi
(1/gm3)=0
vi vi
gm1
gm1
0 Gm → 0
gm3 vout vout
vi
gm1 gm1
Gm → − ∞
gm3 = 1+∆ gm3 >> 1
(1/gm3) = ∞ vi

-1/(gm1-∆)
vi vi

Fig. 5. a) Variation of the amplifier output transconductance Gm as a function of the negative transconductance gm3 and b) the transfer characteristics of the
amplifier for different values of the ratio gm1 /gm3 .

IV. F REQUENCY RESPONSE AND STABILITY

Having studied the low frequency small signal response, the next problem of interest is to study the
high frequency response of the gm boosted amplifier. To understand the frequency response of the gm
boosted amplifier or to appreciate how good or how bad it is, we compare it with two other high gain
amplifier topologies like the cascode amplifier and the two stage amplifier.
The high frequency model of the gm boosted amplifier and the associated pole-zero plot on the s-plane
is shown in Fig.6.(a). The amplifier has two poles, one at the output node and another one at the source
node of input differential pair given by The circuit has a RHP pole at
gm3 − gm1 1
S p1 = & S p2 = − (11)
Cs RCL
Since gm1 is chosen to be slightly less than gm3 , the pole at the source node is a RHP pole close to

jω jω
R CL
vout
vi σ vout σ

-1/RCL gm3-gm1 gm3/Cs CL -1

-1/gm3 Cs Cs vi gmro2CL

(a) (b)

jω
R R vout -1/RC1 σ
vi
C1 CL -1/RCL gm1/Cgd1
(b) gm2/Cgd2

Fig. 6. Differential half circuit and the pole zero plot of a) gm boosted amplifier, b) Cascode amplifier and c) Two stage amplifier.

dc. The pole at the output node is due to the load capacitance. If the amplifier is used in a feedback
configuration driving a capacitive load, the output capacitance can be very high and thus it can create a
low frequency LHP pole.
The circuit also has a zero. When the source impedance blows up, the transconductance tends to zero
and the zero can be found by finding the frequency at which the source impedance blows up to infinity,
which happens when  
1 1 gm3
=− − =⇒ Sz = (12)
sCs gm3 Cs
The circuit has a RHP zero as the degeneration resistor is negative. Since there are two poles, an RHP
pole close to dc and a LHP pole again close to dc if the load capacitor is large and to compound the
problem a RHP zero, that’s a recipe for disaster as they say.
To understand how bad it is, lets compare the frequency response to that of a cascode amplifier. The
cascode amplifier has only one dominant pole at the output node as shown in Fig.6.(b) and the pole
location can be shown to be
1
S p1 = − (13)
gm ro 2CL
The two stage amplifier has two dominant poles at each node of the amplifier as shown in Fig.6.(c) and
the poles are given by
1 1
S p1 = − & S p2 = − (14)
RC1 RCL
C1 here denotes the total output node capacitance at the first stage output, which includes the miller
capacitor from the second stage and the load capacitance from the first stage. In many cases C1 can be
comparable to the load capacitor and thus the two stage amplifier has two low frequency poles. The two
stage amplifier also has two RHP zeroes due to the gate-to-drain capacitances in the first and the second
stages and they are given by
gm1
Sz1,2 = (15)
Cgd
Since Cgd is much smaller in value in comparison to the other capacitors and gm R >> 1, the zeroes occur
at much higher frequencies and can be ignored 1 .
Thus from a frequency response point of view, the gm boosted amplifier is just as good/bad as the two
stage amplifier. Cascode amplifiers are known for their superior frequency response characteristics as
always and hence it is better than the gm boosted and the two stage amplifiers.

V. N OISE ANALYSIS OF THE gm BOOSTED AMPLIFIER

The next step is to perform the noise analysis of the gm boosted amplifier. In a similar manner as
it was done for the frequency response, to understand the results of the noise analysis better, it is more
useful to compare it against the other high gain amplifier topologies like the cascode amplifier and the
two stage amplifier.
The noise analysis of the gm boosted amplifier is very straightforward as there are only three noise sources
in the gm boosted amplifier, the noise contributing MOS devices in the input pair and the negative resistance
devices and the noise from the load resistor as shown in Fig.7.(a). Let Sin1 ( f ) and Sin3 ( f ) denote the one
sided current noise PSD of the input device M1 and the negative resistance device M3 respectively. The
input referred noise can be found by finding the total output voltage noise and then dividing the output
noise by the dc gain Gm R = gm1 R/(1 − gm1 /gm3 ). Or the other approach is to find the total output short
circuit current noise density and then divide it by square of the amplifier transconductance Gm 2 . Since
Sin1 ( f ) denotes the noise current density of the input pair device and Sin2 ( f ) denote the current noise
1 Here it is assumed that the stage amplifier is not compensated. In all practical applications, two stage amplifiers are compensated using different compensation
schemes like Miller, Ahuja or Feed-forward compensation techniques. Once the compensation techniques are applied, the pole and zero locations of the two
stage amplifiers will change.
 gm1
Gm = Gm = gm1 Gm = gm1(gm1R)
1-(gm1/gm3)

R inR in4
iout
iout R inR R inR
vi iout
in1 vi
in1 in2
vi in1
-1/gm3 in3

(a) (b) (c)

Fig. 7. Small signal model showing the different noise sources for a) gm boosted amplifier, b) Cascode amplifier and c) Two-stage amplifier.

density of the negative resistance device and 4kT /R is the noise current density of the load resistor, the
current noise density at the amplifier output can be shown to be
!
Sin1 ( f ) Sin1 ( f )(gm1 /gm3 )2 4kT
Siout ( f ) = 2 + +
(1 − gm1 /gm3 )2 (1 − gm1 /gm3 )2 R
The input referred voltage noise density is given by
 
Siout ( f ) Sin1 ( f ) Sin3 ( f ) 4kT
Svin ( f ) = 2
=2 + +2 (16)
Gm gm1 2 gm3 2
RGm 2
where Gm = gm1 /(1 − gm1 /gm3 ). The factor 2 in the above expression accounts for noise from the two
halves of the differential circuit. Thus both the input pair and the degeneration devices contribute equally
at the input as both the transconductance is chosen to be very close to each other (gm1 ≈ gm3 ). Since
the transconductance of the device is increased, the noise contributor from the load resistor is attenuated
significantly by the amplifier. The total input referred thermal noise of the amplifier can be approximated
as
8kT γ 8kT γ 16kT γ
Svin ( f ) ≈ + ≈ (17)
gm1 gm3 gm1
Now for the cascode amplifier, the noise is mainly dominated by the input MOS device and the load device
as shown in Fig.7.(b). The noise from the intermediate cascode devices gets suppressed by the feedback
action of the input and the load devices. The intermediate devices can be seen as source degenerated
MOS devices, where the input and the load device act like the source degeneration resistor with a very
high resistance. Following a similar approach of finding the output current density and then refer it to the
input, the input referred voltage noise density can be shown to be
8kT γ 8kT γgm4 16kT γ
Svin,cascode ( f ) = + ≈ (18)
gm1 gm1 2 gm1
Here it was assumed that the load device gm is very close to the input device 2 gm .
The noise sources of the two stage amplifier are shown in Fig.7.(c). Assuming that the two stage are
2 This is a reasonable approximation that holds well in both Telescopic cascode and the folded cascode amplifier.
identical gm1 = gm2 , the total input referred noise can be shown to be
 
8kT γ 8kT 8kT γ 8kT 1
Svin,2stage ( f ) = + + + · (19)
gm1 Rgm1 2 gm1 Rgm1 2
(gm1 R)2
The noise of the first stage dominates the overall noise as the noise from the second stage gets attenuated
by the gain of the first stage amplifier. Assuming gm1 R >> 1, the total noise referred noise of the two
stage amplifier can be reduced to
8kT γ 4kT 8kT γ
Svin,2stage ( f ) ≈ +2 2
≈ (20)
gm1 Rgm1 gm1
Thus from a noise point of view, the noise of the gm boosted amplifier is slightly higher than the cascode
and two stage amplifiers.

VI. L ARGE SIGNAL TRANSFER CHARACTERISTICS OF DIFFERENTIAL PAIR WITH NEGATIVE SOURCE DEGENERATION
RESISTANCE

I1 I2 I1 I2
vip vin vip vin
M1 M2 M1 M2

I0 M4 M3

(a) vid = vip-vin (b) I0

I0 I1,I2 I0

√2Vov √2αVov 0 √2αVov √2Vov vid

(c)
α = (1- gm1/gm3)
Fig. 8. The differential pair and the corresponding transfer characteristics for a) A conventional differential pair with a bias current I0 , 2) a differential pair
biased with bias current nI0 , c) a differential pair with negative source degeneration resistance and d) Transfer characteristics of all the circuits overlaid on
top of each other.

So far the small signal behavior of the circuit was studied in detail and compared with the conventional
amplifier topologies. In this section, the large signal behavior of the amplifier is analyzed and compared
with a conventional differential amplifier with a resistive load to develop an intuitive understanding of its
characteristics.
To derive the exact results of the drain current for large signal, we start with the two main equations
relating the differential voltage to the gate-to-source voltages and the zero sum nature 3 of the differential
amplifier current.
vid = Vgs1 +Vgs3 − (Vgs2 +Vgs4 ) & I0 = I1 + I2 (21)
Ignoring the body effect and the channel length modulation, the gate-source voltages of the devices are
given by s s
2I1 2I2
Vgs1 = +VT N & Vgs2 = +VT N (22)
β1 β1
s s
2I2 2I1
Vgs3 = +VT N & Vgs4 = +VT N (23)
β3 β3
where β1 = µnCox (W /L)1,2 and β3 = µnCox (W /L)3,4 are input pair and the source degeneration pair device
parameters. Substituting Eq.(22) and Eq.(23) in Eq.(21), we get
s s !
√ √ 2 2
vid = ( I1 − I2 ) − & I0 = I1 + I2 (24)
β1 β3
Solving the above equations, the drains currents of the differential pair can be shown to be
 s  s !
 2
I0  vid 1 vid
 2 I0 v id 2  v 2
id 1  v 4
id
I1 = 1+ 1− 1− = 1+ − 2 (25)
2 |vid | I0 k 2 |vid | I0 k I0 k
 s  s !
 2
I0  vid 1 vid 2  I0
  vid 2  vid 2 1  vid 4
I2 = 1− 1− 1− = 1− − 2 (26)
2 |vid | I0 k 2 |vid | I0 k I0 k
p p
where k = (2/β1 ) − (2/β3 ). The function vid /|vid | is the sign of the signal vid and its value is assumed
to be zero when vid = 0. It can be immediately seen that the drain currents are exactly the same in both
the devices I1 = I2 = 0.5I0 , when vid = 0. These results are valid as long as the devices are in saturation
region. The condition where the equations are no longer valid, can be found by using the condition when
the drain current fully switches into one of the two devices.
s !
√ √
 
β1 gm1
I1 = I0 =⇒ vid = 2Vov 1 − = 2Vov 1 − (27)
β3 gm3
Similarly the condition when the current switches into the another device can be shown to be
s !
√ √
 
β1 gm1
I2 = I0 =⇒ vid = − 2Vov 1 − = − 2Vov 1 − (28)
β3 gm3
Now that we have the expressions for the nonlinear characteristics of the amplifier, we can study the
impact of negative resistance degeneration on the linearity of the amplifier. The output voltage of the
conventional differential pair assuming a resistive load is given by
s !
2 vid
 2 1 vid
 4
vout = vop − von = (I1 − I2 )·R = I0 R − 2 (29)
I0 k I0 k
3 In a differential pair, the two drain currents of the differential pair follows a zero sum relation. That is the sum of the two currents are constant. An
increase in one current has to happen at the expense of decrease in the drain current of the other device in the differential pair driven by an input of opposite
polarity.
 VDD

R v R VDD
- out +
vip vin
M1 M2 R v R
- out +
vip vin
M4 M3 M1 M2

I0 I0
vout
α = (1- gm1/gm3) I0 R

√2Vov √2αVov

√2αVov √2Vov vid

-I0R

Fig. 9. The differential pair and the corresponding input/output transfer characteristics for a conventional differential amplifier and a gm boosted differential
amplifier

The above expression can be further reduced to

s s
 2
gm1 R 1 vid
 2 gm1 R vid
vout = vid 1 − = vid 1 − (30)
1 − (gm1 /gm3 ) 2I0 k 1 − (gm1 /gm3 ) 2Vov (1 − gm1 /gm3 )
The above expression is valid as long as the devices are in saturation region. That is
s
2
√

gm1 R vid
vout = vid 1 − for |vid | ≤ 2Vov (1 − gm1 /gm3 ) (31)
1 − (gm1 /gm3 ) 2Vov (1 − gm1 /gm3 )
To compare it with a conventional differential pair amplifier with a resistive load, the output voltage can
be expressed as s
vid 2 √
 
vout = gm1 Rvid 1 − for |vid | ≤ 2Vov (32)
2Vov
The transfer characteristics of the differential amplifier and the gm boosted differential amplifier are
shown in Fig.9. The differential pair with gm boosting using negative source degeneration resistance has
a transfer characteristics very similar in shape to a conventional differential pair but the current switching
happens at a much smaller input signal level. Since the bias current is same for both the amplifier and the
transconductance of the gm boosted amplifier is much higher, the current switching happens at a much
smaller input signal level.

A. Problem of input common mode

The whole idea of using a Gm-boosted amplifier using negative resistance is to realize high gain
without resorting to multiple amplifier stages or to stack up devices like the cascode amplifier. A cascode
amplifier has a limited voltage swing due to the stacked devices and the two stage amplifier does not
suffer from this problem. To complete the analysis of the gm boosted amplifier, the voltage swing and
input common mode levels are discussed and compared with the other amplifier topologies here.
The input common mode level of the gm boosted amplifier shown in Fig.9 is required to bias two MOS
devices in series and a tail current source. The input common mode level and the voltage swing of the
amplifier are given by
VCM = VGS1 +VGS3 +Vtail & Vswing = 2(VDD −VOV 1 −VGS3 −Vtail ) (33)
where VOV 1 = VGS1 − VT N is the overdrive voltage of the input pair devices and Vtail is the minimum
voltage required to bias the current source device in the differential amplifier. The input CM level is one
Vgs higher compared to a conventional differential amplifier. A higher input CM also restricts the output
swing as the output signal level cannot go below VCM − VT N . One simple way to address this problem
is to use a complementary input pair and negative resistance structure as shown in Fig.10. The input

VDD VDD

I0 I0 I0
R R
von vop vip vin
M4 M3 M1 M2
vip vin von
M1 M2 M4 M3 vop

R R
I0 I0 I0

(a) (b)

Fig. 10. A complementary differential amplifier with Gm boosting using negative resistance with a) NMOS input pair and PMOS negative resistance
degeneration and b) PMOS input pair and NMOS negative resistance degeneration.

common model voltage required in this case reduces by one VGS and the voltage swing increases by the
same amount. The input common mode and voltage swing are given by
VCM = VGS1 +Vtail & Vswing = 2(VDD −VOV 1 −Vtail ) (34)
Thus the voltage swing and the common mode levels can be made to be equal to the conventional
differential amplifier in this approach. The only problem with this approach is that the power dissipation
of the amplifier is doubled compared to conventional gm boosted amplifier. Another problem with this
approach is that the tail current sources connected to the input pair in this architecture see the full voltage
swing of the differential negative resistance. In a conventional differential pair, the tail current source is
differentially at ground but now the signal level at the tail node is ≈ 0.5vid /(1 − gm1 /gm3 ). This is another
source of non-linearity. In addition to that the noise from the tail current source at the source nodes of M1
and M2 will also contribute to noise. Assuming the current source device is designed to have similar gm
as the input pair, the total input referred noise will increase by 50% compared to the normal gm boosted
amplifier in Fig.9.
To achieve a wide input common mode range or to operate the amplifier over a range of input common
mode levels, a complimentary input pair or a class-AB input amplifier is often used. Fig.11 shows two
class-AB amplifier realizations with gm boosting with the common mode feedback amplifier in place ( all
the biasing circuits are not shown fully). This circuit can operate at a rail-to-rail input common level. The
voltage swing of the amplifier in Fig.11.(b) is given by
Vswing = 2(VDD −VOV 1 −VGS3 −Vtailn −VOV 5 −VSG7 −Vtail p ) (35)
where Vtailn and Vtail p are the minimum voltages required to bias the NMOS and PMOS tail current
sources. The voltage swing of the amplifier shown in Fig.11.(b) is given by
Vswing = 2(VDD −VOV 1 −Vtailn −VOV 5 −Vtail p ) (36)
The voltage swing of class-AB input amplifier in Fig.11.(a) is 2VGS higher compared to the amplifier in
Fig.11.(b). The voltage swing of the amplifier is very similar to that of a folded cascode amplifier. One
can construct a folded cascode amplifier structures using a gm boosting for the input pair devices as well
to achieve very high gains. All the details of the CMFB is not shown in the figure. It is assumed that
VDD
MT1 MT2
MT

M5 M6
M8 M7 M8 M7
von vop VCM
I0 M5 M6
vip von vop vin vip von vop vin
IB VDD
CMFB I0 M1 M2

M4 M3 M4 M3
M1 M2

I0 I0 I0
(a) (b)

Fig. 11. A class AB differential amplifier with gm boosting shown with the CMFB circuitry for a) a complementary input and negative resistance pair and
b) a similar input and negative resistance pair.

the CMFB is stable. This can be ensured by keeping the gain of the error amplifier of the CMFB circuit
smaller.

VII. G AIN BOOSTING BY INCREASING OUTPUT IMPEDANCE USING NEGATIVE RESISTANCE

The other approach to achieve high gains is to use a negative resistance to increase the output impedance
of the amplifier. In this approach a negative resistance is connected to the output node which increases the
amplifier output resistance and hence the gain. Different circuit realizations of the amplifier with output
resistance boosting are shown in Fig.12.(a)-(d). All the amplifiers have a differential input pair, a current
source/resistive load and a differential negative resistance connected in parallel to the load to improve
the output resistance. Let gm1 & gds1 be the transconductance and output conductance of the input pair
devices M1/M2 and gm3 & gds3 be that of the current source load devices M3/M4. Let gml & gdsl denote
 VDD VDD VDD VDD VDD

Vbp Vbp b) IB1 Vbp Vbp c) IB1 IB2

M3 ML ML M4 M3 M4
von vop
von vop vip vin vip vin
M1 M2 M1 M2 ML ML
vip M1 M2 vin von vop vip M1 M2 ML
vin ML vop von
Vbn Vbn Vbn
M3 ML ML M4 Vbn M3 M4
a) IB1 c) IB1 IB2

Fig. 12. a) NMOS input pair with PMOS cross coupled load, b) PMOS input pair with NMOS cross coupled load, c) NMOS input pair with NMOS cross
coupled load and d) PMOS input pair with PMOS cross coupled load

the transconductance and output conductance of the cross coupled load devices ML , then the gain of the
amplifier is given by
vop − von gm1
Av = = (37)
vip − vin gds1 + gds3 + gdsl − gml
If the transconductance gml is chosen such that it cancels out the output resistance at the output node,
then theoretically the gain can reach infinite value
gm1
gds1 + gds3 + gdsl = gml =⇒ Av = →∞ (38)
gds1 + gds3 + gdsl − gml
However choosing the value of gml close to the total output conductance might result in overcompensation
of the output conductance due to process variations and the polarity of the gain might be reversed. When
used in feedback, negative feedback can become positive and thus the system can become unstable. So it
is a common practice that the gml is chosen very close to the output conductance. For example gml can
be chosen such that it cancels out most of the output resistance
gm1 gm1
gds1 + gds3 + gdsl − gml = 0.1gds1 =⇒ Av = = 10 · (39)
gds1 + gds3 + gdsl − gml gds1
Thus the single stage gain increases by ten fold compared to the intrinsic gain of the amplifier!
The circuit configurations shown in Fig.12.(a)-(d) suffer form poor input-common mode range. This

I1 I2

M3 M4 M7 M8
vip - vout + vin von vop
von vop VCM von vop
Iref M1 M2 M5 M6

CMFB I1 I2

Fig. 13. Schematic showing a class-AB differential amplifier with a CMOS negative resiatnce load whose value can be set independent of the input pair
transconductance.

problem can be addressed by choosing a complementary input pair or a class-AB input pair. A fully
differential wide-swing differential amplifier that can operate over a wide range of input common mode
levels is shown in Fig.13. The circuit has a class-AB input pair and a class AB or push-pull output stage
negative resistance which can be biased independent of the input pair devices. Also included in the circuit
schematic is the common mode feedback (CMFB) circuit. The gain of the amplifier can be easily shown
to be
vop − von gm1 + gm3
Av = = (40)
vip − vin gds1 + gds3 + gds7 + gds5 − gm5 − gm7
The circuit offers similar advantages of high gain by an increase in the output impedance due to the
negative resistance offered by the CMOS cross coupled latch structure in the figure. The circuit is also
power optimal as the cross coupled latch provides a higher negative conductance for the same power
compared to either PMOS or NMOS only latch.

A. Frequency response and noise

jω
Rout -Rn
vout σ
vi
CL -1 Rn-Rout
RCL Rn

Fig. 14. High frequency model of a Output resistance boosted amplifier and the corresponding pole zero plot.

The frequency response of the gain boosting using a negative resistance loads is very similar to cascode
amplifier, as the output node impedance is very high due to the negative resistance. Let Rout denote the
output resistance of the amplifier and −Rn denote the negative resistance connected in parallel to the
output resistance to the load as shown in Fig.14. The amplifier has only one dominant pole at the output
given by  
1 Rn − Rout
S p1 = − · (41)
Rout CL Rn
since Rn is very close to Rout , the pole is very close to dc.
The amplifier consists of an input device and a load device and a negative resistance device connected
at the output and hence there are three sources of noise in the amplifier. Let gm1 denote the input pair
transconductance and gml and gm3 denote the transconductance of the negative resistance and the load
devices respectively. The total input referred noise of the amplifier can be shown to be
 
4kT γ 4kT γ(gml + gm3 ) 16kT γ
Svin ( f ) = 2 + 2
≈ (42)
gm1 gm1 gm1
It can be safely assumed that gm1 ≈ gm3 + gml and the noise of the amplifier can be reduced to that of a
cascode amplifier. Thus the noise and the frequency response of the output resistance boosted amplifier
is very similar to that of a cascode amplifier but with an improved voltage swing.

VIII. C ONCLUSION
Two approaches to increase the voltage gain using negative resistance was discussed. In the first
approach the gm of the amplifier is boosted using a negative resistance to achieve very high gain. This
approach suffer from poor voltage swing problems and also a poor frequency response as it has two low
frequency poles and a RHP zero by its design. The second approach is to improve the output resistance of
the amplifier by connecting a negative resistance parallel to the load. This approach has better frequency
response and noise almost comparable to that of single stage cascode amplifiers. The voltage swing is
similar in both the approaches, though the latter approach can operate at low common mode levels.