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Lab1
Lab1
Lab1
1.2 OBJECTIVE
• Verify that the Xilinx tools are up and running
• Introduce you to the Xilinx ISE software.
• Become familiar with Verilog coding and use of the ISE simulator.
• Be able to synthesize and implement Verilog designs using ISE..
1.3 THEORY
1.3.1 INTRODUCTION.
This is a step-by-step tutorial for building a 1-bit full adder in Xilinx ISE 8.2, a Design Suite software that
provides designers with the ability to code designs in a hardware description language such as VHDL or
Verilog. The ISE Design Suite also provides the ability to apply FPGA pin and timing constraints, analyze
for errors and violations, and synthesize to generate configuration bit file formats for FPGAs.
By using half adder, you can design simple addition with the help of logic gates.Let’s see an addition of
single bits.
INPUT OUTPUT
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
Table 1.1 Half Adder truth table
Now it has been cleared that 1-bit adder can be easily implemented with the help of the XOR Gate for the
output ‘SUM’ and an AND Gate for the ‘Carry’. When we need to add, two 8-bit bytes together, we can be
done with the help of a full-adder logic. The half-adder is useful when you want to add one binary digit
quantities. A way to develop a two-binary digit adders would be to make a truth table and reduce it. When
you want to make a three binary digit adder, do it again. When you decide to make a four digit adder, do it
again. The circuits would be fast, but development time is slow.
CIRCUIT DIAGRAM
case(a)
2'b00:
begin
sum <= 0;
carry <= 0;
end
endmodule
1.4.3 Test Bench
module halfadder_tb();
// Inputs
reg [1:0] a;
//outputs
wire sum;
wire carry;
initial begin
a=0;
#100
a=1;
#100
a=2;
#100
a=3;
end
endmodule
INPUT OUTPUT
A B Cin Cout S
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1
Table 1.2 Half Adder truth table
endmodule
// Outputs
wire sum;
wire carry;
// Instantiation
fulladder uut(.a_in(a_in), .b_in(b_in), .c_in(c_in), .sum(sum),
.carry(carry)
);
initial begin
a_in=0;
b_in=0;
c_in=0;
#100
a_in=0;
b_in=0;
c_in=1;
#100
a_in=0;
b_in=1;
c_in=0;
#100
a_in=0;
b_in=1;
c_in=1;
#100
a_in=1;
b_in=0;
c_in=0;
#100
#100
a_in=1;
b_in=0;
c_in=1;
#100
a_in=1;
b_in=1;
c_in=0;
#100
a_in=1;
b_in=1;
c_in=1;
end
endmodule
// Outputs
wire sum;
wire carry;
// Instantiation
fulladder uut(.abc(abc), .sum(sum), .carry(carry)
);
initial begin
abc=0;
#100
abc=1;
#100
abc=2;
#100
abc=3;
#100
abc=4;
#100
abc=5;
#100
1.7 IN LAB-TASK
Implement 4-bit full adder at gate level also create their test bench.
A 2^n-to-n encoder has n number of outputs in correspondence to the 2^n number of inputs. It thus
reduces the number of transmission lines and can be compared to a multiplexer. Only one of the
inputs become "high" (logic state "1") at a time.
Example:
• 8:3 encoder ( you are required to implement 8:3 encoder)