KR21 COMPUTER ORGANIZATION AND ARCHITECTURE CSE II/I

Unit-IV(Part 3)

RISC and CISC in Computer Organization

• RISC : RISC stands for Reduced Instruction Set Computers. It was introduced to execute
as fast as one instruction per clock cycle. This RISC pipeline helps to simplify the
computer architecture’s design.

• CISC : To avoid these consequences, the conventional response of the computer

architects is to add layers of complexity to newer architectures. This also increases the
number and complexity of instructions together with an increase in the number of
addressing modes. The architecture which resulted from the adoption of this “add more
complexity” are known as Complex Instruction Set Computers (CISC).

• Both approaches try to increase the CPU performance

Reduced Instruction Set Architecture (RISC)

• The main idea behind this is to simplify hardware by using an instruction set composed
of a few basic steps for loading, evaluating, and storing operations just like a load
command will load data, a store command will store the data.

Characteristics of RISC

• Simpler instruction, hence simple instruction decoding.

• Instruction comes undersize of one word.

• Instruction takes a single clock cycle to get executed.

• More general-purpose registers.

• Simple Addressing Modes.

• Fewer Data types.

• A pipeline can be achieved.

Advantages of RISC

• Simpler instructions: RISC processors use a smaller set of simple instructions, which
makes them easier to decode and execute quickly. This results in faster processing times.

• Faster execution: Because RISC processors have a simpler instruction set, they can
execute instructions faster than CISC processors.

• Lower power consumption: RISC processors consume less power than CISC
processors, making them ideal for portable devices.
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Disadvantages of RISC

• More instructions required: RISC processors require more instructions to perform

complex tasks than CISC processors.

• Increased memory usage: RISC processors require more memory to store the additional
instructions needed to perform complex tasks.

• Higher cost: Developing and manufacturing RISC processors can be more expensive
than CISC processors.

Complex Instruction Set Architecture (CISC)

• The main idea is that a single instruction will do all loading, evaluating, and storing
operations just like a multiplication command will do stuff like loading data, evaluating,
and storing it, hence it’s complex.

Characteristics of CISC

• Complex instruction, hence complex instruction decoding.

• Instructions are larger than one-word size.

• Instruction may take more than a single clock cycle to get executed.

• Less number of general-purpose registers as operations get performed in memory itself.

• Complex Addressing Modes.

• More Data types.

Advantages of CISC

• Reduced code size: CISC processors use complex instructions that can perform multiple
operations, reducing the amount of code needed to perform a task.

• More memory efficient: Because CISC instructions are more complex, they require
fewer instructions to perform complex tasks, which can result in more memory-efficient
code.

• Widely used: CISC processors have been in use for a longer time than RISC processors,
so they have a larger user base and more available software.
KR21 COMPUTER ORGANIZATION AND ARCHITECTURE CSE II/I

Disadvantages of CISC

• Slower execution: CISC processors take longer to execute instructions because they
have more complex instructions and need more time to decode them.

• More complex design: CISC processors have more complex instruction sets, which
makes them more difficult to design and manufacture.

• Higher power consumption: CISC processors consume more power than RISC
processors because of their more complex instruction sets.

Three-Segment Instruction Pipeline

• The data manipulation instructions operate on data in processor registers. The data
transfer instructions are load and store instructions that use an effective address obtained
from the addition of the contents of two registers or a register and a displacement
constant provided in the instruction.

The program control instructions use register values and a constant to evaluate the branch
address, which is transferred to a register or the program counter PC.

Now consider the hardware operation for such a computer. The control section fetches the
instruction from program memory into an instruction register. The instruction is decoded at the
same time that the registers needed for the execution of the instruction are selected.

The processor unit consists of a number of registers and an arithmetic logic unit (ALU) that
performs the necessary arithmetic, logic, and shift operations. A data memory is used to load or
store the data from a selected register in the register file. The instruction cycle can be divided
into three suboperations and implemented in three segments:

I: Instruction fetch

A: ALU operation

E:Executeinstruction

• The I segment fetches the instruction from program memory. The instruction is decoded
and an ALU operation is performed in the A segment.

• The ALU is used for three different functions, depending on the decoded instruction. It
performs an operation for a data manipulation instruction, it evaluates the effective
address for a load or store instruction, or it calculates the branch address for a program
control instruction.

• The E segment directs the output of the ALU to one of three destinations, depending on
the decoded instruction. It transfers the result of the ALU operation into a destination
KR21 COMPUTER ORGANIZATION AND ARCHITECTURE CSE II/I

register in the register file, it transfers the effective address to a data memory for loading
or storing, or it transfers the branch address to the program counter.

Delayed Load

This is a type of instruction that is fetched from

Differences between CISC and RISC Characteristics:

CISC Characteristics:

1. A large number of instructions around 100 to 200

2. Some instructions that perform specialized tasks and are used infrequently
3. A large variety of addressing mode around 5 to 20
4. Variable length instruction formats
5. Instructions that manipulate operands in memory.

RISC Characteristics:

1. Relatively few instructions.

2. Relatively few addressing modes
3. Memory access limited to load and store instructions.
4. All operations done within the registers of the CPU
5. Fixed Length, easily decoded instruction formats
KR21 COMPUTER ORGANIZATION AND ARCHITECTURE CSE II/I

6. Single cycle instruction execution

7. Hardwired rather than programmed control.

Suppose we have an operation

A = B+C

RISC Instruction set for this would be :

Load R2, B

Load R3, C

Add R4 , R2, R3

Store R4 , A

Now , let us see the CISC instruction set for the same Operation

Move A,B

Add A,C

Pipeline performance

• Pipeline performance is the improvement in speed of performance if pipelining is used.

• Ksegment

• Tpclock cycle

• nno.of tasks

• T1ktp

• Remaining tasks(n-1)tp

• Total=ktp+(n-1)tp

= tp(k+n-1)
KR21 COMPUTER ORGANIZATION AND ARCHITECTURE CSE II/I

Clock cycle 1 2 3 4 5 6 7 8 9
/segment
1 T1 T2 T3 T4 T5 T6
2 T1 T2 T3 T4 T5 T6
3 T1 T2 T3 T4 T5 T6
4 T1 T2 T3 T4 T5 T6
Space time diagram for pipeline

In non pipelining

• tntime

• Nno of tasks

• Total time=ntn

• Speedup ratio=time for non pipelining/time for pipelining

• S=ntn/[k+(n-1)]tp

• As no of tasks increases n>k-1…..n

• S=ntn/ntp=tn/tp

=ktp/tp=k

s=k(speedup ratio=no of tasks)

Ex: Let the time to process tp=20ns,k=4,n=100,calculate speedup?

• Speedup ratio=time for non pipelining/time for pipelining

• S=ntn/[k+(n-1)]tp

• [k+(n-1)]tp=[4+(100-1)]20=2060ns

• non pipelining tn =ktp

=4x20

ntn =100x80=8000ns

S=8000/2060=3.88=4