A Bit-Serial Approximate Min-Sum LDPC Decoder

and FPGA Implementation

Ahmad Darabiha, Anthony Chan Carusone,

Frank R. Kschischang

University of Toronto, Toronto, Canada

ISCAS, Kos, Greece
May 2006
ISCAS 2006

Outline

• Introduction to LDPC codes/decoders

• Proposed techniques
• Bit-serial message passing
• Approximate Min-Sum decoding
• FPGA implementation
• Conclusion

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Introduction

• Low-Density Parity-Check (LDPC) codes

• A sub-class of Error Control Codes (ECC)
• Perform better than Turbo and Reed-Solomon codes
• Approach Shannon limit

• LDPC codes are adopted for

• IEEE 802.3 10Gbit Ethernet standard
• Input BER > 10-3
• Output BER < 10-13
• Code rate 0.84
• DVB-S2 Digital Video Broadcast standard

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LDPC Codes: Structure

M =5 check
DC = 4 nodes

DV = 2 N=10
v a ria b le
nodes

1 0 0 1 0 1 0 0 1 0
0 1 1 0 1 0 0 1 0 0
HMxN = 0 0 0 1 0 1 1 0 1 0
1 1 0 0 0 0 1 0 0 1
• Each bit participates in Dv parity checks 0 0 1 0 1 0 0 1 0 1

• Each check consists of Dc bits

• Good LDPC codes are long (large N) and with a random-like graph

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Min-Sum LDPC Decoding

• A form of iterative message passing decoding
checks
• Messages in Log-Likelihood Ratio (LLR)
• Log(P(x=0) / P (x=1))

• Each iteration does two updates: V1 Cm

V2 Vm-1
• Check node update
cm = chk(v1, .., vm-1)
variable
= (sgn(v1) .. sgn(vm-1)) Min(|v1|, …, |vm-1|)

checks

• Variable node update C2

Cn-1
C1 Vn
vn = var(c1, c2 ,..,cn-1)
= c1 + c2 + .. + cn-1
Variables
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LDPC Decoders: Architecture

• We use fully-parallel architecture

• Allows high throughput
• Graph is directly mapped to hardware

• Major challenge:
• Complex interconnection
• Wire capacitance
- Power dissipation
- Wire delay
• Routing congestion
- Larger area

• We propose a bit-serial scheme to reduce

interconnections

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Bit-Serial Message-Passing

C lk C lk

L in e # 1 b1
S e ria l l in e b1 b2 bn
L in e # 2 b2

L in e # n bn n c y c le s

B it-p a ra lle l B it-s e ria l

• bit-serial scheme
• transfers an n-bit message in n clock cycles over a single wire
• is Ideal for Min-Sum decoding
• reduces the number of wires => reduced routing congestion
• both Min and Sum functions are naturally bit-serial
• facilitates efficient gear shift decoding

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Min-Sum Approximation

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Approximation to Min-Sum Decoding

• In original Min-Sum each check
node needs to find first and checks
second minimum

• We approximate Min-Sum:
Cm
• Variable node the same as V1 V 2 V m -1 V m
conventional Min-Sum
• Check node update:
v a ria b le
cm = check(v1, .., vm)
= (sgn(v1) .. sgn(vm-1)) Min(|v1|, …, |vm|)

• In Approximate Min-Sum only the first minimum needs to be found

• reduces the check node logic by about 50%

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Approximate Min-Sum: Performance

(Full-Precision)
1.E-01

Original MS, LDPC-2048

1.E-02
Original MS, LDPC-992
Approx. MS, LDPC-2048
1.E-03 Approx. MS, LDPC-992
BER .

1.E-04

1.E-05

1.E-06
3.5 4 4.5 5 5.5 6 6.5

EbNo(dB)

Under full-precision computations, conventional Min-Sum and

approximate Min-Sum perform closely

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Approximate Min-Sum: Performance (Quantized)

1.E-01

1.E-02 Original MS, 4bit

Approx. MS, 4bit
1.E-03
BER .

1.E-04

1.E-05

1.E-06

1.E-07
3.5 4 4.5 5 5.5 6
EbNo (dB)

With quantized calculations, there is more than 0.5dB difference in

performance between conventional and approximate Min-Sum

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Approximate Min-Sum + Correction

• We add a correction factor to the check update rule to reduce the
gap between conventional Min-Sum and approximate Min-Sum

• Variable node unchanged

checks
• Check node:

• Define M = min(|v1|, …, |vm-1|, |vm|)

Cm
• Define T = No. of identical absolute V1 V 2 V m-1 Vm
minimums

variable
• cm = check(v1, v2, .., vm)

(sgn(v1) .. sgn(vm-1)) M + 1 if (Vm= M & T = 1),

=
(sgn(v1) .. sgn(vm-1)) M otherwise

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Approximate Min-Sum + Correction: Performance

1.E-01
Original MS, 4bit
1.E-02 Approx. MS, 4bit
Approx. MS+ correction, 4bit
1.E-03
BER .

1.E-04

1.E-05

1.E-06

1.E-07
3.5 4 4.5 5 5.5 6 6.5
EbNo (dB)

By adding the correction factor, performance loss is reduced

from 0.6 dB to less than 0.1dB

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FPGA implementation

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FPGA Min-Sum Decoder

• Decoder built on FPGA (Stratix EP1S80)

• Fully parallel architecture

• Approximate Min-Sum decoding with correction

• Bit-serial message passing

• A regular-(4,15) (480, 355) LDPC code constructed

using progressive edge growth (PEG) algorithm

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Check Node Architecture

In p u t # 1
S ta tu s fla g s
s to re s ta te o f
e a c h in p u t in
c o m p e titio n
In p u t # 2

M in O u t
B it-S e ria l
in p u ts B it-s e ria l
M S B firs t o u tp u t
M S B firs t

In p u t # d c

• Output sign is calculated separately using XOR gates

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Variable Node Architecture

Input #1
1
2 n n
n parallel Output #1
Input #2
adder

bit n n
serial Output #2
inputs

Input #d v bit
serial
n n outputs
Output #d v

• Inputs arrive bit-serially, LSB first

• Addition and subtractions are performed bit-parallel
• For larger word lengths, a serial approach will be more efficient
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BER Performance

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Decoder Spec
L. Yang et al.
This work
TCAS 2006

FPGA device Stratix EP1S80 Xilinx XC2V8000

Logic 66,000 LUTs 53,000 LUTs

Memory 0 102 blockRAMs

PEG_LDPC
Code type (4,15) regular
multi-rate codes

Code rate 0.74 ½, 5/8, 7/8

Code length 480 9000
Decoding algorithm Modified Min-Sum Min-Sum
iterations/frame 15 24
Clock frequency 61 MHz 100 MHz
Throughput 650 Mbit/sec Up to 40 Mbit/sec
Quantization 3 bit -
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Conclusion

• Bit-serial message passing

• An efficient approach for implementing fully-parallel LDPC decoders
• Reduces interconnection complexity
• Suitable for Min-Sum decoding

• Modified Min-Sum decoding with the correction factor demonstrates

high BER performance with 48% saving in check node logic

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