project synopsis

In The Name of Almighty

Lec. 4:
Flash ADC (Part-I)
Architecture & Challenges
Lecturer: Samaneh Babayan
Integrated Circuit Lab.
Department of Computer Science & Engineering
ImamReza University of Mashhad
Sep. 2015.
 In The Name of Almighty

Lec. 4:
Flash ADC (Part-I)
Architecture & Challenges
Lecturer: Hooman Farkhani
Department of Electrical Engineering
Islamic Azad University of Najafabad
Feb. 2016.
Email: H_farkhani@yahoo.com
Analog to Digital Converters

 Nyquist-Rate ADCs
 Flash ADCs
 Sub-Ranging ADCs
 Folding/ Interpolating ADCs
 Pipelined ADCs
 Successive Approximation ADCs (SA-ADCs)
 Integrating (serial) ADCs

 Oversampling ADCs
 Delta-Sigma based ADCs

3
4
Conversion Principles

Principle Resolution Speed Cost

Serial High Low Low

Conversion >12 Bit <1kHz

Successive Medium Medium Medium

Approximation 8-14 Bit <100MHz

Parallel Low High High

Conversion 6-10 Bit >100MHz

Delta High Low-Medium Low

Sigma >12 Bit <1MHz (analog only)

5
6
 ADC Architectures
 Flash ADCs:
High speed, but large area and high power dissipation. Suitable for low-medium
resolution (6-10 bit).
 Sub-Ranging ADCs:
Require exponentially fewer comparators than Flash ADCs. Hence, they consume
less silicon area and less power.
 Pipelined ADCs:
Medium-high resolution with good speed. The trade-offs are latency and power.
 Successive Approximation ADCs:
Moderate speed with medium-high resolution (8-14 bit). Compact implementation.
 Integrating ADCs or Ramp ADCs:
Low speed but high resolution. Simple circuitry.
 Delta-Sigma based ADCs:
Moderate bandwidth due to oversampling, but very high resolution thanks to
oversampling and noise shaping.

7
ADC Architectures

8
9
 Flash ADC
Vi VFS Vi
Strobe • Advantrages
VFS 1. Conceptually most straightfor
fs
7 ward
7Δ One clock cycle / conversion
6 highest possible speed
6Δ 2. resolution: 3 ~ 8 bits
5 3. clock rates 20 MHz ~ tens of G

Encoder
5Δ Hz
Dout
…
…

…
…

2Δ
… • Disadvantages:
1 1. (2N -1) comparators required
Δ
Hardware complexity grows
0 exponentially with resolution
Do 0
2. Comparator offset limit the
resolution
2N-1
comparators
3. Large Power Consumption
4. Complex Layout Issues

10
Flash ADC
Thermometer Code

VFS Vi Strobe Thermometer code b2 b1 b0

fs
0 1
111

1 0
110

…
…
…

…
1 1
010

1 1
001

000
N
2 -1 1-of-n code
comparators
ROM encoder

11 11
 Flash ADC Challenges
● High Complexity (2N-1 Comparators):
- consumes large area
- high input capacitor
- Large power consumption
- Large comparators needed for
removing offset.
● Limited to the resolution of 4-8 Bits.
● Speed limited by single
comparator plus encoding logic.

1mV • VDD = 1.8 V

• 10-bit → 1023 comparators
1V
• VFS = 1 V → 1 LSB = 1 mV
σ
→ Vos < 0.5 LSB
• DNL < 0.5 LSB
→ σ = 0.1-0.2 mV
• 0.5 mV = 3-5 σ

12 12
 Flash ADC Challenges

128

• DNL < 0.5 LSB

32
• Large VFS relaxes offset tolerance
Vos, max [mV]

VFS = 2V • Small VFS benefits conversion speed

8
- (settling, linearity of building blocks)
VFS = 1V
2

0.5

4 6 8 10
N [bits]

13 13
 A Typical CMOS Comparator

VDD

Vos derives from:

M3 M4 M5 M6
• Preamp input pair
Φ mismatch (Vth,W,L)
Vos +
Vo V o- • PMOS loads and
M1 M2
Vi M9 current mirror
• Latch mismatch
M7 M8
• CI / CF imbalance
of M9
VSS
• Clock routing
Preamp Latch • Parasitics

14
Latch Regeneration

VDD
PA tracking Latch
Φ Latch reseting regenrating
M5 M6

Φ VDD
+
Vo Vo-
Vo+
CL M9 CL
Vo
M7 M8
Vo-
VSS VSS

Exponential regeneration due to positive feedback of M7 and M8

– 15 – 15
Regeneration Speed – Linear Model

Vo+ Vo- Vo+

-1
CL CL
 CL gmVo-
M7 M8 Vo-

 
 Vo   Vo

1 1  Vo  
        0
   
  
 o
V gm Vo /sCL 1 gm /sCL  Vo 

Δs  gm /sCL  1  0  sp  gm /CL , singleRHP pole

Vo t  0  Vo t  0 expt  gm /CL 

– 16 – 16
Reg. Speed – Linear Model

Vo+ Vo-

CL CL
Vo(t=0)
t Vo = 1V
M7 M8

Vo Vo(t=0) t/(CL/gm)
1V 100mV 2.3
CL  Vo t  
1V 10mV 4.6 t  ln 
gm  Vo t  0
1V 1mV 6.9
1V 100μV 9.2

– 17 – 17
Reg. Speed – Linear Model

M3 M4 Vm+ M5 M6 Vm- gm5Vm+ gm5Vm-

Vm+ V m- Φ=1 R9 R9
M1 M2 x Vo +
Vo-
 Vo+ 2 2 Vo-
Vi M9 X
-1 -1
M7 M8
gm7 gm7

gm1 gm5R9 R9 1
A V1  A V2  ,  to be amplifier.
gm3 2  gm7R9 2 gm7

Vo 0  Vi 0 A V  Vi 0 A V1A V2

Vo t   Vi 0 A V1A V2  expt  gm /CL 

– 18 – 18
Comparator Metastability

T/2
Φ Vo t   Vi 0 A V1A V2  expt  gm /CL 

Curve AV1AV2 Vi(t=0)

1 2 3 4  10 10 mV
Vo+  10 1 mV

Vo-  10 100 μV
 10 10 μV

Comparator fails to produce valid logic outputs within T/2 when input falls into a r
egion that is sufficiently close to the comparator threshold

– 19 – 19
Comparator Metastability

Do
Δ Assuming that the input is uniformly di
j+1
stributed over VFS, then

Δ
Vi BER 
1LSB

j
Vo t   Vi 0 A V1A V2  expt  gm /CL 
Vos

• Cascade preamp stages (typical flash comparator has 2-3 PA stages)

• Use pipelined multi-stage latches; PA can be pipelined too
• Avoid branching off comparator logic outputs

– 20 – 20
Comparator Metastability

Vi 1 1 1

x 0
100

1 0
011

Logic levels can be misinterpreted by digital gates (branching off, diff. outputs)
– even a wrong decision is better than no decision!

– 21 – 21
CI and CF in Latch

Φ
M5 M6
Φ

Vo+ Vo-
Cgs Cgd
CM
M9 jump
CL CL Vo+
M7 M8
Vo-

• Charge injection and clock feedthrough introduce CM jump in Vo+ and Vo-
• Dynamic latches are more susceptible to CI and CF errors

– 22 – 22
Dynamic Offset of Latch

Dynamic offset derives from:

Φ
• Imbalanced CI and CF
• Imbalanced load capacitance
• Mismatch b/t M7 and M8
• Mismatch b/t M5 and M6
+
Vo • Clock routing

Vo- 0.5V CM jump 

  50mV offset
10% imbalance 

Dynamic offset is usually the dominant offset error in latches

– 23 – 23
Typical CMOS Comparator

VDD
• Input-referred latch
M3 M4 M5 M6 offset gets divided by
the gain of PA
Φ
Vos
Vo +
V o- • Preamp introduces
M1 M2
Vi its own offset (mostly
M9
static due to Vth, W,
M7 M8 and L mismatches)
• PA also reduces
VSS
kickback noise
Preamp Latch

Kickback noise disturbs reference voltages, must settle before next sample

– 24 – 24
 Comparator Offset

VDD

M3 M4 M5 M6 Differential pair mismatch:

Φ
1 
2  ΔW 
2
 ΔL  
2

Vos  ΔV th 
Vos
 Vov   
2 2
 
+ -
Vo Vo
M1 M2
Vi M9
4  W   L  
M7 M8
gm1 gm5R9
A V1  A V2 
VSS gm3 2  gm7R9
Preamp Latch

Vos,34  Vos,56
2 2 2 2
Total input-referred Vos,78 Vos,dyn
Vos  Vos,12   
2 2
comparator offset: A
2
A
2
A V2
2 2
A V1 A V2
2
V1 V1

– 25 – 25
Matching Properties

Suppose parameter P of two rectangular devices has a mismatch error of ΔP. The variance of
parameter ΔP b/t the two devices is

2
A
σ ΔP   P  SP D2 ,
2 2 1st term dominates
WL for small devices

where, W and L are the effective width and length, D is the distance

A Vth2
Threshold : σ  Vth  =
2
+ S Vth2D2
WL
σ 2 β  A β2
Current factor :   Sβ 2D2
β 2
WL

Ref: M. J. M. Pelgrom, et al., “Matching properties of MOS transistors,” IEEE Journal o

f Solid-State Circuits, vol. 24, pp. 1433-1439, issue 5, 1989.

– 26 – 26
Why Large Devices Match Better?

R1 R2

W X X X X X X … X X

L
10 identical resistors

L  L 
R1  RS  with std σR1 R2  RS 10    10R1 with std σR2 ,
W W
10
σR2   σR j 2  10σR12  σR2  10σR1
2

j1

σR2 10σR1 1  σR1  σR 1 1 “Spatial

      
R2 10R1 10  R1  R A WL averaging”

– 27 – 27
ADC Input Capacitance

A Vth2
σ  Vth  
2
Cg  10 fF / μm2
WL

• N = 6 bits → 63 comparators
N (bits) # of comp. Cin (pF)
• VFS = 1 V → 1 LSB = 16 mV
6 63 3.9
• σ = LSB/4 → σ = 4 mV
8 255 250
• AVT0 = 10 mV·μm → L = 0.24 μm,
10 1023 ??!
W = 26 μm

• Small Vos leads to large device sizes, hence large area and power
• Large comparator leads to large input capacitance, difficult to drive and difficult to m
aintain tracking bandwidth

– 28 – 28
Refernces
 Professor Boris Murmann Course slides 2012,
Stanford University- EE315B course
 Dr. Reza Lotfi, ADC course slides 2008.

29