Microelectronic Engineering 72 (2004) 273–277

www.elsevier.com/locate/mee

Charge trapping and detrapping in HfO2 high-j gate stacks

E.P. Gusev *, C. DÕEmic, S. Zafar, A. Kumar
IBM Semiconductor Research and Development Center (SRDC), IBM Thomas J. Watson Research Center,
Yorktown Heights, NY 10598, USA

Abstract

We report on charge transfer (trapping and detrapping) dynamics in ultrathin poly-Si gated NFET devices with
ultrathin HfO2 high-j gate dielectrics deposited by atomic layer deposition (ALD). The focus of this work is twofold: (i)
to investigate the role of processing on charge trapping in the ALD HfO2 stacks and (ii) to study trapped charge
(in)stability (i.e., detrapping) as a function of temperature, gate bias and light illumination. The kinetics of both
trapping and detrapping suggest the existence of more than one kind of existing traps with their energy levels located
deep in the forbidden gap of the insulator.
Ó 2004 Elsevier B.V. All rights reserved.

Keywords: High-j gate dielectrics; Charge trapping; HfO2 ; Atomic layer deposition

1. Introduction understood and solved for successful high-j inte-

The search for high dielectric constant (high-j)
materials for near-future gate dielectrics in MOS
ULSI devices is currently an enormous materials
and technological challenge [1,2]. HfO2 -based
materials are under intense investigation and op-
timization due to their high dielectric constant
(
20 vs. 3.8 for SiO2 ), wide band gap/barrier
height and good thermal stability. While HfO2
(and other high-j candidates) show a desired effect
of significantly reduced gate tunneling (leakage)
current, there is still a number of fundamental is-
sues, such as fixed charge, reduced channel mo-
bility and trapped charge, which have to be
*
Corresponding author.
E-mail address: gusev@us.ibm.com (E.P. Gusev).
gration into the Si CMOS technology [2,3].
Charge trapping in high-j gate stacks is known
to be more severe compared to conventional SiO2 -
based gate dielectrics [3]. It is believed to happen
due to filling of pre-existing traps, unlike SiO2
where the concentration of pre-existing traps is
very low (
1010 cm2 or less) and trap creation is
the dominant mechanism. Charge trapping is a
major device reliability issue since it causes
threshold voltage (Vt ) shifts and drive current
degradation over device operation time. It also
precludes accurate mobility (inversion charge)
measurements due to a distortion of C–V curves.
In this work, we explore the kinetics of electron
trapping and detrapping in poly-Si gated HfO2
gate stacks. Special focus is given to the effects of
processing (specifically interface engineering, post-
deposition anneals and thermal budget for dopant
activation anneals) on charge trapping behavior.

0167-9317/$ - see front matter Ó 2004 Elsevier B.V. All rights reserved.
doi:10.1016/j.mee.2004.01.003
274 E.P. Gusev et al. / Microelectronic Engineering 72 (2004) 273–277
While charge trapping is well documented in the
recent literature [3–10], detrapping phenomena are
not. This motivated us to investigate discharging
in the high-j stacks in more detail.
2. Experimental
Ultrathin HfO2 films were grown by atomic
layer deposition at 300 °C using the HfCl4 and
H2 O chemistry [11,12]. Physical thickness of the
high-j layer was in the 2–6 nm range. The HfO2
layers were deposited on different sub-1 nm inter-
layers on Si(1 0 0): chemical oxides and thermally
grown (oxy)nitrides. High-j deposition step was
followed by a densification anneal in oxygen or
nitrogen ambients. After that, standard CMOS
processing with activation anneals in the 900–1000
°C range was utilized to fabricate poly-Si gated
devices. Equivalent electrical thickness of most
measured stacks was in the 1.5–2 nm range (with
quantum mechanical corrections taken into ac-
count). More details on device fabrication and
electrical and physical characterization can be
found elsewhere [3].
Charge trapping and detrapping were studied
by measuring threshold voltage shift (Vt ) of high-
frequency (100 kHz) capacitance–voltage (C–V)
curves as a function of charging or discharging
time (or injected charge) by using a pulsing (also
known as ‘‘stress and sense’’) technique shown in
Fig. 1 and also described in [3,9,10]. Fresh devices
were used for each stress measurement. One im-
Fig. 1. Illustration of the pulsing technique used for charge
trapping or detrapping measurements.
Fig. 2. Threshold voltage shift due to electron trapping from
Cg –Vg measurements. Stress conditions correspond to substrate
injection.
portant methodological comment we would like to
make, before discussing results, is that charge
trapping cannot be accurately evaluated from gate
leakage Ig (or SILC, DIg =Ig ) or hysteresis mea-
surements. One can see a significant Vt shift (
+80
meV) in the Cg –Vg measurements (Fig. 2) whereas
there in no considerable shift (<4 meV) in the gate
current (Ig ) curves on same devices stressed under
identical conditions (Vstress ¼ 1.5 V for 1 h, Qinj
4
C/cm2 ). This is also true for the C–V hysteresis
analysis – sometimes stacks with a small hysteresis
nevertheless show a significant charge trapping.
Finally, we note that the pulsing technique used in
our work has time resolution on the order of
several seconds and is especially useful to investi-
gate long-term Vt instability and reliability, as
described in detail in [10].
3. Results and discussion
Typical charge trapping data is shown in Fig. 3
(as a function of stress time) and in Fig. 4 (as a
function of injected charge, that was calculated
from gate current measurements). For a given
stack thickness, these Vt shifts correspond to
trapped charge density on the order of 1011 –1012
cm2 . One can see from the semi-log plots that Vt
shift due to electron trapping follows a power-law
dependence, consistent with recently proposed
 E.P. Gusev et al. / Microelectronic Engineering 72 (2004) 273–277
Fig. 3. Charge trapping in an NFET device with a HfO2 /oxy-
nitride stack stressed at different temperatures.
Fig. 4. Same dataset as Fig. 3 plotted as a function of injected
charge density.
model of charge trapping in high-j dielectric
stacks [9]. The model assumes a spectrum of pre-
existing trap states within the gate stack with a
relatively board energy (and trapping cross-sec-
tion) distributions. The model yields the following
expression for the threshold voltage shift over
b
stress time (at short times), DVt ¼ DVmax ðt=s0 Þ ,
where s0 ¼ e=ðJ0 r0 Þ. The parameter of b ð0 <
b < 1Þ characterizes the broadness of the trap
distribution, r0 is a characteristic electron capture
cross-section, and J0 is gate current density.
One can see from Fig. 3, charge trapping vs.
time initially accelerates with increasing tempera-
275
ture. This is caused by increased gate leakage
current which is known to have a stronger de-
pendence on temperature in high-j stacks due to
other than direct tunneling components of the gate
current (e.g., trap-assisted tunneling, Frankel–
Poole, etc.). After normalizing the x-axis of Fig. 3
to injected charge (Fig. 4), threshold voltage shift
becomes almost independent on temperature, ex-
cept for the higher temperature region. At T > 200
°C, thermally induced de-trapping results in
smaller Vt shifts observed in our measurements.
Next we discuss the effect of processing on
charge trapping. One important question to un-
derstand is to what extend charge trapping in high-
j stacks is intrinsic to metal oxides (e.g., HfO2
used in this study) and to what extend it is process-
related. For example, it was found that moisture
absorption within the high-j stack is an important
processing parameter that makes charge trapping
worse [13]. In this study we investigated the role of
interface engineering, post-deposition anneals and
activation anneals after poly-Si gate deposition.
We also found that charge trapping (after nor-
malization to injected charge density) becomes
worse with increasing HfO2 oxide thickness, sug-
gesting the presence of a ‘‘bulk’’ component of
charge trapping.
As illustrated in Fig. 5, charge trapping does
depend on interface quality. Hafnium oxide
deposited on thermally pre-grown oxynitride
Fig. 5. Threshold voltage shift as a function of stress time (at
1.5 V) for HfO2 with different sub-1 nm interfaces. Vt shift vs.
Qinj shows the same trend.
276 E.P. Gusev et al. / Microelectronic Engineering 72 (2004) 273–277
interfaces (with varied nitrogen content) are su-
perior to a chemical oxide. The effect of annealing
after HfO2 deposition step is shown in Fig. 6. Once
again, one can see some improvement of charge
trapping after rapid thermal annealing in nitrogen.
However, the improvement is still insufficient
compared to very little charge trapping in con-
ventional SiO2 insulators in this thickness range.
High-j gate stacks are known to be less ther-
mally stable at high temperatures, unlike the poly/
SiO2 /Si system. Therefore we investigated charge
trapping in the stacks after high temperature poly-
Si activation anneals (at 900–1000 °C for 5–15 s),
that may degrade stack quality. Our data (not
shown) suggests that the temperature of activation
anneals does not have an observable effect on
charge trapping.
Up to this point, we discussed electron trapping
caused by direct tunneling from inversion layer of
silicon into the gate insulator. Under certain con-
ditions, carriers with excess energy (so called ‘‘hot’’
carriers) can be injected into the dielectric. This
process is more probable in high-j stacks due to a
lower barrier height at the injector interface. In
general, we observed more severe charge trapping
during ‘‘hot’’ charge injection. Furthermore, hot
carriers may induce new trap creation in the high-j
stack in addition to pre-existing trap centers. More
details on charge trapping under these extreme
conditions can be found in our recent work [10].
Fig. 6. Comparison of oxygen (furnace) and nitrogen (rapid
thermal) annealing on charge trapping.
Fig. 7. Kinetics of charging (at 1.5 V), discharging (at )0.9 V)
and 2nd charging (again at 1.5 V).
Finally, we investigate how stable the trapped
electrons are. One of the reasons for performing
this set of discharging experiments was to better
understand the nature of the trapping sites in high-
j stacks. Our detrapping studies suggest that most
charges are trapped at deep levels in the forbidden
gap – a relatively slow discharging relaxation over
time was observed. Enhanced decay rate was seen
when an opposite polarity gate voltage was applied
to the stack (up to the complete discharging,
Fig. 7). Substrate temperature increase and device
illumination by light also accelerate detrapping,
although to a lesser extent. Our results suggest that
more than one type of (existing) traps are re-
sponsible for charge trapping and that some new
trap creation may take place during charge injec-
tion under certain conditions. More experimen-
tal results on charge detrapping can be found
elsewhere [14].
4. Summary
We investigated an important issue of charge
trapping and detrapping in poly-Si gated high-j
stacks with an ultrathin ALD grown HfO2 di-
electric. The emphasis was given to: (i) the role of
processing in reducing charge trapping and (ii)
detrapping kinetics. We observed some improve-
ment in charge trapping, in particular, by interface
engineering and post-deposition annealing, but
still insufficient compared to the SiO2 benchmark.
 E.P. Gusev et al. / Microelectronic Engineering 72 (2004) 273–277
Detrapping studies (carried out under various gate
bias conditions, wafer temperatures, and light il-
lumination) revealed more than one kind of traps
with energy levels deep in the forbidden gap of the
insulator.
Acknowledgements
The authors thank D. Buchanan, M. Fischetti,
E. Cartier, D. DiMaria and S. Guha for fruitful
discussions, and G. Singco and B. Linder for
software support.
References
[1] M.L. Green, E.P. Gusev, R. Degraeve, E. Garfunkel, J.
Appl. Phys. 90 (2001) 2057.
[2] G.D. Wilk, R.M. Wallace, J.M. Anthony, J. Appl. Phys. 89
(2001) 5243.
277
[3] E.P. Gusev, D.A. Buchanan, E. Cartier, et al., IEDM
Tech. Digest (2001) 451.
[4] M. Houssa, V.V. AfanasÕev, A. Stesmans, Appl. Phys. Lett.
77 (2000) 1885.
[5] M. Houssa, V.V. AfanasÕev, A. Stesmans, M.M. Heyns,
Appl. Phys. Lett. 79 (2001) 3134.
[6] J.R. Chavez, R.A.B. Devine, L. Koltunski, J. Appl. Phys.
90 (2001) 4284.
[7] W.J. Zhu, T.P. Ma, S. Zafar, T. Tamagawa, IEEE Electron
Device Lett. 23 (2002) 597.
[8] A. Kerber, E. Cartier, L. Pantisano, M. Rosmeulen, R.
Degraeve, T. Kauerauf, G. Groeseneken, H.E. Maes, U.
Schwalke, IRPS, April 2003.
[9] S. Zafar, A. Callegari, E.P. Gusev, M.V. Fischetti, J. Appl.
Phys. 93 (2003) 9298.
[10] A. Kumar, T.H. Ning, M.V. Fischetti, E.P. Gusev, VLSI
Sympos. Tech. Digest (2002) 152;
J. Appl. Phys. 94 (2003) 1728.
[11] T. Suntola, Mater. Sci. Rep. 4 (1989) 261.
[12] E.P. Gusev, E. Cartier, D.A. Buchanan, M.A. Gribelyuk,
M. Copel, H. Okorn-Schmidt, C. DÕEmic, Microelectron.
Eng. 59 (2001) 341.
[13] S. Zafar, S. Callegari, V. Narayanan, S. Guha, Appl. Phys.
Lett. 81 (2002) 2608.
[14] E.P. Gusev, C. DÕEmic, Appl. Phys. Lett. 83 (2003) 5223.