SEQUENTIAL LOGIC CIRCUITS

Till now we studied the logic circuits whose outputs at any instant of time depend only on the input
signals present at that time are known as combinational circuits. Moreover, in a combinational
circuit, the output appears immediately for a change in input, except for the propagation delay
through circuit gates.

On the other hand, the logic circuits whose outputs at any instant of time depend on the present
inputs as well as on the past outputs are called sequential circuits. In sequential circuits, the output
signals are fed back to the input side. A block diagram of a sequential circuit is shown in Figure
below:-

Asynchronous sequential circuit: A sequential circuit whose behavior depends upon the
sequence in which the input signals change is referred to as an asynchronous sequential circuit.
The output will be affected whenever the input changes. The commonly used memory elements in
these circuits are time-delay devices. There is no need to wait for a clock pulse. Therefore, in
general, asynchronous circuits are faster than synchronous sequential circuits. However, in an
asynchronous circuit, events are allowed to occur without any synchronization. And in such a case,
the system becomes unstable. Since the designs of asynchronous circuits are more tedious and
difficult, their uses are rather limited. The memory elements used in sequential circuits are flip-
flops which are capable of storing binary information.

Synchronous sequential circuit: A sequential circuit whose behavior can be defined from the
knowledge of its signal at discrete instants of time is referred to as a synchronous sequential circuit.
In these systems, the memory elements are affected only at discrete instants of time. The
synchronization is achieved by a timing device known as a system clock, which generates a
periodic train of lock pulses. The outputs are affected only with the application of a clock pulse.

Difference between synchronous and asynchronous circuit

Asynchronous Sequential Circuits synchronous Sequential Circuits

These circuits do not use a clock signal for These circuits use a clock signal to
synchronization. synchronize the operation of flip-flops.
 State changes can occur at any time, based on Changes in state occur only at specific points
the changing inputs. in time, usually triggered by the rising or
falling edge of the clock.

Timing is not as critical, and elements can Timing is critical, and all elements change
change state independently of one another. state simultaneously.

A latch is a digital circuit element used to store one or more bits of information. It is a bistable
multivibrator, meaning it has two stable states, typically denoted as "set" and "reset" or "1" and
"0". Unlike flip-flops, latches do not have a clock input and can change state as soon as their inputs
change.

There are various types of latches, and some common ones include:

SR Latch (Set-Reset Latch): It has two inputs, Set (S) and Reset (R), and two outputs, Q and Q'
(complement of Q). The latch holds its state until one of the inputs is activated, activated, causing
the latch to change state.
 SR latch using NOR gate
INPUTS OUTPUT ACTIONS
S
S R Q Q̅
0 0 Q Q̅ memory
0 1 0 1 Reset
1 0 1 0 set
1 1 0 0 Not used

When e implement the using NAND gate the input were reverse and the truth table is as follows

SR latch using NAND gate

INPUTS OUTPUT ACTIONS
S
S R Q Q̅
0 0 1 1 Not used
0 1 0 1 Reset
1 0 1 0 set
1 1 Q Q̅ memory
Latches are often used in digital circuits for short-term storage of data. However, they lack the
synchronous behavior of flip-flops, which means they are more susceptible to glitches and changes
in input states. For applications requiring more controlled and predictable behavior, flip-flops are
often preferred over latches.

FLIP-FLOP

A flip-flop is a digital circuit element used for storing binary information. It is a bistable
multivibrator, meaning it has two stable states, typically denoted as "set" and "reset" or "1" and
"0". Flip-flops are fundamental building blocks in digital circuits and play a crucial role in memory
storage, data processing, and sequential logic.

There are several types of flip-flops, with the most common being:
SR Flip-Flop (Set-Reset Flip-Flop): It has three inputs, Set (S) and Reset (R), and a clock input
and two outputs, Q and Q' (complement of Q). The flip-flop holds its state until one of the inputs
is activated, causing it to change state. The SR flip-flop has the same truth table as SR latch

SR flip-flop truth table

INPUTS OUTPUT ACTIONS

S
S R Q Q̅
0 0 Q Q̅ memory
0 1 0 1 Reset
1 0 1 0 set
1 1 0 0 Not used

Characteristic Table of an S-R Flip-flop

INPUTS OUTPUTS
Qn S R Qn+1
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 X
1 0 0 1
1 0 1 0
1 1 0 1
 1 1 1 x

D Flip-Flop (Data Flip-Flop): It has two input, a data input (D) and a clock input (C or CLK),
and two outputs, Q and Q' (complement of Q). The D flip-flop stores the input data at the rising or
falling edge of the clock signal.

D flip-flop Truth Table

INPUT OUTPUT ACTIONS

S
D Q Q̅
0 0 1 Reset
1 1 0 set
Characteristic table of D Flip-Flop

INPUTS OUTPUTS
Qn D Qn+1
0 0 0
0 1 1
1 0 0
1 1 1
JK Flip-Flop: It has three inputs, J, K, and a clock input. The JK flip-flop combines the
functionality of SR and D flip-flops, allowing for toggling between states when both J and K are
active.

JK Flip-Flop Truth Table

INPUTS OUTPUT ACTIONS

S
J K Q Q̅
0 0 Q Q̅ memory
0 1 0 1 Reset
1 0 1 0 set
1 1 Q̅ Q Toggle
Characteristic Table o JK Flip-Flp

INPUTS OUTPUTS
Qn J K Qn+1
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 1
1 0 0 1
1 0 1 0
 1 1 0 1
1 1 1 0

T Flip-Flop (Toggle Flip-Flop): It has a toggle input (T) and a clock input. The T flip-flop toggles
its state (changes from 0 to 1 or vice versa) when the clock signal transitions.

Flip-flops are crucial in the design of sequential logic circuits, such as memory units, counters,
and state machines. They are also used to store temporary data and synchronize the flow of
information within digital systems. Flip-flops are characterized by their ability to maintain a state
until explicitly changed, making them essential for digital storage and computation.

A race-around condition, also known as a race condition or feedback race, is a phenomenon that
can occur in digital circuits, particularly in sequential logic circuits, leading to undesirable and
unpredictable behavior. This condition arises when there is a feedback loop in the circuit, and
signals race against each other, causing the system to oscillate or enter an unpredictable state.

Master-Slave J-K Flip-flop

A master-slave (M-S) flip-flop is shown in Figure below. Basically, a master-slave flip-flop is a

system of two flip-flops—one being designated as master and the other is the slave. From the
figure below we see that a clock pulse is applied to the master and the inverted form of the same
clock pulse is applied to the slave.

When CLK = 1, the first flip-flop (i.e., the master) is enabled and the outputs Qm and Q'm respond
to the inputs J and K according to the table shown in Figure 7.13. At this time the second flip-flop
(i.e., the slave) is disabled because the CLK is LOW to the second flip-flop. Similarly, when CLK
becomes LOW, the master becomes disabled and the slave becomes active, since now the CLK to
it is HIGH. Therefore, the outputs Q and Q' follow the outputs Qm and Q'm respectively. Since the
second flip-flop just follows the first one, it is referred to as a slave and the first one is called the
master. Hence, the configuration is referred to as a master-slave (M-S) flipflop.

EXCITATION TABLE OF A FLIP-FLOP

From the characteristic table of a flip-flop, since this table refers to the operational characteristics
of the flip-flop. But in designing sequential circuits, we often face situations where the present
state(PS) & the next state(NS) of the flip-flop is specified, and we have to find out the input
conditions that must prevail for the desired output condition. By present and next states we mean
to say the conditions before and after the clock pulse respectively. For example, the output of an
S-R flip-flop before the clock pulse is Qn = 1 and it is desired that the output does not change when
the clock pulse is applied. Now from the characteristic table of an S-R flip-flop, we obtain the
following conditions:

1. S = R = 0

2. S = 0, R = 1

We come to the conclusion from the above conditions that the S input must be 0, whereas the R
input may be 0 or 1 (i.e., don’t-care). Similarly, for all possible situations, the input conditions can
be found out. A tabulation of these conditions is known as an excitation table. The table below
gives the excitation table for S-R, D, J-K, & T flip-flops. These conditions are derived from the
corresponding characteristic tables of the flip-flops.

INTERCONVERSION OF FLIP-FLOPS

 Identify the available and required flip flop

 Make a characteristic table of the required flip flop
 Make the excitation table of the available flip flop
 Write the Boolean expression of the available flip flop
 Draw the circuit

Design procedures for clocked sequential circuits

 State diagram is given

 Obtain the state table
 Reduce the number of state if possible
 Do state assignment( if required)
 Determine the number of flip-flops required and assign a letter
 Decide the type of flip-flop to be used
 Derive the excitation table
 Obtain the expression for circuit input
 Draw the circuit

Moore State Machine:

 Output Dependency: Outputs depend only on the current state.

  Output Changes: Outputs change only when transitioning between states.
 Complexity: Generally simpler and easier to design.
 Use Cases: Suitable for applications where the outputs are primarily determined by the
current state, and timing is not critical.
 Example: Elevator control systems, vending machines.

Mealy State Machine:

 Output Dependency: Outputs depend on both the current state and inputs.
 Output Changes: Outputs can change asynchronously with state changes.
 Complexity: Can be more complex due to the direct influence of inputs on outputs.
 Use Cases: Suitable for applications where outputs need to respond quickly to input
changes and where a more dynamic response is desired.
 Example: Traffic light controllers, communication protocols.
 Comparison:
 Output Characteristics: Moore machines have outputs that depend only on the current
state, while Mealy machines have outputs that depend on both the current state and inputs.
 Timing: Moore machines are often simpler and suitable for applications where timing is
less critical. Mealy machines, with their dynamic response to inputs, are suitable for
situations requiring quick output changes.
 Design Complexity: Moore machines tend to be simpler to design, making them more
suitable for applications with straightforward logic requirements. Mealy machines, while
more flexible, can be more complex due to input-dependent output changes.

REGISTERS
A register is a group of binary storage cells capable of holding binary information. A group of flip-
flops constitutes a register, since each flip-flop can work as a binary cell. An n-bit register, has n
flip-flops and is capable of holding n-bits information. In addition to flip-flops a register can have
a combinational part that performs data-processing tasks.
4-Bit Shift Register: A 4-bit shift register is a sequential digital circuit that can shift data bits
through its four stages. It consists of four flip-flops connected in series, and each flip-flop holds
one bit of data. The operation involves shifting data either to the left or right based on a clock
signal.

Shift registers are classified into the following types:

1. SISO (Serial In Serial Out)
2. SIPO (Serial In Parallel Out)
3. PISO (Parallel In Serial Out)
4. PIPO (Parallel In Parallel Out)
5. Bi-directional Shift Register
6. Universal Shift Register
Let’s examine each mode in detail:

1] SISO (Serial In Serial Out):

 This shift register allows serial input and produces a serial output. As there is only one
output, it delivers 1 bit at a time in a serial pattern. A 4-bit shift register using D flip-flops is
illustrated below, with all flip flops connected in a serial manner and synchronized by the
same clock signals.

 Initially, all flip flops are in a reset condition (Q3=Q2=Q1=Q0=0). If the input data series is
1111, the first LSB bit (1) is considered as Din and is applied to the input of the first flip flop
(D3). The output of the first flip flop is connected to the input of the second flip flop, and so
 on. The stored word in the register is updated on each falling edge of the clock signal,
resulting in a sequential output.

 Before applying the clock signal, the output is initialized to Q3Q2Q1Q0=0000. Upon
applying the clock signal, during the first falling edge of the clock, Flip-Flop 3 (FF3) is
triggered, updating the stored word in the register to Q3Q2Q1Q0=1000.

 Subsequently, at the next negative edge of the clock, Flip-Flop 2 (FF2) is set, leading to a
modification of the stored word to Q3 Q2 Q1 Q0=1100.

 Upon the occurrence of the third negative clock edge, Flip-Flop 1 (FF1) is activated,
resulting in an output modification to Q3 Q2 Q1 Q0=1110.
 Finally, with the arrival of the fourth negative clock edge, the stored word in the register
becomes Q3 Q2 Q1 Q0=1111.
2] SIPO (Serial In Parallel Out):

 The Serial-In-Parallel-Out (SIPO) shift register facilitates serial input and generates a parallel
output. Illustrated below is a 4-bit SIPO shift register utilizing D flip-flops, where each flip-
flop is interconnected in a serial fashion and synchronized by identical clock signals. The
output of one flip-flop is linked to the input of the subsequent flip-flop, forming a serial
chain.
 Initially, all flip-flops are reset to Q3=Q2=Q1=Q0=0. Taking a 4-bit input data series, such as
1011, the first Least Significant Bit (LSB) bit (0) is considered as “Din” and is applied to the
input of the initial flip-flop. Each flip-flop’s output is connected to a parallel output. The
register’s stored word is updated with each falling edge of the clock signal, resulting in a
parallel output.

 To commence, all flip-flops are set to a reset state: Q3 Q2 Q1 Q0 = 0000. Applying the first
serial input bit (1) to the first flip-flop’s input, on the falling edge of the clock, the first flip-
flop is triggered, latching the data. The shift register now holds Q3 Q2 Q1 Q0 = 1 0 0 0.

 Subsequently, applying the second serial input bit (1) to the first flip-flop’s input, the first
flip-flop is triggered again on the falling edge of the clock, and the data is latched. The shift
register now holds Q3 Q2 Q1 Q0 = 1 1 0 0.

 Continuing the process for the third and fourth serial input bits (0 and 1), after each clock
edge, the shift register holds:
Clock Edge 3: Q3 Q2 Q1 Q0 = 0 1 1 0.
Clock Edge 4: Q3 Q2 Q1 Q0 = 1 0 1 1.

 After all four clock edges, the final parallel output is Q3 Q2 Q1 Q0 = 1011. This iterative
process ensures that the parallel output consistently represents the entire serial input data
stream.
 SIPO shift registers find common application when there is a need to convert a serial data
stream into a parallel format for subsequent processing in a digital system.

3] PISO (Parallel In Serial Out):

 The Parallel-In-Serial-Out (PISO) shift register is a digital circuit that accepts parallel input
data and produces a serial output. In contrast to the Serial-In-Parallel-Out (SIPO) shift
register, the PISO configuration is useful when data needs to be shifted out serially while
being presented in parallel at the input. Consider a 4-bit PISO shift register using D flip-
flops.
 Initially, all flip-flops are reset (Q3=Q2=Q1=Q0=0). If the parallel input data is 1011, each
bit is simultaneously applied to the corresponding flip-flop inputs. Illustrated below is a 4-bit
SIPO shift register utilizing D flip-flops. Here, Output of previous Flip Flop is connected to
the input of the next one via a combinational circuit. Here we also have shift/Load bar
terminal in the circuit digaram.

 In Parallel-In-Serial-Out (PISO) shift registers, there are two primary modes of operation: the
“load” mode and the “shift” mode. These modes determine how data is handled in the shift
register.

 Let’s consider a 4-bit PISO shift register in both load and shift modes:

1. Load Mode:
In the load mode, the PISO shift register accepts parallel input data. During this mode, the
parallel input data is loaded into the flip-flops simultaneously. Each flip-flop stores one bit of
the parallel input data. This mode is typically activated by a control signal (e.g., Load/Shift
control). Initialize all flip-flops to a reset state: Q3 Q2 Q1 Q0 = 0000. Apply parallel input
 data (e.g., 1011) to the flip-flop inputs.
Activate the load control signal. On the rising or falling edge of the clock, the parallel input
data is loaded into the flip-flops.
Result after load: Q3 Q2 Q1 Q0 = 1011.

2. Shift Mode:
In the shift mode, the PISO shift register shifts the stored data out serially. The stored parallel
data is shifted out bit by bit, starting from the Most Significant Bit (MSB) to the Least
Significant Bit (LSB).
This mode is activated by a different control signal or the absence of a load signal. The
shifting occurs on each clock edge, either rising or falling, depending on the design.
Deactivate the load control signal (or activate the shift control signal). On each subsequent
clock edge, the stored data is shifted out serially. Result after shift: Serial output = 1011.

 Now, let’s delve into the operational transition of the combinational circuit as it switches
from the load mode to the shift mode.

 In the configuration, there is a Shift/Load bar terminal with two lines, one of which is
connected to a NOT gate, providing inverse inputs to both lines. A circuit, comprising one
OR gate and two AND gates, is interlinked. Pay close attention to the connections: notice
how the output of the first flip-flop is linked to the input of an AND gate, and how the
Shift/Load lines are connected to the AND gates, along with input lines B3, B2, B1, and B0.
Initially, the shift register operates in load mode to load the data. For the Parallel-In-Serial-
Out (PISO) shift register to function in load mode, the Shift/Load bar input must be 0, and
for it to operate in shift mode, it must be 1.

 Refer to the diagram below, where the AND gates receive input values based on the
shift/load input. Following the logic of AND gates, if any input is 0, the output is 0.
Consequently, the output of AND gates 1, 3, 5 will be 0. Conversely, if any input is 1, the
other terminal serves as the output. Thus, the output of AND gates 2, 4, 6 will be B2, B1, B0,
respectively. Following the logic of the OR gate, the output of OR gate 1, 2, 3 will be B2,
B1, B0, respectively. This output is then fed into the input of the flip-flop. Flip-flop 1 directly
 takes the input B3. This process facilitates loading the input B3B2B1B0 into the flip-flops.
Subsequently, after the clock input, the input data is available at the output, resulting in
Q3Q2Q1Q0 = B3B2B1B0.

 During shift mode, the Shift/Load bar terminal is set to 1. The diagram illustrates how the
AND gates receive inputs based on the shift/load line inputs. According to the AND gate’s
operation, the output of AND gates 2, 4, 6 will be 0, and the output of AND gates 1, 3, 5 will
be Q3Q2Q1. Following the OR gate’s logic, the output of OR gate 1, 2, 3 will be Q3Q2Q1,
respectively. This output is then connected to the input of the flip-flop, facilitating the shift of
data in the PISO shift register.
4] PIPO (Parallel In Parallel Out):

 A Parallel-In-Parallel-Out (PIPO) shift register is a type of digital shift register that allows
parallel input data to be loaded into the register and simultaneously produces parallel output
data. Unlike Serial-In-Serial-Out (SISO) or Parallel-In-Serial-Out (PISO) shift registers, a
PIPO shift register enables parallel transfer of data both at the input and output.
Here’s a brief overview of how a 4-bit PIPO shift register works:
 Initially, all flip-flops in the PIPO shift register are set to a reset state (Q3 Q2 Q1 Q0 = 0000).
Apply the parallel input data (D3 D2 D1 D0) to the respective inputs of each flip-flop. Each
flip-flop stores one bit of the parallel input data. On the rising or falling edge of the clock
signal (depending on the design), the parallel input data is latched into the flip-flops
simultaneously.

 The data in all flip-flops are available simultaneously at the parallel outputs (Q3 Q2 Q1 Q0).
The PIPO shift register retains the parallel data until new parallel data is provided and
clocked in.

 A key characteristic of the PIPO shift register is its ability to perform parallel transfers at
both the input and output stages. This makes it suitable for applications where parallel data
needs to be maintained and processed concurrently.

5] Bidirectional Shift Register:

 A bidirectional shift register is a sequential logic circuit that can shift data in both directions
— left and right, depending on the control signals. A 4-bit Bidirectional shift register using D
flip-flops is illustrated below. This versatile circuit adapts its behavior based on the value of
 “M,” where M=1 designates operation as a Shift Right Register, and M=0 configures it as a
Shift Left Register.

 Examine the connections closely, particularly focusing on the intricate relationship between
the output of the first flip-flop and the input of an AND gate. Additionally, observe how the
control signal lines, denoted by “M,” intricately interface with the AND gates. These
connections are meticulously designed to ensure precise control over the bidirectional shift
register’s functionality.

 M=1 (Shift Right Register):

When the control signal, denoted as “M,” is set to 1, the bidirectional shift register operates
as a Shift Right Register.
Refer to the diagram above, where the AND gates receive input values based on the control signal
“M.” Applying the logic of AND gates, if any input is 0, the output is 0. Consequently, the
outputs of AND gates 2, 4, 6, and 8 will be 0. Conversely, if any input is 1, the opposite terminal
serves as the output. Thus, the outputs of AND gates 1, 3, 5, and 7 will be DR, Q3, Q2, and Q1,
respectively. Following the logic of the OR gate, the outputs of OR gates 1, 2, 3, and 4 will be
DR, Q3, Q2, and Q1, respectively. This collective output is then directed into the input of the flip-
flop. Consequently, the data undergoes a rightward shift, effectively realizing the functionality of
a Shift Right Register.

 M=0 (Shift Left Register):

Conversely, when the control signal “M” is set to 0, the bidirectional shift register transforms
into a Shift Left Register.
Refer to the diagram above, where the AND gates once again receive input values based on the
control signal “M.” Employing the AND gate logic, if any input is 0, the output is 0.
Consequently, the outputs of AND gates 1, 3, 5, and 7 will be 0. Conversely, if any input is 1, the
opposite terminal becomes the output. Thus, the outputs of AND gates 2, 4, 6, and 8 will be Q2,
Q1, Q0, and DL, respectively. Following the logic of the OR gate, the outputs of OR gates 1, 2, 3,
and 4 will be Q2, Q1, Q0, and DL, respectively. Subsequently, this combined output is fed into
the input of the flip-flop. In this manner, the data experiences a leftward shift, effectively
embodying the characteristics of a Shift Left Register.

6] Universal Shift Registers:

 Previously, we explored the functionalities of shift registers that enable left and right data
shifting, as well as data loading. However, imagine the need for a shift register that
seamlessly integrates all these capabilities into a single, comprehensive unit. Introducing the
universal shift register, a versatile solution that combines the abilities to shift data both left
and right, while also facilitating simultaneous data loading.
 The universal shift register marks a significant advancement by consolidating the features of
various shift registers into a unified design. It offers the flexibility to perform left and right
shifts as well as parallel loading, making it a powerful and adaptable component in digital
systems. Below diagram shows a universal shift register using 4 D flip flops:

 The universal shift register is designed to execute four distinct functionalities:

1. Hold

2. Shift Right

3. Shift Left

4. PIPO (Parallel Input Parallel Output)

 The selection of a specific operation is determined by the control signals S0 and S1. To
facilitate these operations, four 4:1 multiplexers (MUX) are employed, utilizing the outputs
Q3, Q2, Q1, and Q0.
1. In Hold mode, where data should remain static even after the application of a clock input, the
output is looped back to the input, effectively connecting it to I0.

2. For the Shift Right operation, necessitating a rightward movement of data, connections are
established from Q0, Q1, Q2, and Q3 to I1, as depicted in the accompanying diagram.

3. Conversely, for the Shift Left operation, involving a leftward shift, connections from Q2, Q1,
Q0, and Q3 are linked to I2.

4. To fulfill the requirements of the PIPO mode, where data needs to be directly connected to
the inputs, D3, D2, D1, and D0 are directly linked to I3. This comprehensive approach
ensures that the universal shift register seamlessly performs all the specified functions.

Potential Applications:

 Serial-to-Parallel Conversion: Convert a serial stream of data into parallel form for
processing.
 Data Storage and Retrieval: Used for temporary data storage in applications like
memory buffers.
 Shift and Rotate Operations: Implement shift and rotate operations in digital systems.
 LED Displays: Control LED displays by sequentially activating LEDs.
 Serial Communication: Used in serial communication protocols for data transmission.
INTRODUCTION TO MICROPROCESSOR AND MICROCOMPUTER ARCHITECTURE

A microprocessor is a programmable electronics chip that has computing and decision making
capabilities similar to central processing unit of a computer. Any microprocessor based systems
having limited number of resources are called microcomputers. Nowadays, microprocessor can be
seen in almost all types of electronics devices like mobile phones, printers, washing machines etc.
Microprocessors are also used in advanced applications like radars, satellites and flights. Due to
the rapid advancements in electronic industry and large scale integration of devices results in a
significant cost reduction and increase application of microprocessors and their derivatives.

Microprocessor:

Functionality: A microprocessor is the central processing unit (CPU) of a computer. It performs

general-purpose processing tasks and is the brain of a computer system.

Components: It typically requires external components such as memory, input/output devices,

and other peripherals to function.

Applications: Microprocessors are used in computers and high-level processing systems.

Versatility: Microprocessors are designed for a wide range of applications and tasks.

A Microcontroller is a programmable digital processor with necessary peripherals. Both

microcontrollers and microprocessors are complex sequential digital circuits meant to carry out
job according to the program / instructions. Sometimes analog input/output interface makes a part
of microcontroller circuit of mixed mode(both analog and digital nature).

Microcontroller:

Functionality: Microprocessors are designed for general-purpose computing, while

microcontrollers are optimized for specific control applications.

Components: Microprocessors usually require external components, whereas microcontrollers

integrate the CPU, memory, and peripherals on a single chip.

Complexity: Microprocessors tend to be more complex, handling a wide range of tasks, while
microcontrollers are simpler and application-specific.
Applications: Microprocessors are used in computers and high-level systems, while
microcontrollers are common in embedded systems and IoT devices.

Bit: A bit is a single binary digit.

 Word: A word refers to the basic data size or bit size that can be processed by the arithmetic and
logic unit of the processor. A 16-bit binary number is called a word in a 16-bit processor.

 Bus: A bus is a group of wires/lines that carry similar information.

 System Bus: The system bus is a group of wires/lines used for communication between the
microprocessor and peripherals.

 Memory Word: The number of bits that can be stored in a register or memory element is called
a memory word.

 Address Bus: It carries the address, which is a unique binary pattern used to identify a memory
location or an I/O port. For example, an eight bit address bus has eight lines and thus it can address
28 = 256 different locations. The locations in hexadecimal format can be written as 00H – FFH.

 Data Bus: The data bus is used to transfer data between memory and processor or between I/O
device and processor. For example, an 8-bit processor will generally have an 8-bit data bus and a
16-bit processor will have 16-bit data bus.

 Control Bus: The control bus carry control signals, which consists of signals for selection of
memory or I/O device from the given address, direction of data transfer and synchronization of
data transfer in case of slow devices.

A typical microprocessor consists of arithmetic and logic unit (ALU) in association with control
unit to process the instruction execution. Almost all the microprocessors are based on the principle
of store-program concept. In store-program concept, programs or instructions are sequentially
stored in the memory locations that are to be executed. To do any task using a microprocessor, it
is to be programmed by the user. So the programmer must have idea about its internal resources,
features and supported instructions. Each microprocessor has a set of instructions, a list which is
provided by the microprocessor manufacturer. The instruction set of a microprocessor is provided
in two forms: binary machine code and mnemonics.

Microprocessor communicates and operates in binary numbers 0 and 1. The set of instructions in
the form of binary patterns is called a machine language and it is difficult for us to understand.
Therefore, the binary patterns are given abbreviated names, called mnemonics, which forms the
assembly language. The conversion of assembly-level language into binary machine-level
language is done by using an application called assembler.

A microprocessor's instruction set typically includes various types of instructions:

Arithmetic Instructions: Perform mathematical operations like addition, subtraction,

multiplication, and division.

Logical Instructions: Execute logical operations such as AND, OR, XOR, and NOT.

Data Transfer Instructions: Move data between registers, memory, and peripherals such as
MOV, LOAD.

Control Transfer Instructions: Direct the flow of program execution, including jumps, calls, and
returns.

Input/Output Instructions: Facilitate communication between the microprocessor and external

devices.

Compare and Branch Instructions: Compare data and alter the program flow based on the result.

Bit Manipulation Instructions: Modify individual bits within data.

Classification of Microprocessors: Based on their specification, application and architecture

microprocessors are classified.

Based on size of data bus:

 4-bit microprocessor

 8-bit microprocessor

 16-bit microprocessor
 32-bit microprocessor

 64-bit microprocessor

Based on application:

 General-purpose microprocessor- used in general computer system and can be used by

programmer for any application. Examples, 8085 to Intel Pentium.

 Microcontroller- microprocessor with built-in memory and ports and can be programmed for any
generic control application. Example, 8051.

 Special-purpose processors- designed to handle special functions required for an application.

Examples, digital signal processors and application-specific integrated circuit (ASIC) chips.

Based on architecture:

 Reduced Instruction Set Computer (RISC) processors

 Complex Instruction Set Computer (CISC) processors

Arithmetic and Logic Unit

The ALU performs the actual numerical and logical operations such as Addition (ADD),
Subtraction (SUB), AND, OR etc. It uses data from memory and from Accumulator to perform
operations. The results of the arithmetic and logical operations are stored in the accumulator.

Control Unit
This Generates signals on data bus, address bus and control bus within microprocessor to carry out
the instruction, which has been decoded. Typical buses and their timing are described as follows:

 Data Bus: Data bus carries data in binary form between microprocessor and other external units
such as memory. It is used to transmit data i.e. information, results of arithmetic etc between
memory and the microprocessor. Data bus is bidirectional in nature. The data bus width of 8085
microprocessor is 8-bit i.e. 28 combination of binary digits and are typically identified as D0 – D7.
Thus size of the data bus determines what arithmetic can be done. If only 8-bit wide then largest
number is 11111111 (255 in decimal). Therefore, larger numbers have to be broken down into
chunks of 255. This slows microprocessor.

 Address Bus: The address bus carries addresses and is one way bus from microprocessor to the
memory or other devices. 8085 microprocessor contain 16-bit address bus and are generally
identified as A0 - A15. The higher order address lines (A8 – A15) are unidirectional and the lower
order lines (A0 – A7) are multiplexed (time-shared) with the eight data bits (D0 – D7) and hence,
they are bidirectional.

 Control Bus: Control bus are various lines which have specific functions for coordinating and
controlling microprocessor operations. The control bus carries control signals partly unidirectional
and partly bidirectional. The following control and status signals are used by 8085 processor:

Evolution of Microprocessors

We can categorize the microprocessor according to the generations or according to the size of the
microprocessor:

First Generation (4 - bit Microprocessors)

The first generation microprocessors were introduced in the year 1971-1972 by Intel Corporation.
It was named Intel 4004 since it was a 4-bit processor.

It was a processor on a single chip. It could perform simple arithmetic and logical operations such
as addition, subtraction, Boolean OR and Boolean AND.

I had a control unit capable of performing control functions like fetching an instruction from
storage memory, decoding it, and then generating control pulses to execute it.
Second Generation (8 - bit Microprocessor)

The second generation microprocessors were introduced in 1973 again by Intel. It was a first 8 -
bit microprocessor which could perform arithmetic and logic operations on 8-bit words. It was
Intel 8008, and another improved version was Intel 8088.

Third Generation (16 - bit Microprocessor)

The third generation microprocessors, introduced in 1978 were represented by Intel's 8086, Zilog
Z800 and 80286, which were 16 - bit processors with a performance like minicomputers.

Fourth Generation (32 - bit Microprocessors)

Several different companies introduced the 32-bit microprocessors, but the most popular one is
the Intel 80386.

Fifth Generation (64 - bit Microprocessors)

From 1995 to now we are in the fifth generation. After 80856, Intel came out with a new processor
namely Pentium processor followed by Pentium Pro CPU, which allows multiple CPUs in a
single system to achieve multiprocessing.

Instruction Cycle

An instruction cycle, also known as a fetch-decode-execute cycle, is the basic operation performed
by a central processing unit (CPU) to execute an instruction. The instruction cycle consists of
several steps, each of which performs a specific function in the execution of the instruction. The
major steps in the instruction cycle are:

1. Fetch: In the fetch cycle, the CPU retrieves the instruction from memory. The instruction
is typically stored at the address specified by the program counter (PC). The PC is then
incremented to point to the next instruction in memory.

2. Decode: In the decode cycle, the CPU interprets the instruction and determines what
operation needs to be performed. This involves identifying the opcode and any operands
that are needed to execute the instruction.
 3. Execute: In the execute cycle, the CPU performs the operation specified by the instruction.
This may involve reading or writing data from or to memory, performing arithmetic or
logic operations on data, or manipulating the control flow of the program.

4. There are also some additional steps that may be performed during the instruction cycle,
depending on the CPU architecture and instruction set:

5. Fetch operands: In some CPUs, the operands needed for an instruction are fetched during
a separate cycle before the execute cycle. This is called the fetch operands cycle.

6. Store results: In some CPUs, the results of an instruction are stored during a separate cycle
after the execute cycle. This is called the store results cycle.

7. Interrupt handling: In some CPUs, interrupt handling may occur during any cycle of the
instruction cycle. An interrupt is a signal that the CPU receives from an external device or
software that requires immediate attention. When an interrupt occurs, the CPU suspends
the current instruction and executes an interrupt handler to service the interrupt.

These cycles are the basic building blocks of the CPU’s operation and are performed for every
instruction executed by the CPU. By optimizing these cycles, CPU designers can improve the
performance and efficiency of the CPU, allowing it to execute instructions faster and more
efficiently.

What Is Moore's Law?

Moore's Law states that the number of transistors on a microchip doubles every two years. The
law claims that we can expect the speed and capability of our computers to increase every two
years because of this, yet we will pay less for them. Another tenet of Moore's Law asserts that this
growth is exponential. The law is attributed to Gordon Moore, the co-founder and former CEO of
Intel.