Digital Circuit Design

Course Outline

• Required Textbook:
▪ Fundamentals of Logic Design, 7th Edition by Charles H.
Roth and Larry L. Kinney
▪ Software provided by CD in textbook:
o LogicAid: Manipulating logic functions
o SimUaid: Graphical simulation of digital circuits
o DirectVHDL: A VHDL editor and compiler
Course Outline

• Instructor:
▪ Dr. Chin-Feng Lai
▪ Office: 系館3F 41301A
▪ Email: cinfon@ieee.org
• Teaching Assistants (graders):
▪ Lab
o 廖聲享- N96114247@gs.ncku.edu.tw
o 劉彥甫- N96114255@gs.ncku.edu.tw
Course Outline

• Course Description
Introduction to logic design and interfacing digital circuits.
1. Boolean algebra
2. Combinatorial logic circuits
3. Digital multiplexers
4. Circuit minimization techniques
5. Flip-flop storage elements
6. Shift registers
7. Counting devices
8. Sequential logic circuits
Course Outline

• Course Description
▪ Combinational Digital Logic
o Number systems
o Binary arithmetic
o Logic gates
o Logic operations
o Arithmetic operations
o MSI components (Encoders, decoders, MUX, ...)
Course Outline

• Course Description
▪ Sequential Digital Logic
o Flip-Flops
o State machines
o State diagrams
o Timing
o Registers, shifters, and counters
o Basic control unit
▪ Introduction to VHDL
o A basic introduction to hardware definition languages
(specifically VHDL)
o VHDL design of Combinational & Sequential Circuits
Course Outline
1. Introduction number systems and
conversions.
2. Boolean algebra.
3. Boolean algebra (continued).
4. Applications of Boolean algebra
minterm and maxterm expansions.
5. Karnaugh maps.
6. Quine-McCluskey method.
7. Multi-level gate circuits.
8. Combinational circuit design and
simulation using gates.
9. Multiplexers, decoders, and
programmable logic devices.
10. Introduction to VHDL.
11. Latches and flip-flops.
12. Registers and counters.
13. Analysis of clocked sequential
circuits.
14. Derivation of state graphs and
tables.
15. Reduction of state tables state
assignment.
16. Sequentional circuit design.
17. VHDL for sequential logic.
18. Circuits for arithmetic operation.
19. State machine design with SM
charts.
20. VHDL for digital system design.
Course Outline

• Grading Scheme
▪ Homework Assignments: 30%
▪ Project Assignments: 20%
▪ Mid-Term Exams: 20%
▪ Final Exam: 30%

All Exams will be cumulative!!!

Introduction to Digital Logic:
What is Digital Logic?

• What is Digital Logic?

▪ The basis for all digital systems!!

For Example Computers ?

(Intel)
10
Introduction to Digital Logic:
Industries

• Product

Analog

Digital
Introduction to Digital Logic:
Motivation
• System on a Chip (SoC) Band gap

POR

GPIO
RAM

Dec.

PUMP

16k Flash
MAC

32K Osc PLL/Osc

Introduction to Digital Logic:
Motivation
• System → Modules (ALU, Memory, Register)
• Logic → Gates
• Circuit → Transistor, Resistance, Capacitance

(Intel)
 Introduction to Digital Logic
• VerilogHDL Design, Simulation, and Synthesis Flow
電路規格

always @(negedge reset or posedge

clk)
begin
if (!reset)
q_reg = #1 8'h00;
電路模擬 else
simulation if (en==1'b1)
q_reg = #1 data;
end
Verilog HDL
assign q = q_reg; 硬體描述語言 電路合成
synthesis

電路修改

D Q
D Q
D FF
D Q
DCloc
FF Q
D Q
FFk rsQ
DCloc
D Q rs
FFk Qt
DCloc
D Q
ModelSim 電路模擬器 FFk rsQt
DCloc
D Q
FFk rsQt
DCloc
data[7:0] D Q q[7:0]
e
FFk rsQt
DCloc
en
n
FFk rsQt
DCloc
Cloc k
rs t
電路模擬 clk k rs tQ
同步正緣時鐘脈衝 t
simulation ( clock )
reset

非同步負緣重置 ( reset )

CPLD / FPGA
晶片
可程式化元件
Introduction to Digital Logic:
FPGA Platform

• Hardware Design using Xilinx Chip (EDK-3SAISE)

FPGA
Chip
Introduction to Digital Logic:
Prototype

• VLSI Architecture Design

15
Introduction to Digital Logic:
• Moore’s Law
▪ Chip complexity ~doubles every two years
Xilinx FPGA: Virtex-Ultrascale XCVU440 has > 20 billion transistors

beloit.edu
Introduction to Digital Logic:
http://knowledge.wharton
• Top 30 Innovations over the last 30 years

18 of these are tied

to Digital Logic