Interview Questions on SVA for Formal Verification:

Here are some common interview questions on SystemVerilog Assertions (SVA) for
formal verification, along with answers:

1. What are the different types of assertions in SVA?

 Immediate Assertions: These check a condition at the current simulation time
and immediately raise a failure if violated. Not suitable for formal verification as
they don't capture temporal behavior.
 Concurrent Assertions: These verify the design's behavior over multiple clock
cycles using the assert property statement. Ideal for formal verification due to
their ability to express temporal properties.
2. Explain the syntax of a concurrent assertion in SVA.
Code snippet
assert property (<name>) {
@(<clock_signal>) <expression>
|-> ... // implication (leads to)
}

 <name>: A unique identifier for the assertion.

 <clock_signal>: The clock signal on whose edges the assertion is evaluated.

 <expression>: A temporal expression using SVA operators and keywords to

describe the desired property.

 |->: Implication operator, indicating what behavior should eventually follow the

initial condition.
3. How are temporal operators used in SVA for formal verification?

SVA offers various temporal operators to express temporal relationships between

signals:

 $next(signal): Value of signal in the next clock cycle.

 $past(signal, n): Value of signal n clock cycles ago.

 #n: Delay of n clock cycles.

 eventually (expr): expr will eventually become true in the future.

 always (expr): expr will always be true from this point onwards.
  until (expr1, expr2): expr1 will be true until expr2 becomes true.

Formal verification tools use these operators to analyze the design's behavior across
different execution paths.

4. Give an example of an SVA assertion for formal verification.

Code snippet
assert property (req_valid_hold) {
@(posedge clk) req_valid;
#1; // Wait for one clock cycle
|-> eventually (#1:2) ack_valid;
}
This assertion states that whenever req_valid is asserted for at least one clock cycle,
an acknowledgment (ack_valid) must be received within the next 1 or 2 clock cycles.
This helps formally verify the handshake protocol between a requester and responder.
5. What are some challenges of using SVA for formal verification?
 Complexity of assertions: Writing accurate and concise SVA assertions can be
challenging, especially for intricate design properties.
 Formal verification runtime: The verification process can be computationally
expensive for large designs, requiring careful assertion selection and
optimization techniques.
 Limited coverage: Formal verification with SVA may not cover all possible
design scenarios. It's crucial to combine it with other verification methods.