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SV Lectures Unit 1
SV Lectures Unit 1
by
Revathi Pogiri
Assistant Professor, Dept. of ECE
GMR Institute of Technology Rajam.
ASIC Flow
• Armed with this plan, you write stimulus vectors that exercise these features in the
DUT
• You then simulate the DUT with these vectors and manually review the resulting log
files and waveforms to make sure the design does what you expect.
• Once the test works correctly, you check it off in the verification plan and move to
the next one.
Figure shows how directed tests incrementally cover the features in the verification plan.
Each test is targeted at a very specific set of design elements. If you had enough time, you
could write all the tests needed for 100% coverage of the entire verification plan.
The figure shows the total design space and features that are covered by directed test
cases. In this space are many features, some of which have bugs. You need to write tests
that cover all the features and find the bugs.
• Layered testbench using transactors: A layered testbench helps you control the
complexity by breaking the problem into manageable pieces. Transactors provide
a useful pattern for building these pieces.
• Test-specific code kept separate from the testbench: code specific to a single
test must be kept separate from the testbench to prevent it from complicating the
infrastructure
• In Figure, you can see the initial delay before the first random test runs.
• Every random test you create shares this common testbench, as opposed to directed
tests where each is written from scratch.
• single constrained-random testbench is now finding bugs faster than the many directed
ones
• If the new area is not legal, you need to write more constraints to keep random
generation from creating illegal design functionality
• When you look at the functional coverage reports, find the holes where there are gaps
in the coverage.
• Now you make minimal code changes, perhaps by using new constraints, or by
injecting errors or delays into the DUT.
• Spend most of your time in this outer loop. Writing directed tests for only a few
features that are very unlikely to be reached by random tests.
• Although this process may seem to make the test bench more complex, it actually
helps to make your task easier by dividing the code into smaller pieces that can be
developed separately.
• At the bottom is the signal layer that contains the DUT and the signals that connect
it to the testbench
• The DUT's inputs are driven by the driver that runs single commands, such as bus
read or write.
• The DUT's output drives the monitor that takes signal transitions.
• For example, a device is an MP3 player that can concurrently play music from its
storage, download new music from a host, and respond to input from the user, such
as adjusting the volume and track controls. Each of these operations is a scenario.
• The scenario layer of your testbench arranges all these steps with constrained-
random stimulus.
• Functional coverage measures the progress of all tests in fulfilling the verification
plan requirements.
• Do you need all these layers in your testbench? The answer depends on what your
DUT looks like. A complicated design requires a sophisticated testbench.
• System Verilog introduces new data types with the following benefits:
• Two-state: better performance, reduced memory usage
• Queues, dynamic and associative arrays: reduced memory usage, built-in
support for searching and sorting
• Classes and structures: support for abstract data structures
• Unions and packed structures: allow multiple views of the same
• data Strings: built-in string support
• Enumerated types: code is easier to write and understand
• Verilog-1995 has two basic data types: variables and nets, both of which
hold 4-state values: 0, I, Z, and X.
• RTL code uses variables to store combinational and sequential values.
• Variables can be unsigned single or multi-bit (reg [7: 0] m), signed 32-bit
variables (integer), unsigned 64-bit variables (time), and floating-point
numbers (real).
• Variables can be grouped together into arrays that have a fixed size.
• All storage is static, meaning that all variables are alive for the entire
simulation and routines cannot use a stack to hold arguments and local
values.
➢ Hence System Verilog has extended Verilog by adding more C like data-
• System Verilog adds many new data types to help both hardware
designers and verification engineers:
➢ Types that can have unknown (X) and high-impedance (Z) value in
addition to zero (0) and one (1) are called 4-state types.
➢ reg can only be driven in procedural blocks like always and initial while
➢ System Verilog introduces a new 4-state data type called logic that can be
➢ But, a signal with more than one driver needs to be declared a net- type
such as wire so that System Verilog can resolve the final value.
• Rather than trying to choose between reg and wire, declare all your signals
as logic, and you'll get a compilation error if it has multiple drivers.
• A logic signal can be used anywhere a net is used, except that a logic
variable cannot be driven by multiple structural drivers, such as when you
are modelling a bidirectional bus.
really need all the four values (0, 1, x, z) like for example when modeling a
network packet with a header that specifies the length of the packet.
➢ System Verilog adds many new 2-state data types that can only store and
➢ his will aid in faster simulation, take less memory and are preferred in
➢ The most important 2-state data type is bit which is used most often in
testbenches.
• You might be tempted to use types such as byte to replace more verbose
declarations such as logic [7: 0 ]
• You could use byte unsigned. but that is more verbose than just bit [7: 0 ].
• Use the $isunknown() operator that returns 1 if any bit of the expression
is X or Z.
Multidimensional array
Multidimensional arrays are also known as an array of arrays.
int arr[2][3];
•The term packed array is used to refer to the dimensions declared before the data
identifier name
•The term unpacked array is used to refer to the dimensions declared after the data
identifier name
➢ Packed arrays can be of single bit data types (reg, logic, bit), enumerated types, and
range
➢ Scalar: Scalar is 1-bit data object of reg/logic/bit declared without specifying a range
➢ A packed array is a mechanism for subdividing a vector into sub-fields, which can be
Packed Arrays:
•In packed arrays, the bits are stored consecutively in memory without any gaps or
padding.
•The bit order is determined by the range specified in the declaration.
Example:
bit [7:0] packed_array;
stored as follows:
7 6 5 4 3 2 1 0
1 0 1 0 1 0 1 0
Packed Arrays:
•In packed arrays, the bits are stored
consecutively in memory without any gaps or
padding.
•The bit order is determined by the range
specified in the declaration.
Example:
bit unpacked_array[7:0];
0 1 2 3 4 5 6 7
1 0 1 0 1 0 1 0
➢ Packed arrays store bits consecutively in memory based on the specified range, while
unpacked arrays store bits based on the order of the array elements.
➢ The choice between packed and unpacked arrays depends on the design requirements
➢ In fixed size array, array size will be constant throughout the simulation, Once
the array is declared no need to create it.
➢ By default, the array will be initialized with value ‘0’.
Note:
➢ A dynamic array is an unpacked array whose size can be set or changed at run time,
and hence is quite different from a static array where the size is pre-determined
➢ The default size of a dynamic array is zero until it is set by the new () constructor.
➢ Queues are declared using the same syntax as unpacked arrays, but specifying $ as
the array size. In queue 0 represents the first, and $ representing the last entries.
➢ bounded queue – queue with the number of entries limited or queue size specified
➢ unbounded queue – queue with unlimited entries or queue size not specified
Queue Initialization
Array Declaration
data_type array_name [ index_type ];
where:
data_type – data type of the array elements.
array_name – name of the associative array.
index_type – data-type to be used as an index, or *.
* indicates the array is indexed by any integral expression of arbitrary size.
➢ There are many built-in methods in System Verilog to help in array searching and
ordering.
➢ Array manipulation methods simply iterate through the array elements and each
➢ The iterator argument specifies a local variable that can be used within the with
➢ In such cases we can use a typedef to give a user-defined name to an existing data type.
➢ The new data-type can then be used throughout the code and hence avoids the need to
Syntax:
➢ In this example, the signal data is assigned the value 8'hFF using the alias mydata.
➢ The advantage of using an alias is that it allows you to refer to the same signal using
different names, which can make the code more readable and easier to understand.
➢ The user can assign any integer value for any of the enumerated names.
➢ If any name does not have an assigned value, then it automatically takes the
incremented value of the previous name.