Analog VLSI Circuits

E3 238
Switched Capacitor Circuits
❑ References:
• A-H: CMOS analog circuit design by Allen and Holdberg
• Behzad Razavi - Design of Analog CMOS Integrated Circuits
• Vazgen, Melikyan et al. “Adjustable Low-Power Non-overlap Clock Generator
for Switched-Capacitor Circuits.” .
Overview
1. Motivation
2. Switched cap resistor + Integrator
3. SC Amplifier
4. Capacitors/Parasitic Insensitive SC circuits
5. Switches
6. Non-Idealities in SC circuits
7. Other application of SC circuits

IISc, Analog VLSI Circuits E3 238 2

 Typical Analog Signal Chain
Motivation
• Filters are a vital component in Analog Signal Chain
• Filters with low Bandwidth Signals require large time
constants.
 = 
• Large Time constants => Large Resistors and Capacitors
• Area Intensive  Cost Intensive

• Amplifiers gain control usually done through Resistors – Audio signals Bandwidth – 20Hz to 20KHz
Can load the Amplifier output, Introduces noise
Bio medical
• Sampled systems can allow us to use some techniques Signals BW
which can improve performance of the system
e.g Auto Zeroing(offset reduction), SC cmfb etc

IISc, Analog VLSI Circuits E3 238 Ref: A-H 3

 Motivation
Continuous Time Integrator -

 
=
 ω

Time Constant depends on absolute value of Resistor and

Capacitor. Accuracy ~ 20% due to Process Variations.
Integrators are the basic building blocks
in realising Filters. MOS transistors form very good switches and IC processes
have good matching of capacitor ratios.

➢ Since ADC is a Sample and Quantize system. Can we use

discrete time system to realise integrator/filters?

➢ Can we use switches and capacitors to replace the resistor?

IISc, Analog VLSI Circuits E3 238 Ref: A-H 4

Overview
1. Motivation
2. Switched cap resistor + Integrator
3. SC Amplifier
4. Capacitors/Parasitic Insensitive SC circuits
5. Switches
6. Non-Idealities in SC circuits
7. Other application of SC circuits

IISc, Analog VLSI Circuits E3 238 5

 Switched Cap Resistor
Non Overlap
Clocks!!

In  phase of the clock In  phase of the clock

,1 =   ,2 =  
Emulating a resistor using two
switches and a capacitor.  Total charge transfer from  to  =   − 
 Q =  V − V
• Resistor value is determined by Sampling
frequency and Capacitance Δ Δ
= and  =
•  accurate to few ppm, Cap ratio accurate to  Δ
~.5%
 
• Has also given us tunability by varying ==f
sC
frequency
IISc, Analog VLSI Circuits E3 238 Ref: A-H 6
Z transforms review
• Converts discrete time signal to frequency domain representation

  →   → [] sampling at frequency  =
∞ 

  = ෍    
0
• Time delay –
  ↔ ()
  −   ↔    
(  −  ) ↔   ()
  −  ↔    

IISc, Analog VLSI Circuits E3 238 Ref: A-H 7

Z transforms review
• Continuous time systems • Discrete time systems
̶ Difference equations
̶ Differential equations
• V(n-1), V(n), …
̶ Laplace transform () ̶ z transform ()
̶ Substitute  =  to get •     , …
frequency response ̶ Substitute z =   to get frequency
response
Im Im
s plane z plane
 = ω  =  

Re
Re

IISc, Analog VLSI Circuits E3 238 Ref: A-H 8

Switched Cap Integrator

Phase 1 Phase 2


 ( − )
 ( − ) 

 [( − )]


 [( − )]


IISc, Analog VLSI Circuits E3 238 Ref: A-H 9

 Switched Cap Integrator
Phase 1 Phase 2


 ( − )
 ( − ) 
 [( − )]

 [( − )]


,2 = 
,1 =   [ − )]

,1 = −  [( − )] ,2 = −  [( − )]

Charge Conservation –
,1 = ,2 − ,1
 
   [( − )] = − 

 () 
−

 +   [( − )] 
=−
 Since  is isolated from input in phase  ,  −

 =  []
 ()  −  


   [( − )] = −   +   [( − )]

     = −   +     () IISc, Analog VLSI Circuits E3 238 Ref: A-H 10
 Switched Cap Integrator

• To look at the frequency response we set  =   , ℎ  =
1 
 () 2
 1 • If we assume that sampling frequency is much higher than signal
=− frequency, then,   ≈  +  ,   ≪ 
 ()  1

  1 1
=−
  2 1
• Time constant is decided by frequency
Converting to frequency    and Ratio of capacitors
= • Large time constants possible without
response  
excessively large components
• Very good matching for ratio of
  1  capacitors ~ 0.5%
=− • Precise Setting of time constant
  2 

IISc, Analog VLSI Circuits E3 238 Ref: A-H 11

Switched Cap Integrator
Steps Used to Analyse Switched capacitor circuits –
1. Draw out the circuits in the two phases
2. Write charge equations in the two phases and observe the flow of charge
3. Use z-Transform to convert from time domain to frequency domain
4. Use  =   to convert to continuous time frequency response

Things to keep in mind –

1. We need Non overlapping clocks, as any overlap
will create error.
2. Signal frequency is usually much lower than the
sampling frequency

IISc, Analog VLSI Circuits E3 238 Ref: A-H 12

Overview
1. Motivation
2. Switched cap resistor + Integrator
3. SC Amplifier
4. Capacitors/Parasitic Insensitive SC circuits
5. Switches
6. Non-Idealities in SC circuits
7. Other application of SC circuits

IISc, Analog VLSI Circuits E3 238 13

 Switched Cap Amplifier
Continuous time
Inverting Amp

This Switch used

to periodically set DCop

Resistor loads the output of the OpAmp

thus, reducing Open loop Gain.

Let’s try and use capacitors to set gain ratio.

Discrete time Amplifier

IISc, Analog VLSI Circuits E3 238 Ref: A-H 14
 Switched Cap Amplifier (Analysis)
Step 1

1 =   − 
Step 2
2 = 
−   −   Charge eq


  
 −   = −  [  −  ]

   
   = −  
  
   = −  Step 3
Charge
    conservation
=− 
  

 
  =− 

  =  / Step 4
∠  = −8 −  Frequency
response

IISc, Analog VLSI Circuits E3 238 Ref: A-H 15

Non-Overlap Clock generator

IISc, Analog VLSI Circuits E3 238 Ref: A-H 16

Overview
1. Motivation
2. Switched cap resistor + Integrator
3. SC Amplifier
4. Capacitors/Parasitic Insensitive SC circuits
5. Switches
6. Non-Idealities in SC circuits
7. Other application of SC circuits

IISc, Analog VLSI Circuits E3 238 17

 Switched Capacitor circuits

• Capacitor
• Switch
• OpAmp
IISc, Analog VLSI Circuits E3 238 Ref: A-H 18
On Chip capacitors
MIM Cap MOM cap MOS cap
Composed of the top two Interdigitated capacitors Gate capacitor of
layers of metal and a special formed by metal MOSFET
MIM Cap metal layer in the middle connections
Excellent Matching Good Matching Good Matching
Low Density Moderate Density High Density
Large Parasitics ( 10% ) Large Parasitics Low Parasitics
Accurate Stability and Varies with Voltage
Determinism not as good
MOM cap as MIM
Only available in
Advanced Nodes

For Switched Capacitor Applications, MIM cap is preferred

IISc, Analog VLSI Circuits E3 238 Ref: A-H 19

MOS cap
On Chip capacitors
 connected to GND
Practical Capacitor Integrator with parasitics 3 connected to virtual GND
4 connected to OpAmp output

 is the only cap which affects

signal

 ()  +   

=−
 ()   −  

•  is nonlinear and not controllable

•  accuracy is again not good
• Bad for precision applications
IISc, Analog VLSI Circuits E3 238 Ref: A-H 20
Parasitic Insensitive Integrators

IISc, Analog VLSI Circuits E3 238 Ref: A-H 21

Parasitic Insensitive Integrators

1,1 =   −

2,1 = −  − Step 2

 Charge eq
2,2 = −  ( − )


2,2 = 2,1 − 1,1


  
−   − = −   −  −   −

   Step 3
   =      +      Charge
conservation
    
= .
    −  

   
= . Step 4
    Frequency
response

IISc, Analog VLSI Circuits E3 238 Ref: A-H 22

Parasitic Insensitive Integrators

IISc, Analog VLSI Circuits E3 238 Ref: A-H 23

Parasitic Insensitive Integrators

IISc, Analog VLSI Circuits E3 238 Ref: A-H 24

Overview
1. Motivation
2. Switched cap resistor + Integrator
3. SC Amplifier
4. Capacitors/Parasitic Insensitive SC circuits
5. Switches
6. Non-Idealities in SC circuits
7. Other application of SC circuits

IISc, Analog VLSI Circuits E3 238 25