Revised Regulation- 2008

Reg. No:
(A)

SRI RAMAKRISHNA ENGINEERING COLLEGE, COIMBATORE

(Autonomous Institution, Approved by AICTE and permanently affiliated to Anna University, Chennai)

AUTONOMOUS EXAMINATIONS – NOV 2014

THIRD SEMESTER
DIGITAL LOGIC CIRCUITS
08AB303, 08AD303 & 08AG303
COMMON TO B.E – EEE, EIE & BME
Answer ALL questions
Duration: 3 Hours Maximum: 100 Marks
PART - A (10 x 1 = 10 Marks)

1. What is the octal equivalent of the binary number 10111101

a)675 b)275 c)572 d)573

2. Which of the following gate is a two-level logic gate

a) NAND b) NOR c) XOR d) AND

3. A circuit that can convert one of ten numerical keys pressed on a keyboard to BCD is
a ________
a) MUX b)DEMUX c)Comparator d) Priority Encoder

4. How many outputs would two 8-line-to-3-line encoders, expanded to a 16-line-to-4-

line encoder, have?
a) 16 b) 8 c) 3 d) 4

5. The terminal count of a modulus-11 binary counter is

a)1010 b)1000 c)1001 d)1100

6. A 4-bit binary up counter has an input clock frequency of 20 kHz. The frequency of
the most significant bit is

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 a)1.25KHz b)2.50 KHz c)160 KHz d)320 KHz
7. How many different states does a 3-bit asynchronous counter have?
a)3 b) 4 c)7 d)8

8. A cycle occurs when a circuit goes through a unique sequence of __________ states
a) meta stable b) stable c) unstable d) mono stable

9. PALs tend to execute ________ logic

a) PLA b) POS c) SOP d) XOR

10. Which of the following logic families has the shortest propagation delay?
a) TTL b) ECL c)CMOS d)74SXX

PART - B (5 x 2 = 10 Marks)
11. State and prove Consensus law.
12.
Implement the logic function f = ∑ m(0,2,3 ,6) using a decoder.
13. Derive the characteristic table of JK flip flop.
14. What is race condition?
15. Compare PAL and PLA.

PART - C (5 x 16 = 80 Marks)
16. a) i) Reduce the following switching function using K-map Π M (12)
(2,3,5,7,9,11,12)+ Π D(1,4,8,14)
ii) Find the complement of the expression Y=ABC+ABC′+A′B′C+A′BC (4)
(OR)
b) Using Quine McClusky method to obtain the minimal sum for the (16)
following function

F (V,W,X,Y,Z) = ∑ m( 4,5,6,7 ,9,10,14,19,26 ,30,31)

17. a) i) The output of a NAND gate network is F(A,B,C)=m(3,6,7,x).The (10)

output of the gate network does not change if all the gates are
replaced by NOR gates. Determine the value of x.
ii) Design 3 bit comparator. (6)

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 (OR)
b) i) Design BCD to Gray Code converter. (10)
ii)
Implement the function using 8:1 MUX only ∑ m(0 ,1,2,6,7,9,12,14) (6)

18. a) i) Convert SR Flip Flop to JK Flip Flop. (10)

ii) Discuss about Johnson counter and its working principle. (6)
(OR)
b) Design a modulo 5 synchronous counter using JK FF and implement (16)
it. Construct its timing diagram.

19. a) Explain the procedure for analysis of asynchronous sequential (16)

circuits with known example in detail
(OR)
b) What are Hazards and illustrate the types of hazards with examples (16)

Compulsory Question:
20. i) Implement the switching function Z=bc +de+c′d′e′+bd using PLA (6)
ii) Explain the general architecture of FPGA with neat diagram. (10)
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