Faculty of Engineering and Technology

Electrical Engineering Department

ELE 215 – Logic Design and

Digital Circuits
Lecture 5 - Combinational Logic
(Part A)
Dr. Nermin Salem
nfawzy@fue.edu.eg
 Course Outline
• Introduction
• Numbering System
• Logic Gates and Gate-Level Minimization
• Boolean Algebra
• K-maps
• Combinational Logic Introduction
Combination Circuits
• Synchronous Sequential Logic Procedure Analysis
Binary Adder-Subtractor
• Registers and Counters Decimal Adder
Binary Multiplier
• Memories and Programmable Logic Magnitude Comparator

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 Introduction
• There are types of logic circuits of digital systems:
➢Combinational Circuits
➢Sequential Circuits
• A combinational circuit performs an operation that can be specified
logically by a set of Boolean functions.
• Combinational logic gates react to the values of the signals at their inputs
and produce the value of the output signal, transforming binary
information from the given input data to a required output data.

For n input variables, there are For each possible input combination,
2𝑛 possible binary combinations. there is one possible output value.

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 Analysis Procedure
• The first step in the analysis is to make sure that the given circuit is
combinational and not sequential.
• The diagram of a combinational circuit has logic gates with no feedback
paths or memory elements
• Obtain the output Boolean functions or the truth table.
1. Label all gate outputs that are a function of input variables with arbitrary symbols but with
meaningful names. Determine the Boolean functions for each gate output
2. Label the gates that are a function of input variables and previously labeled gates with other
arbitrary symbols. Find the Boolean functions for these gates
3. Repeat the process outlined in step 2 until the outputs of the circuit are obtained
4. By repeated substitution of previously defined functions, obtain the output Boolean
functions in terms of input variables

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 Example 1

Inputs are: A,B and C

Outputs: 𝐹1 and 𝐹2

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 Solution of Example 1
𝐹2 = 𝑨𝑩 + 𝑨𝑪 + 𝑩𝑪
∴ 𝐹1 = 𝐹2′ 𝑇1 + 𝐴𝐵𝐶
𝑇1 = 𝐴 + 𝐵 + 𝐶
′
= 𝐴𝐵 + 𝐴𝐶 + 𝐵𝐶 𝐴 + 𝐵 + 𝐶 + 𝐴𝐵𝐶
𝑇2 = 𝐴𝐵𝐶
= 𝐴′ + 𝐵′ 𝐴′ + 𝐶 ′ 𝐵′ + 𝐶 ′ 𝐴 + 𝐵 + 𝐶 + 𝐴𝐵𝐶
𝑇3 = 𝐹2 ′ 𝑇1 = 𝐴′ + 𝐴′ 𝐶 ′ + 𝐴′ 𝐵′ + 𝐵′ 𝐶 ′ 𝐴𝐵′ + 𝐵𝐵′ + 𝐵′ 𝐶 + 𝐴𝐶 ′ + 𝐵𝐶 ′ + 𝐶𝐶 ′ + 𝐴𝐵𝐶
𝐹1 = 𝑇3 + 𝑇2 = 𝐴′ + 𝐵′ 𝐶 ′ 𝐴𝐵′ + 𝐵′ 𝐶 + 𝐴𝐶 ′ + 𝐵𝐶 ′ + 𝐴𝐵𝐶
= 𝐴′ 𝐴𝐵′ + 𝐴′ 𝐵′ 𝐶 + 𝐴′ 𝐴𝐶 ′ + 𝐴′ 𝐵𝐶 ′ + 𝐴𝐵′ 𝐶𝐶 ′ + 𝐴𝐵′ 𝐶 ′ + 𝐵′ 𝐵𝐶𝐶 ′ + 𝐴𝐵𝐶
= 𝑨′ 𝑩′ 𝑪 + 𝑨′ 𝑩𝑪′ + 𝑨𝑩′ 𝑪′ + 𝑨𝑩𝑪

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Solution of
Example 1
(Cont.)
 Example
Design a circuit that converts Binary Code Decimal (BCD) into the
Excess – 3 code.
Solution: 1. Define the number of inputs and outputs.

2 3

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 Example
4

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 Binary Adder/Subtractor
• Half Adder: A combinational circuit that performs the addition of two bits.
• Full Adder: A combinational circuit that performs the addition of three bits
(two significant bits and a previous carry).
• The names of the circuits stem from the fact that two half adders can be
employed to implement a full adder.
• Adder–Subtractor: is a combinational circuit that performs the arithmetic
operations of addition and subtraction with binary numbers.
• The design is a hierarchical design. The half adder design is carried out first,
from which we develop the full adder. Connecting n full adders in cascade
produces a binary adder for two n-bit numbers. The subtraction circuit is
included in a complementing circuit.

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Half Adder

Logic Diagram
𝐴0 𝐵0

𝐴0 is Augend
𝐶1 HA
𝐵0 is Addend
𝑆0 is Sum
𝐶1 is Output carry

𝑆0
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 Addend Carry from previous
Augend
operation

Full Adder 𝑥 𝑦

𝐶1 FA 𝑧

𝑆0
Logic Diagram Block Diagram
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 Binary Adder
A binary adder is a digital circuit that produces the arithmetic sum of
two binary numbers. It can be constructed with full adders connected in
cascade, with the output carry from each full adder connected to the
input carry of the next full adder in the chain.

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 Binary Adder
To demonstrate with a specific example, consider the two binary numbers A = 1011
and B = 0011. Their sum S = 1110 is formed with the four-bit adder as follows:

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 Binary Adder

Block Diagram of 4-bit Binary Adder

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 Binary Subtractor
The subtraction of unsigned binary numbers can be done most
conveniently by means of complements.
Remember that: The subtraction A - B can be done by taking the 2’s
complement of B and adding it to A .
The 2’s complement can be obtained by taking the 1’s complement and
adding 1 to the least significant pair of bits.
The 1’s complement can be implemented with inverters, and a 1 can be
added to the sum through the input carry.

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 Binary Adder-Subtractor

When M = 0,
the circuit is an
adder.
when M = 1, the
circuit becomes a
subtractor.

• An overflow V cannot occur after an addition if one number is positive and the other is negative.
• An overflow may occur if the two numbers added are both positive or both negative.
• An overflow condition can be detected by observing the carry into the sign bit position and the carry out of the sign bit position.
• These two carries are not equal, an overflow has occurred. This is indicated in the examples in which the two carries are explicitly shown.
• If the two carries are applied to an exclusive-OR gate, an overflow is detected when the output of the gate is equal to 1.
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 Decimal Adder – BCD Adder
• When the binary sum is equal to or less
than 1001, the corresponding BCD
number is identical, and therefore no
conversion is needed.
• When the binary sum is greater than 1001,
we obtain an invalid BCD representation.
The addition of binary 6 (0110) to the
binary sum converts it to the correct BCD
representation and produces an output
carry as required.
• K is an output carry
• The condition for a correction and an
output carry can be expressed by the
Boolean function:
𝐶 = 𝐾 + 𝑍8 𝑍4 + 𝑍8 𝑍2

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 BCD Adder
Block
Diagram

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- L4 19
Binary
Multiplier
• Multiplication of binary
numbers is performed in the
same way as multiplication of
decimal numbers.
• The multiplicand is multiplied
by each bit of the multiplier,
starting from the least
significant bit. Each such
multiplication forms a partial
product. Successive partial
products are shifted one
position to the left.
• The final product is obtained
from the sum of the partial
products. Nermin Salem ELE 215
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 Binary Multiplier
For J multiplier bits and K multiplicand bits, we
need (J×𝐾) AND gates and (J−1) K -bit adders
to produce a product of (J + K) bits
Consider a multiplier circuit that multiplies a
binary number represented by four bits by a
number represented by three bits.
➢ Let the multiplicand be represented by
𝐵3 𝐵2 𝐵1 𝐵0 and the multiplier by
𝐴2 𝐴1 𝐴0
Here, we have K = 4 and J = 3
∴ we need 12 AND gates and two 4-bit
adders to produce a product of seven bits.

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 Magnitude Comparator
A magnitude comparator is a combinational circuit that compares two numbers A and
B and determines their relative magnitudes. The outcome of the comparison is
specified by three binary variables that indicate:
A>B,A=B,A<B
Consider two numbers, A and B , with four digits each. Write the coefficients of the
numbers in descending order of significance:
𝐴 = 𝐴3 𝐴2 𝐴1 𝐴0 𝐵 = 𝐵3 𝐵2 𝐵1 𝐵0
• For equality to exist, all 𝑥𝑖 variables must be equal to 1, a condition that dictates an
AND operation of all variables: (𝐴 = 𝐵) = 𝑥3 𝑥2 𝑥1 𝑥0
• To determine whether A is greater or less than B , we inspect the relative magnitudes of
pairs of significant digits, starting from the most significant position. If the two digits of a
pair are equal, we compare the next lower significant pair of digits. The comparison
continues until a pair of unequal digits is reached. If the corresponding digit of A is 1 and
that of B is 0, we conclude that A > B. If the corresponding digit of A is 0 and that of B is 1,
we have A < B:

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Magnitude
Comparator

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 References
▪ M. Mano and M. Ciletti, Digital Design, with an introduction to the
Verilog HDL. 5th Ed. Pearson, 2013.
▪ John F. Wakerly, Digital Design: Principles and Practices. 4th Ed.
Pearson, 2005.
▪ R. Katz and G. Boriello, Contemporary Logic Design. 2nd Ed. Pearson,
2005.
▪ S. Brown and Z. Vranesic , Fundamentals of Digital Logic with
Verilog Design. 3rd Ed. SEM, 2013.

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 Thank You

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