The Universal Asynchronous Receiver/Transmitter (UART

The Universal Asynchronous Receiver/Transmitter (UART) controller is the key

component of the serial communications subsystem of a computer. The UART takes
bytes of data and transmits the individual bits in a sequential fashion. At the destination, a
second UART re-assembles the bits into complete bytes.

Serial transmission is commonly used with modems and for non-networked

communication between computers, terminals and other devices.

There are two primary forms of serial transmission: Synchronous and Asynchronous.
Depending on the modes that are supported by the hardware, the name of the
communication sub-system will usually include a A if it supports Asynchronous
communications, and a S if it supports Synchronous communications. Both forms are
described below.

Some common acronyms are:

UART Universal Asynchronous Receiver/Transmitter

USART Universal Synchronous-Asynchronous Receiver/Transmitter

Synchronous Serial Transmission

Synchronous serial transmission requires that the sender and receiver share a clock with
one another, or that the sender provide a strobe or other timing signal so that the receiver
knows when to ``read'' the next bit of the data. In most forms of serial Synchronous
communication, if there is no data available at a given instant to transmit, a fill character
must be sent instead so that data is always being transmitted. Synchronous
communication is usually more efficient because only data bits are transmitted between
sender and receiver, and synchronous communication can be more costly if extra wiring
and circuits are required to share a clock signal between the sender and receiver.

A form of Synchronous transmission is used with printers and fixed disk devices in that
the data is sent on one set of wires while a clock or strobe is sent on a different wire.
Printers and fixed disk devices are not normally serial devices because most fixed disk
interface standards send an entire word of data for each clock or strobe signal by using a
separate wire for each bit of the word. In the PC industry, these are known as Parallel
devices.

The standard serial communications hardware in the PC does not support Synchronous
operations. This mode is described here for comparison purposes only.

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Asynchronous Serial Transmission

Asynchronous transmission allows data to be transmitted without the sender having to

send a clock signal to the receiver. Instead, the sender and receiver must agree on timing
parameters in advance and special bits are added to each word which are used to
synchronise the sending and receiving units.

Baud Rate, Data Bits and Parity

Serial communication using RS-232 requires that you specify four parameters: the baud
rate of the transmission, the number of data bits encoding a character, the sense of the
optional parity bit, and the number of stop bits. Each transmitted character is packaged
in a character frame that consists of a single start bit followed by the data bits, the
optional parity bit, and the stop bit or bits. A typical character frame encoding the letter
"m" is shown here.

Figure1

Baud rate

Definition of baud and bits per second (BPS)

The two most corrupted terms in telecommunications. Baud is the number of
signal level changes per second in a line, regardless of the information content of
those signals. Bits per second is the rate of transfer of information bits. The ratio
of BPS to baud depends on the information coding scheme that you are using. For
example, each character in asynchronous RS-232 coding includes a start and stop
bit that are not counted as information bits, so the BPS rate is actually less than
the baud rate. Present-day modems, on the other hand, use a set of discrete
amplitude and phase values to encode multiple bits with each signal change. This
technique, along with compression schemes and other tricks, allows BPS rates of
14,400 and higher on lines that support relatively low signal change rates (about
2400 baud for phone lines).

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Baud rate, is a measure of how fast data is moving between instruments that use serial
communication. RS-232 uses only two voltage states, called MARK and SPACE. In such
a two-state coding scheme, the baud rate is identical to the maximum number of bits of
information, including "control" bits, that are transmitted per second.

MARK is a negative voltage and SPACE is positive; Figure 1 above shows how the
idealised signal looks on an oscilloscope.

(Start bit)

A start bit signals the beginning of each character frame. It is a transition from negative
(MARK) to positive (SPACE) voltage; its duration in seconds is the reciprocal of the
baud rate. The Start Bit is used to alert the receiver that a word of data is about to be sent,
and to force the clock in the receiver into synchronisation with the clock in the
transmitter. These two clocks must be accurate enough to not have the frequency drift by
more than 10% during the transmission of the remaining bits in the word. If we're
transmitting at 9600 baud, then the duration of the start bit and each subsequent bit will
be about 0.104 ms. The entire character frame of eleven bits would be transmitted in
about 1.146 ms.

Data bits

Data bits are transmitted "upside down and backwards." That is, inverted logic is used
and the order of transmission is from least significant bit (LSB) to most significant bit
(MSB). To interpret the data bits in a character frame, you must read from right to left,
and read 1 for negative voltage and 0 for positive voltage. For the figure above, this
yields 1101101 (binary) or 6D (hex). An ASCII conversion table on page 9 of this
handout shows that this is the letter "m".
Parity bit
An optional parity bit follows the data bits in the character frame. The parity bit, if
present, also follows inverted logic: read 1 for negative voltage and 0 for positive voltage.

This bit is included as a simple means of error checking. The idea is this: you specify
ahead of time whether the parity of the transmission is to be even or odd. Suppose the
parity is chosen to be odd. The transmitter will then set the parity bit in such a way as to
make an odd number of 1's among the data bits and the parity bit. The transmission in the
figure above uses odd parity. There are five 1's among the data bits, already an odd
number, so the parity bit is set to 0.

Stop bits
The last part of a character frame consists of 1, 1.5, or 2 stop bits. These bits are always
represented by a negative voltage. If no further characters are transmitted, the line stays
in the negative (MARK) condition. If the Stop Bit does not appear when it is supposed to,
the UART considers the entire word to be garbled and will report a Framing Error to the
host processor when the data word is read. The usual cause of a Framing Error is that the

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 sender and receiver clocks were not running at the same speed, or that the signal was
interrupted.

Assume we want to send the letter 'A' over the serial port. The binary representation of
the letter 'A' is 01000001. Remembering that bits are transmitted from least significant bit
(LSB) to most significant bit (MSB), the bit stream transmitted would be as follows for
the line characteristics 8 bits, no parity, 1 stop bit, 9600 baud.

LSB (0 1 0 0 0 0 0 1 0 1) MSB

The above represents (Start Bit) (Data Bits) (Stop Bit)

Because asynchronous data is ``self synchronising'', if there is no data to transmit, the

transmission line can be idle.
Transmission rates
Knowing the structure of a character frame and the meaning of baud rate as it applies to
RS-232, you can calculate the maximum transmission rate, in characters per second, for a
given communication setting. This rate is just the baud rate divided by the bits per frame.
In the case above, we have a total of eleven bits per character frame. If the transmission
rate is set at 9600 baud, then we get 9600/11 = 872 characters per second.

If you want to squeeze more characters per second into your transmission, then get rid of
the parity bit and reduce the stop bits to one. The character frame then has (assuming
seven data bits) a total of only nine bits. If you are still transmitting at 9600 baud, then
you will be able to send 9600/9 = 1066 characters per second.

The next step is to drop the start and stop bits entirely and send only the data bits. This
can be done with synchronous transmission. The start of each new character is signaled
on a separate line running between the transmitter and receiver. Assuming once again that
each character has seven data bits and that the transmission takes place at 9600 baud, the
synchronous arrangement is able to send 9600/7 = 1371 characters per second.

Note that these are maximum character transmission rates. It may happen that the
hardware on one end or the other of the serial link may not be able to reach these rates,
for whatever reason. The actual transmission rate is usually throttled by signals on the
link's handshaking lines.

Other UART Functions

In addition to the basic job of converting data from parallel to serial for transmission and
from serial to parallel on reception, a UART will usually provide additional circuits for
signals that can be used to indicate the state of the transmission media, and to regulate the
flow of data in the event that the remote device is not prepared to accept more data. For
example, when the device connected to the UART is a modem, the modem may report
the presence of a carrier on the phone line while the computer may be able to instruct the
modem to reset itself or to not take calls by raising or lowering one more of these extra

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signals. The function of each of these additional signals is defined in the EIA RS232-C
standard.
The RS232-C and V.24 Standards
In most computer systems, the UART is connected to circuitry that generates signals that
comply with the EIA RS232-C specification. There is also a CCITT standard named V.24
that mirrors the specifications included in RS232-C.

RS232-C Bit Assignments (Marks and Spaces)

In RS232-C, a value of 1 is called a Mark and a value of 0 is called a Space. When a
communication line is idle, the line is said to be ``Marking'', or transmitting continuous 1
values.
The Start bit always has a value of 0 (a Space). The Stop Bit always has a value of 1 (a
Mark). This means that there will always be a Mark (1) to Space (0) transition on the line
at the start of every word, even when multiple word are transmitted back to back. This
guarantees that sender and receiver can resynchronise their clocks regardless of the
content of the data bits that are being transmitted.
The idle time between Stop and Start bits does not have to be an exact multiple (including
zero) of the bit rate of the communication link, but most UARTs are designed this way
for simplicity.
In RS232-C, the "Marking" signal (a 1) is represented by a voltage between -3 VDC and
-12 VDC, and a "Spacing" signal (a 0) is represented by a voltage between 0 and +12
VDC. The transmitter is supposed to send +12 VDC or -12 VDC, and the receiver is
supposed to allow for some voltage loss in long cables. Some transmitters in low power
devices (like portable computers) sometimes use only +5 VDC and -5 VDC, but these
values are still acceptable to a RS232-C receiver, provided that the cable lengths are
short. these voltages are shown in Figure 2

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Figure 2

The original RS–232 standard was defined in 1962. As this was before the days of TTL
logic, it should not be surprising that the standard does not use 5 volt and ground logic
levels. Instead, a high level for the driver output is defined as being +5 to +15 volts and a
low level for the driver output is defined as being between –5 and –15 volts. The receiver
logic levels were defined to provide a 2 volt noise margin. As such, a high level for the
receiver is defined as +3 to +15 volts and a low level is –3 to –15 volts. Figure 3
illustrates the logic levels defined by the RS–232 standard. It is necessary to note that, for
RS–232 communication, a low level (–3 to –15 volts) is defined as a logic 1 and is
historically referred to as “marking”. Likewise a high level (+3 to +15 volts) is defined as
a logic 0 and is referred to as “spacing”.

Figure 3

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Programming the AVR UART

Example

#include <avr/io.h>
#include <avr/interrupt.h>
#include <avr/signal.h>

typedef unsigned char u8;

void delay(void)
{
unsigned int count;
for( count = 0; count < 0xfff; count++);
}

void initUart (void)

{
UBRRL = 0x0c;
UCSRB = 0x18;
}

u8 rx (void)
{
while ((UCSRA & 0x80) != 0x80);
return (UDR);
}

void tx (u8 d)
{
while ((UCSRA & 0x20) != 0x20);
UDR = d + 1;
}

main ()
{
initUart ();
tx ('X');
while (1)
{

tx ('d');
delay();
}
}

Figure 1

Insert the relevant values into the registers, compile and load. Ensure that you connect
the RXD and TXD pins (also marked as RS232 SPARE) to PD0 and PD1.

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Now open Hyperterminal, set to 4800 bits/sec, 8 bits, no parity, 1 stop bit and no
handshaking and view. Once you have got the hang of this program, modify main() as
shown below:

main ()
{
initUart ();
delay();
tx ('X');

while (1)
tx (rx ());
}

An extract from the Atmel data sheet for the USART

Register Description

UART I/O Data Register

UDR
UDR( address 0x0C)
7 6 5 4 3 2 1 0
UDR Read MSB LSB
UDR Write MSB LSB

The UART Transmit Data Buffer Register and UART Receive Data Buffer Register
share the same I/O address.
The transmit buffer can only be written to when the UDRE flag in the UCSRA register is
set. When the data is written to the transmit buffer, and the transmitter is enabled, the
transmitter will load the data into the transmit shift register when the shift register is
empty.. Then the data will be serially transmitted on the TxD pin.

UART Control and Status Register UCSRA (address 0x0B)

7 6 5 4 3 2 1 0
UCSRA RXC TXC UDRE FE DOR PE U2X MPCM

Bit 7 – RxC: UART Receive Complete

This flag is set when there are unread data in the receive buffer and cleared when the
receive buffer is empty. If the receiver is disabled, the receive buffer will be flushed and

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the RX bit will become zero. The RxC flag can be used to generate a Receive Complete
Interrupt.

Bit 6 – TxC: UART Transmit Complete

This flag bit is set when the entire frame in the transmit shift register has been shifted out
and there are no new data currently present in thr transmit buffer (UDR). The TxC flag is
automatically cleared when a transmit complete interrupt is executed, or it can be cleared
by writing a one to its bit location. The TxC flag can be used to generate a Transmit
Complete Interrupt.

Bit 5 – UDRE: UART Data Register Empty

The UDRE flag indicates if the transmit buffer (UDR) is ready to receive new data. If
UDRE is one, the buffer is empty, and therefore ready to be written.

The rest of the bits in this register are not required for our purposes.

UART Control and Status Register UCSRB (address 0x0A)

7 6 5 4 3 2 1 0
UCSRA RXCIE TXCIE UDRIE RXEN TXEN UCSZ2 RXB8 TXB8

Bit 7 – RXCIE: RX Complete Interrupt enable

Writing this bit to one enables interrupt on the RXC flag. A UART Receive Complete
Interrupt will only be generated if the RXCIE bit is written to one, the global interrupt
enable flag in SREG is written to one and the RXC bit in UCSRA is set.

Bit 6 – TXCIE: TX Complete Interrupt enable

Writing this bit to one enables interrupt on the TXC flag. A UART Transmit Complete
Interrupt will only be generated if the TXCIE bit is written to one, the global interrupt
enable flag in SREG is written to one and the TXC bit in UCSRA is set.

Bit 5 UDRIE: UART Data Register Empty Interrupt Enabled

Not used

Bit 4 – RXEN: Receiver Enable

Writing a one to this bit enables the UART receiver. The receiver will override normal
port operation for the RxD pin when enabled. Disabling the receiver will flush the
receive buffer.

Bit 3 – TXEN: Receiver Enable

Writing a one to this bit enables the UART transmitter. The transmitter will override
normal port operation for the TxD pin when enabled.

The rest of the bits in this register are not required for our purposes.

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The UART Baud Rate Registers – UBRRL and UBRRH( address 0x09)
7 6 5 4 3 2 1 0
UBRRH URSEL ----- ----- ----- UBBR11 UBBR10 UBBR9 UBBR8
UBRRL UBBR7 UBBR6 UBBR5 UBBR4 UBBR3 UBBR2 UBBR1 UBBR0

The following UBRR setting are using a clock rate of 1 MHz.

Baud Rate (bps) U2X = 0 U2X = 1

UBRR UBRR
2400 25 51
4800 12 25
9600 6 12
14400 3 8
19200 2 6

ASCII Character Set

This page shows a chart and table of the American Standard Code for Information
Interchange (ASCII) character set. Each ASCII character has a corresponding 7-bit code;
practically all modern computers follow this correspondence in their character displays.
Note that the coding for ASCII characters runs from 00 to 7F (hex). Characters from 80
to FF (hex) (using an 8-bit code with the MSB set to 1) are not defined in ASCII. Use of
these additional codes varies widely among computer systems.

ASCII Chart

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 Physical Device Controls: Format Effectors

• BS: Backspace
• HT: Horizontal Tab
• LF: Line Feed
• VT: Vertical Tab
• FF: Form Feed
• CR: Carriage Return

Physical Device Controls: Other

• BEL: Bell
• DC1, DC2, DC3, DC4: No assigned meaning in ASCII, but DC1 and DC3 are
used for XON and XOFF in most software handshaking schemes.

Logical Communications Controls

• SOH: Start of Header

• STX: Start of Text
• ETX: End of Text
• EOT: End of Transmission
• ENQ: Enquiry
• ACK: Acknowledge
• DLE: Data Link Escape
• NAK: Negative Acknowledge
• SYN: Synchronous Idle
• ETB: End of Transmission Block

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 Physical Communications Controls

• NUL: Null
• DEL: Delete
• CAN: Cancel
• EM: End of Medium
• SUB: Substitute

Information Separators

• FS: File Separator

• GS: Group Separator
• RS: Record Separator
• US: Unit Separator

Controls for Code Extensions

• SI: Shift In
• SO: Shift Out
• ESC: Escape

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