Half Adder

Source Code of HA

`timescale 1ns / 1ps

module halfadder(a,b,s0,c0);

input a,b;

output s0,c0;

assign s0=a^b;

assign c0=a&b;

endmodule

Test Bench

`timescale 1ns / 1ps

module test_halfadder;

reg a,b;

wire s0,c0;

halfadder m1(a,b,s0,c0);

initial

begin

a=0; b=0;

#10 a=0; b=1;

#10 a=1; b=0;

#10 a=1; b=1;

#10 $stop;

end

endmodule
A test bench calls out (or “instantiates”) the Verilog source file to be
simulated (often called the “Circuit Under Test, or CUT), it drives all
the inputs to the CUT, and it defines how the inputs change over
time.
 Full Adder

Source code:
`timescale 1ns / 1ps
module fa(a,b,c,sum,carry);
input a,b,c;
output sum,carry;
assign sum=a^b^c;
assign carry=a&b|b&c|c&a;
endmodule

Test Bench:

`timescale 1ns / 1ps

module test_fa;
reg a,b,c;
wire sum, carry;
fa m1(a,b,c,sum,carry);
initial
begin
a=0; b=0; c=0;
#10 a=0; b=0; c=1;
#10 a=0; b=1; c=0;
#10 a=0; b=1; c=1;
#10 a=1; b=0; c=0;
#10 a=1; b=0; c=1;
#10 a=1; b=1; c=0;
 #10 a=1; b=1; c=1;
#10 $stop;
end
endmodule
 Half -Subtractor
Source code

`timescale 1ns / 1ps

module hs(a,b,d,b0);

input a,b;

output d,b0;

assign d=a^b;

assign b0=~a&b;

endmodule

Test Bench

`timescale 1ns / 1ps

module test_hs;

reg a,b;

wire d,b0;

hs m1(a,b,d,b0);

initial

begin

a=0;b=0;

#10 a=0; b=1;

#10 a=1; b=0;

#10 a=1; b=1;

#10 $stop;

end

endmodule
 Full Subtractor
Source code

`timescale 1ns / 1ps

module fs(a,b,c,d,b0);

input a,b,c;

output d,b0;

assign d=a^b^c;

assign b0=~a&b|b&c|c&~a

endmodule

Test Bench

`timescale 1ns / 1ps

module test_fs;

reg a,b,c;

wire d, b0;

fa m1(a,b,c,d,b0);

initial

begin

a=0; b=0; c=0;

#10 a=0; b=0; c=1;

#10 a=0; b=1; c=0;

#10 a=0; b=1; c=1;

#10 a=1; b=0; c=0;

#10 a=1; b=0; c=1;

#10 a=1; b=1; c=0;

#10 a=1; b=1; c=1;

#10 $stop;

end

endmodule
Source Code

`timescale 1ns / 1ps

module mul12(i0,i1,i2,i3,s1,s0,op);

input i0,i1,i2,i3,s1,s0;

output op;

assign op=(~s1&~s0&i0)|(~s1&s0&i1)|(s1&~s0& i2) |(s1&s0&i3);

endmodule

Test Bench

`timescale 1ns / 1ps

module test_mul12;

reg i0,i1,i2,i3;

reg s1,s0;

wire op;

mul12 m1(i0,i1,i2,i3,s1,s0,op);

initial

begin

{i0,i1,i2,i3}=4'b1010;

{s1,s0}=2'b00;

#10{s1,s0}=2'b01;

#10{s1,s0}=2'b10;

#10{s1,s0}=2'b11;

#10$finish;

end

endmodule