Design and implement Synchronous mod-6 UP counter using T

Flipflop
Truth Table
state Next state

Q1 Q2 Q3

0 0 0 0 0 1

0 0 1 0 1 0

0 1 0 0 1 1

0 1 1 1 0 0

1 0 0 1 0 1

1 0 1 0 0 0

Logic Diagram
Code
library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

entity mod_6_up_counter is

port (

clk : in std_logic;

rst : in std_logic;

q_out : out std_logic_vector(2 downto 0)

);

end entity mod_6_up_counter;

architecture Behavioral of mod_6_up_counter is

signal t1, t2, t3: std_logic;

begin

process(clk, rst)

begin

if rst = '1' then

t1 <= '0';

t2 <= '0';

t3 <= '0';

elsif rising_edge(clk) then

t1 <= not t1;

if t1 = '1' then

t2 <= not t2;

if t2 = '1' then

t3 <= not t3;

end if;

end if;

end if;
 end process;

q_out <= t3 & t2 & t1;

end architecture Behavioral;

Waveform

Design and implement Synchronous mod-6 DOWN counter using T Flipflop

Truth Table

state Next state

Q1 Q2 Q3

1 0 1 1 0 0

1 0 0 0 1 1

0 1 1 0 1 0

0 1 0 0 0 1

0 0 1 0 0 0

0 0 0 1 0 1
Logic Diagram

Code
library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity mod6_down_counter is

Port ( clk : in STD_LOGIC;

rst : in STD_LOGIC;

count : out STD_LOGIC_VECTOR (2 downto 0));

end mod6_down_counter;
architecture Behavioral of mod6_down_counter is

signal q : std_logic_vector(2 downto 0);

begin

process(clk, rst)

begin

if rst = '1' then -- Reset

q <= "111";

elsif rising_edge(clk) then

if q = "000" then

q <= "111"; -- Roll-over

else

q <= q - 1; -- Decrement

end if;

end if;

end process;

count <= q;

end Behavioral;

Waveform