Saturated Iron Core Superconductor and Thyristor
based DC Fault Current Limiter for HB-MMC
Hidayat Ur Rehman
Department of Electrical Engineering
UET Peshawar
Peshawar, KPK, Pakistan
hidayat0625@gmail.com
Abstract — Last three decades have witnessed exponential
2021 IEEE Open Conference of Electrical, Electronic and Information Sciences (eStream) | 978-1-6654-4928-1/21/$31.00 ©2021 IEEE | DOI: 10.1109/ESTREAM53087.2021.9431410
growth in necessities of limiting DC fault current and instant
restoration of High Voltage DC power systems. In this paper,
Half Bridge Modular Multilevel Converter (HB-MMC) has
been investigated for DC fault current. Half Bridge Modular
Multilevel Converter is unable to clear DC fault current due its
free-wheeling diodes, therefore it is indispensible to confine DC
fault current. For limiting DC fault current and instant
restoration of system, Thyristor based DC fault current limiter
and Saturated Iron Core Superconductor fault current limiter
(SI-SFCL) is analyzed with Hybrid DC Circuit Breaker
(HDCCB). The Thyristor based fault current limiter consists of
thyristor, resistor and an inductor. SI-SFCL consists of
primary, secondary and superconducting coil. The Thyristor
based DC fault current Limiter confine fault current to 2.5 kA
from 14 kA which show 82% suppression of DC fault current,
while SI-SFCL confine fault current to 3.5 kA from 14 kA which
shows 75% suppression of DC fault current. The restoration
time achieved from TB-FCL with HDCCB is 28 ms and from SI-
SFCL with HDCCB is 140 ms. A PSCAD/EMTDC is used to
design and simulate HB-MMC, SI-SFCL, TB-FCL and HDCCB
Keywords — DC fault Current, Half Bridge Modular
Multilevel Converter (HB-MMC), Hybrid DC Circuit Breaker
(HDCCB), Saturated Iron Core Superconductor Fault current
Limiter (SI-SFCL), Thyristor Based DC Fault Current Limiter
(TB-FCL)
I. INTRODUCTION
HVDC transmission systems are emerging as highly
efficient, reliable and an economical solution to be connected
with remotely located energy sources. The developments that
are recently made in voltage source converter HVDC
substitute the conventional line commutated HVDC
Converters [1, 2]. HVDC system utilizes two level VSC
system for amalgamation of DC load and distributed
generations to make system feasible. However, It has some
drawback such as high switching frequency, high power loss,
low quality and harmonics [3]. In order to eradicate these
problems, Modular Multilevel Converter is designed based on
VSC system. This converter has the capability to attain
comparable frequency with lower switching frequency, high
efficiency, extensibility, outstanding output waveform, low
harmonic distortion due to large number of sub-modules and
achieving of high level voltage through their modular
structure thus make it a better choice to select for HVDC
system [4].
Sub-modules are the integral part of MMC. In MMC, there
are two sub modules i.e. Half Bridge and Full Bridge sub
module. Half Bridge sub-modules are unable to clear fault
current due to its free-wheeling diodes which behaves as an
unconstrained bridge even each IGBT device in sub-modules
are blocked. On the other hand, Full Bridge sub- module
978-1-6654-4928-1/21/$31.00 ©2021 IEEE
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Amjad Ullah Khattak
Department of Electrical Engineering
UET Peshawar
Peshawar, KPK, Pakistan
amjad67@gmail.com
proficiently interrupting the fault current. Due to these
constraints, HB-SM is establishing itself as an efficient and
widely used technology for DC grid applications. HB-SM
offers advantage of compact size, low power loss and low
cost. Therefore, it is requisite to use external protection device
for confining DC fault current in HB-MMC based HVDC grid
applications [5, 6].
DC fault current needs to be confined due to no crossing
point. Some external scheme has to be applied to achieve this
goal of power system. In case of AC, it is easier to clear AC
fault current as the AC fault current always cross the zero
crossing point. Numerous researchers have published several
papers on interruption and limitation of DC fault current for
HB-MMC. Several papers come up with their best ideas to
confine and clear the DC fault current for High Voltage Direct
Current applications.
An external pre-charged capacitor to confine DC fault
current in HB-MMC is presented in [7]. The proposed method
subsume of two external pre-charged capacitor in which each
capacitor has connected in series with HVDC poles. During
normal operation, the pre-charged capacitors are bypassed but
when DC fault occur, the pre-charged capacitors have inserted
in DC current path for fault suppression. A stage current
limiting scheme of HDCCB for HB-MMC is proposed in [8].
The proposed scheme is based on HDCCB and consists of
main branch, current limiting branch and transfer branch. The
main branch subsume of ultra fast disconnector (UFD) and
Load commutation switch (LCS). The current limiting branch
consist of UFD and reactor. And the transfer branch consists
of full bridge sub-modules which further divided into resistive
type and capacitive type. The proposed scheme reduced fault
current to 8 kA from 18 kA. Designing of an improved
modular multilevel converter with DC blocking capability is
presented in [9]. In proposed scheme two diode valves and two
director switches has been installed around one arm of HB-
MMC. During normal operation, Diode valves and director
switch did not change the direction of current. When fault
occur, the director switches are turned off and the reversed
bias voltage which is provided by one arm block the dc fault
current. Reference [10] refers to the designing of Hybrid
bypass method for limiting DC fault current in HB-MMC. In
proposed scheme, a bypass thyristor has been incorporated to
each HB-SM to take up the fault current until circuit breaker
did not clear the fault. The Author substitute redundant HB-
SM with redundant FB-SM in [11]. As FB-MMC has
capability to block fault current. So with FB-SM, the fault
current has been blocked. Author proposed a two modified
Modular Multilevel converter topologies for fault current
limiting in HB-MMC in [12]. One topology consists of single
IGBT pact, four diodes, IGBT switch and a capacitor. In
which switches operates like one leg of a 2-level half bridge
converter. Second topology consists of three IGBT packs and
a capacitor in each modules. The disadvantage of this method
is higher losses and an intricate structure due to increase in
semi-conductor devices. Designing of a unprecedented design
of superconductor fault current limiter is presented in [13].
This method brings down the DC fault current value to 10 kA
from 20 kA. The author study the effect of a number of
superconducting rings on limiting the fault current. The main
disadvantage is large size due to large number of
superconducting rings and also the author confine the fault
current to 50% of its maximum value. Design of an enhanced
fault current limiter with Direct Circuit Breaker to limit fault
current is presented in [14]. This design clear DC fault current
of Half Bridge Modular Multilevel Converter. The enhanced
fault current limiter technique subsume IGBT, thyristors,
resistor, inductor and metal oxide resister. With increasing
value of resistor, the fault current has bring down to 4 kA from
12 kA which is tantamount to 67% of fault current reduction
and with the decreasing inductance, the DC fault current has
also reduce to 67% of fault current. Design of SI-SFCL of 15
KV, 3 kA VSC is presented in [15]. This design limit the DC
fault current to 70% of its maximum value. An active SI-
SFCL with and without metal oxide arrestor for confining DC
fault current in VSC-HVDC system is designed in [16]. When
only active SI-SFCL has connected, fault current has been
reduced to 40 kA from peak 60 kA.
Author proposes a bridge type SFCL which consist of four
coils, two permanent magnet and iron core with four limb in
[17]. The proposal method limit the fault current to 70 A from
100 A. SI-SFCL with combination of Hybrid DC circuit
Breaker for HB-MMC is designed in [18]. This method have
limiting capability upto 50% of its maximum value. Author
proposed a parallel resonance type fault current limiter, which
consist of bridge part and resonance part in [19]. The bridge
part consist of diode, de-limiting reactor, thyristor and IGBT.
The resonance part consists of parallel inductor and capacitor.
The thyristor in the bridge part has been used to limit fault
current. The proposed method limit the fault current to 600 A
from 2.5 kA. Author proposed four topologies in [20]. These
topologies are based on thyristor to limit fault current. 1st
topology consists of simple forced commutation circuit with
metal oxide arrestor. 2nd topology consists of forced
commutation circuit with two additional thyristors to avoid a
capacitor. In 3rd topology, a transformer with low inductance
has been integrated into the circuit with capacitor and
thyristor. In 4th topology, the thyristor in 3rd topology has been
replaced by temperature dependent resistor with a positive
temperature co-efficient. All topologies limit the fault current
upto 70%. Author proposed series resonant fault current
limiter (SRFCL) which consists of capacitor, resistor and
bypass circuit, the bypass circuit is the main circuit in SRFCL
to limit the fault current in [21]. The SRFCL limit the fault
current to 50 kA from 80 kA. Design of a thyristor based fault
current limiter with combination of capacitor, inductor and
Hybrid DC circuit Breaker is presented in [22]. The proposed
design limits the fault current to 62.1% from its maximum
value. The need engender to design a fault current limiter
which is better than the preceding ones.
This paper proposed a conceptual design of TB-FCL and
SI-SFCL for HB-MMC of large DC power systems. Firstly,
the electrical characteristic and operating principle of TB-FCL
and SI-SFCL were analyzed and then a detailed design
process and a corresponding configuration of the TB-FCL and
SI-SFCL were proposed and applied to HB-MMC. After
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designing of TB-FCL and SI-SFCL, the HDCCB is connected
in series with SI-SFCL and TB-FCL to investigate the
breaking capacity and restoration of DC system.
The rest of the paper is structured as follow: Section II
explains the conceptual design of SI-SFCL, TB-FCL and
HDCCB. Section III explain the simulation results of fault
current limiter and circuit breaker. Section IV discussed
conclusion and future work.
II. CONCEPTUAL DESIGN OF SI-SFCL,
TB-FCL AND HDCCB
A. Configuration of SI-SFCL for HB-MMC
Superconductor fault current limiter has ideal fault
characteristics such as low impedance during normal state and
high impedance during short circuit current. Due to
impedance characteristics, SFCL has been classified into
resistive type, flux type, magnetic shield type, inductive type
and diode bridge type. Inductive type SFCL has high
reliability and does not rely on quenching as required by
resistive type SFCL. Therefore, Inductive type SFCL has
widely used as fault current limiter for HVDC system.
Saturated iron core SFCL is most widely used type of
inductive type SFCL. In 1980’s, the original concept of SI-
SFCL was proposed by B. P. Raju and was widely used in AC
system to limit AC fault current. With good limiting capability
for AC fault current, the concept of SI-SFCL extended to DC
power systems. The proposed structure of SI-SFCL consists
of two coil and one superconducting coil. The two coils are
primary coil and secondary coil. The primary coil is connected
directly to power system while the secondary coil is connected
to DC current source with ramp control, resistor, an inductor
and capacitor. The ramp rate control is used to limit the output
fluctuation. The secondary winding of SI-SFCL has low
power loss and can withstand large amount of current. The
proposed structure is shown in Fig. 1.
B1
ip is
R
DC Bias
DC
Supply
Np Ns Source
C
L
Primary Side
Iron Core
Secondary Side
B2
Fig. 1. Proposed structure of SI-SFCL.
As known that superconductor material has zero
resistance, due to this property, the secondary winding of
SFCL has withstand several hundred amperes of current.
When SI-SFCL is in current limiting state, the SI-SFCL show
non-linear inductance characteristic, therefore resistor and
capacitor has been ignored and simplified circuit has been
drawn as shown in Fig. 2. The cost of SI-SFCL has been
determined by the size of Iron core and number of windings
of DC and AC coils. The specifications of SI-SFCL design
simulated in PSCAD are: Transformer is 5 MVA, air core
reactance is 0.2 pu, resistance is 89 ohm, inductor is 1 H and
capacitor has a value of 1 F. In current limiting state, the SI-
SFCL show non-linear inductance. The non-linear inductance
is equal to [23].
 Vp ∆1 = 2
=
5& − ( &3 + ( &' (7)
+ - !µ

B. Configuration of TB-FCL for HB-MMC

Two types of fault current limiter are widely used in VSC-
if
Lnl HVDC systems namely superconductor fault current limiter
and solid state fault current limiter. Solid state fault current
+ -
limiters also referred as Non-Superconductor fault current
limiter. Solid State FCL are made of semiconductor devices.
Thyristor as compared to other semiconductor devices offer
Fig. 2. Simplified structure of SI-SFCL. several advantages as it have low on state losses, low cost,
high capability of blocking, light triggered and simple
connection. The thyristor has a distinctive property to control
= , (1) the current magnitude by providing gate pulse, due to this
property thyristor is used to control large amount of currents.
where = , is the length of the core and is the cross Another advantage lie in the possibility of series and parallel
connection of thyristor is to reach the available desired
sectional area and is the number of primary turns. The voltage. For high rating applications, the thyristor is more
cross sectional area of the transformer core and number of suitable candidate in term of cost and efficiency. The proposed
primary turns of transformer are calculated by using the design is simple and does not have any bypassing or switching
following formula: circuits. The proposed structure consists of total twelve
thyristor which are connected in parallel and are bi-directional
= 1.2 × √ , (2) as shown in Fig. 3. During normal state, current flow through
thyristor T7-T12 and when fault occur the current flow
= . (3) through thyristor T1-T6.The low value resistor and inductor is
. × × !× "
connected in series is to enforced equal sharing of current to
thyristor. The inductance and resistor has a value of 100.
where P is the rated power of system; #$ is the base frequency
of SI-SFCL, % is the maximum primary voltage, &' is the
maximum saturation of magnetic field.
The relationship between the magnetic flux density and T1 T2 T3 T4 T5 T6
primary current are [24]: R L

* +
() =
T12 T11 T10 T9 T8 T7
, (4)
,

where , () is the secondary current, ( is the primary current

and ) is number of secondary turns.
Fig. 3. Proposed structure of TB-FCL.
Using Energy calculation formula, the energy variation
from -. to -/ can be calculated and is equal to: C. Configuration of HDCCB
3 Due to no crossing point, it is nearly impossible to confine
∆1 = 23 %) () 5- = 2 5& − ( &/ + and clear DC fault current without the help of any scheme. In
4 4 µ
( &. , (5) case of AC, it is easy to clear AC fault current as the AC fault
current always cross the zero crossing point. To make it to
where &. and &/ are the flux densities at time -. and -/ . zero, the hybrid DC circuit breaker is leading technology for
HVDC system.
The energy variation after fault is
The HDCCB consists of three branches i.e. main branch,
; & auxillary branch and surge arrestor. The main branch also
∆1 = : 5& − ( &< + ( &'
!
µ called load current branch and consist of an ultra-fast dis-
&
=
connector (UFD) and load commutation switch (LCS) which
(6)
+ : 5& − ( &3 are connected in series. The UFD and LCS both made low loss
;
µ current path for HDCCB. The LCS contain IGBT which are
+ ( &< in parallel order for bidirectional interruption process and are
enough to commutate fault current to the auxillary branch.
where &' is the magnetic flux density before fault and &3 is Auxillary branch include IGBT cells which are in parallel to
magnetic flux density after fault. &' and &3 are the magnetic surge arrestor. Each IGBT cells contain IGBT modules which
flux density at saturation and non-saturated region. &< is the are parallel and their number of cell varies as voltage level
magnetic flux density at positive saturation point. At varies. The main purpose of auxillary branch is to carry large
saturation region, the variation of magnetic flux density is current when UFD switch is in opening process. The surge
negligible so &' = &< , the equation can be simplified as: arrestor is used to reduce fault current to zero and it also

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provide over-voltage protection to the IGBT’s cells of the A. SI-SFCL
auxillary branch. The design of HDCCB simulate in PSCAD
is shown in the Fig. 4. The SI-SFCL is designed as shown in Fig. 1 in PSCAD
and applied to 1000 MW power system of Half Bridge
Modular Multilevel converter. The operation of SI-SFCL are
as follow: When there is no fault in transmission line and
Load Commutation Switch
(LCS) system run smoothly, the dependent current source of
Residual DC
Current
Ultrafast
Disconnector
secondary coil engender the iron core to saturate and thus has
Breaker (RCD)
(UFD) a low magnetic permeability. Thus the primary coil behave
like an air core conductor and have a little effect on DC power
system. When fault occur, it is requisite that the iron core
does not saturate before IGBT switch turn off. Due to non-
Main Branch saturation of iron core, the magnetic permeability increases
and thus the inductance of primary coil increase which
confine the rise of DC fault current. When the iron core is
non-saturated, the relationship between primary voltage and
the inductor current is

Auxillary Branch
% = 5(> .
5- (8)

Surge Arrestor
Integrating eq (4) into eq (1) we get
Fig. 4. Structure of HDCCB.

*.
III. SIMULATION RESULTS % ∆- = 2* ? 5( , (9)
A 1000 MW power system is designed to transmit power
to a location which is 400 km away from the system. For where ∆- = -* − - , where - is the final moment at the
voltage of the SI-SFCL rises to %@ , -* is the initial moment
AC/DC and DC/AC conversion, HB-MMC is designed. The
when IGBT transfer branch turns off, ( ? and ( . are the
fault applied at mid of transmission line. The protection
inductor current at the moment of -* and - .
scheme includes each TB-FCL and SI-SFCL with HDCCB.
The HB-MMC test system parameters are shown in Table I.
Setting ( . and ( / as the current of inductor L when the
iron core is in positive and negative knee, then we get ( ? =
TABLE I. HB-MMC PARAMETERS
Parameters Value ( . and ( . ≤ ( / . By the relationship between the magnetic
Apparent Power 1000 MVA field intensity and the current ( = (C − ( ) we obtain
Active Power ±1000 MW
Reactive Power ±100 MVAr 2 &< ≥ % ∆-. (10)
Nominal DC Voltage ±420 kV
Nominal Frequency 50 Hz The results of SI-SFCL limiting DC fault current shown in
Number of cells per arm 76 Fig. 6. The DC fault current without SI-SFCL is 14 kA. When
Capacitance Leakage per 10 MΩ SI-SFCL is designed and applied to HB-MMC, the fault
Resistance current limited to 3.5 kA which show 75% reduction of fault
current from its maximum 14 kA value. The fig. 6 also shows
Maximum Fault Current 14 kA the results of HDCCB with cooperation of SI-SFCL. With the
Transmission Length 400 km help of HDCCB , the dc fault current forced to zero within 140
ms. SI-SFCL parameter are shown in Table II.

The main simulation model designed in PSCAD software TABLE II. PARAMETERS OF SI-SFCL
is shown in Fig. 5.
Parameter Value
DC voltage of system ±420 kV
Normal DC Current of system 2 kA
Maximum Fault Current 14 kA
Target of fault Current >70 %
Capacitor 1 µF
Inductor 1H
Resistance 89 Ω
Core Material 50PN470
Number of Primary Turns 198
Number of Secondary Turns 180

Fig. 5. Simulation Model designed in PSCAD.

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 When there is no fault the current passes through T7 to
T12 and the system run smoothly but when fault occur, in
order to protect IGBT from damage, the fault current flow
through T1 to T6. The flow of the current through thyristors
without fault is shown in Fig. 7 while flow of current through
thyristor when fault occur shown in Fig. 8.
Without TB-FCL, the dc fault current is 14 kA but when
TB-FCL is incorporated in system, the fault current limited to
2.5 kA. The TB-FCL shows 82% suppression of DC fault
current from its maximum value. The TB-FCL is connected in
series with HDCCB to make the current to zero and restore the
Fig. 6. Simulation Results Without SI-SFCL and With SI-SFCL and system. With the help of HDCCB the current is quashed to
HDCCB. zero within 28 ms.

B. TB-FCL
The proposed TB-FCL is designed as shown in fig. 3 in T4
T1 T2 T3 T5 T6
PSCAD and applied to 1000 MW power system of HB-MMC. L
R
In normal condition, the TB-FCL has no impact on power
quality. Moreover, it has no exceptional harmonic in steady T12 T11 T10 T9 T8 T7
state fault current limitation mode. The voltage equation
across fault current limiter is

5(F ⁄5- + H(F (-) = %IJKL-, (11)

Flow of current I

where L is the inductance, R is the resistor and V cos Lt is the
power of DC system and α is the firing angle of thyristor.
The main purpose of inductor is to produce sufficient
series inductance to keep di/dt with in capability of thyristor.
The resistor and inductor are parallel and their impedance is
Z = R/L.
The firing angle is in range of 90<N<120. The value of the
limiter inductance is determined from the limiter characteristic
equations which are [25].
Fig. 7. Flow of current when there is no fault.
Fig. 9 shows response of the power system before, during
and after clearing fault. When TB-FCL and HDCCB is
connected in series with HB-MMC, before fault the power
slowly reaches to 1000 MW and when fault occur at 2 sec, the
power dip to zero, with the help of HDCCB, the fault clear in
(12) minimum possible time and system restore to stable state.
Fig. 10 shows phase voltage when fault occur.
Flow of dc fault current If

VWX F
O = %L PQ Rsin L- − sin L -Y, (13)
+. VWX F T4
T1 T2 T3 T5 T6
R L
where
T12 T11 T10 T9 T8 T7

.
L = = ]L. (14)
Z [ \[

The term is magnification factor which accounts for Fig. 8. Flow of DC fault current.
+.
partial series tuning. The fault inductance is

= ^ + . + ). (15)

where ^ is the total inductance of transmission line and the

generator, . is the inductance of fault current limiter and
). is the series inductance of the load

'
. = ( ^ + ). ), (16)
+'

where
.
_L = . (17)
√\

Fig. 9. System Response of TB-FCL.

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 IV. CONCLUSION
The Authors presented two types of most used fault
current limiter which are superconductor and non -
superconductor fault current limiter. SI-SFCL is a type of
superconductor fault current limiter while Thyristor based
fault current limiter is a type of non-superconductor fault
current limiter. This paper present thorough and
comprehensive analysis of DC fault current limiters for HB-
MMC. The two types of fault current limiters have been
explained and then designed. The result shows that the TB-
FCL limit 82% DC fault current while the SI-SFCL limits only
75% DC fault current which is far better than previous
Fig. 10. Phase Voltages during Fault. technologies. The TB-FCL is better candidate than SI-SFCL
for limiting DC fault current in DC systems. The TB-FCL is
less expensive, having small size and more effective than SI-
SFCL. The future work includes small scale development of
TB-FCL.
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