INDEX

Sr. No. Contents Page No.

1 Introduction

2 Description

3 Physical Address Generation

4 Conclusion

5 Reference

INTRODUCTION

Physical address calculation in microprocessors refers to the

process by which the CPU translates logical addresses generated
by the program into physical addresses in the computer's
memory. This translation is essential for the CPU to access data
and instructions stored in the memory modules. The physical
address calculation involves several steps and components
within the microprocessor architecture.
 PHYSICAL MEMORY ADDRESS GENERATION

- One Mbyte (1024 Kbyte) of physical memory can be interface with the 8086
microprocessor because 8086 has 20 addresslines i.e. 220 = 1024 Kbyte or 1
Mbyte
- The segment registers are used to hold 16-bit of the starting address of four
memory segments.
- But 8086 has 20-bit address bus, so it can address any of 220 = 1 Mbytes in
memory.
- The address associated with any instruction or data byte is only 16-bit called as
effective address or offset or displacement or logical address.
- The logical addresses are used to calculate physical address.
 Advantages:
1. Memory Protection: Physical address generation allows for memory protection
mechanisms to be implemented. By mapping logical addresses to physical
addresses, the MMU can enforce access control policies, preventing unauthorized
access to certain memory regions. This helps enhance system security.

2. Memory Management: Physical address generation enables efficient memory

management techniques such as paging and segmentation. These techniques allow
the operating system to allocate and deallocate memory dynamically, optimizing
the use of physical memory resources.

3. Virtual Memory: Physical address generation facilitates the implementation of

virtual memory systems. Virtual memory allows programs to use more memory
than is physically available by utilizing secondary storage (like hard drives) as an
extension of RAM. This enhances multitasking capabilities and enables the
execution of larger programs.
4. Address Space Isolation: Physical address generation provides address space
isolation between different processes running on the system. Each process sees its
own virtual address space, which is mapped to different physical memory locations
by the MMU. This prevents processes from interfering with each other's memory,
enhancing system stability and security.

Disadvantages:
1. Overhead: Physical address generation introduces overhead in terms of additional
hardware (MMU) and software (memory management algorithms) required to
perform address translation. This overhead can impact system performance,
especially in real-time or performance-critical applications.

2. Complexity: Implementing physical address generation and memory management

techniques adds complexity to the system design. Developers need to carefully
design and optimize memory management algorithms to ensure efficient use of
memory resources while maintaining system stability and performance.

3. Fragmentation: Memory fragmentation can occur in systems employing physical

address generation, especially with dynamic memory allocation techniques like
paging and segmentation. Fragmentation leads to inefficient use of memory, as it
becomes fragmented into small, unusable chunks over time. This can degrade
system performance and require periodic memory defragmentation.
4. Hardware Cost: The hardware required for physical address generation, such as
the MMU, adds to the overall cost of the system. Additionally, more sophisticated
memory management techniques may require specialized hardware support, further
increasing the cost of implementation.

Overall, while physical address generation provides several advantages such as

memory protection, virtual memory support, and address space isolation, it also
comes with drawbacks such as overhead, complexity, fragmentation, and increased
hardware cost. Balancing these factors is crucial for designing efficient and cost-
effective computer systems.
Calculate the physical address if :

i. CS = 1200H and IP = DE00H

Ans:
Zero is inserted
1 2 0 0 0 CS
+ D E 0 0 IP
P.A = 1 F E 0 0

ii. SS = FF00H and SP = 0123H

Ans:
Zero is inserted
F F 0 0 0 SS
+ 0 1 2 3 SP
P.A= F F 1 2 3
iii. DS = 1F00H and BX = 1A00H for
MOV AX, [BX]
Ans:
Zero is inserted
1 F 0 0 0 SS
+ 1 A 0 0 SP
P.A = 2 0 A 0 0
 CONCLUSION
The physical address generation process in microprocessors
plays a pivotal role in enabling the CPU to access data and
instructions stored in the computer's memory. Through a series
of steps facilitated by components like the Memory
Management Unit (MMU), page tables, Translation Look aside
Buffer (TLB), and segmentation, logical addresses generated by
the CPU are translated into physical addresses that correspond to
specific locations in memory.

Reference
 Textbook