QUIZ - Datapath Design

Computer Organization

Qno.1. ​ Compare the data paths of ADD and SUB instructions of SAP; and then do the same
for ADD and OUT.
Solution:
The datapath of the ADD, SUB and OUT instructions along with control signals of the SAP:

Ring Counter ADD SUB OUT

State

T​1 MAR ← PC (E​p​, Lm )

T​2 PC ← PC + 1 ( C p )

T​3 IR ← RAM (CE, LI )

T​4 MAR ← IR (E I , LM ) OUT ← AC ( E A , LO )

T​5 B ← RAM ( CE, LB ) None

T​6 AC ← AC + B AC ← AC - B None
( S U , E U , LA ) ( S U , E U , LA )

Qno.2. ​In ARM ISA, besides LDA and STA, is there any other instruction that accesses
memory? If there is any describe the role and the necessity for its existence (specifically in
accessing memory)
Solution:
All load/store instructions in ARM ISA access memory such as (LDR,STR,LDM,STM etc.).
Apart from them, ​Register/Memory Swap (​SWP​)​ also accesses the memory. It reads the
contents of a memory location into one register and writes the contents of another register into
the same memory location in an uninterruptible pair of operations (atomic).
Its main use is in implementing operation on lock variables to coordinate correct operations on
memory data that are shared between programs in multiprocessor configurations.
the lock can also be used to control the access to resources (printer, scanner, file, etc), to build
synchronization mechanism, etc. The synchronization mechanims, you will learn in OS course.
Qno.3. ​ Compare Load-Store with free for all architecture. In free for all, any instruction can
access memory. Specifically compare the “variation in execution time” between these two
designs.
Solution:

Load-Store Architecture Free for All (Register-Memory)

(Register-Register)

Consists of simple instructions that take Consists of complex instructions that take
single cycle to execute multiple cycles to execute.

Complexity lies in compiler Complexity lies in microprogram

Execution Time: ​The performance is often
better than that of the register-memory
architecture because of the simplified
instruction set. The execution of instructions
is high due to use of many registers for
holding and passing the instructions.
However the performance also depends on
the code being executed and the
performance of the compiler.
Execution Time: ​The overall performance is
reduced by the slower clock speed. However
this architecture makes efficient use of
memory since complexity of instruction allows
to use less number of instructions to achieve
a given task, this could help in slightly
improving the performance.

Qno.4. ​Show that AND & NOT are sufficient to realize NAND, OR, NOR, and EXOR.
Solution:

i. NAND:
A ​NAND​ B = AB = NOT(A A
​ ND​ B)
ii. OR:
A ​OR​ B = A + B = A . B = ​NOT​(​NOT​(A) ​AND​ ​NOT​(B))
iii. NOR:
A ​NOR​ B = A + B = A B = N
​ OT(​ A) ​AND​ ​NOT(​ B)
iv. EXOR:

A ​XOR​ B = A ⊕ B = AB + AB = (A.B. (A.B)

Qno.5. ​Argue that 2’s complement addition is sufficient to realize arithmetic operations – MUL
and DIV
Solution:
Using control loops, MUL and DIV can be achieved by repeated 2’s complement addition(or
subtraction).
A*B is A added B times. A/B is B is subtracted from A until the remainder becomes less than B.
The number of subtractions give the quotient.
Qno.6. ​ What is the role of IR in SAP, what are the two types of values in an IR?
Solution:
The IR in SAP contains the instructions to be executed. The two types of values in an IR are
Op-code​ and ​Address​.

Qno.7. ​ Go find some ISAs and a comparison among them.

Solution:
Comparisons between some ISAs are:

Architecture Bits Type Design Instruction Branch Endianess

Encoding Evaluation

x86 16, 32, Register CISC Variable Condition Little

64 Memory code

Arm64/A64 64 Register RISC Fixed Condition Big

Register (32-bit) Code

MIPS 64 Register RISC Fixed Condition Big

(32→64) Register (32-bit) Register

Source:
https://en.wikipedia.org/wiki/Comparison_of_instruction_set_architectures#Instruction_sets

Qno.8. ​In a superscalar, a pipeline is a high-level view of datapath – is this True?

Solution:​ True.

Qno.9. ​You designed an ALU with Logisim. You also did a control circuitry for this ALU. What is
the nature of this control circuitry – is this a multiplexor?
Solution:
Yes. The selection between the various operations is through the multiplexer.