[IDEC강좌: 고성능 ADC 설계를 위한 이론 및 설계 기법]

Introduction to Data Converters

2012. 7. 2 ~ 3
Seung-Tak Ryu
stryu@ee.kaist.ac.kr
Time Table

일정 교육내용

[오 전]

○ Data converter intro (noise, linearity, FoM)

1일차 ○ Flash ADC

[오 후]

○ Flash ADC 설계 실습

[오 전]

○ Two-step and Pipelined ADC

2일차 ○ SAR, time-interleaving ADC

[오 후]

○ Pipeline ADC single-stage 설계 실습

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Outline

q General concepts
Ø Block diagrams of ADC/DAC
Ø Sampling theorem
Ø Simple operational principles
q Nonidealities in data converters
Ø Noise
Ø Nonlinearity
q Performance metrics

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Data Converters in Information Processing Sys.

q Analog/Digital interface

Audio
Amplificaion
Video Filtering
ADC
Frequency-
Conversion
Communication
Channels Data Aquisition
DSP
Data Distribution
Wireless, Cable
Amplificaion
Design automation
Filtering
Speaker Frequency- DAC Programmability
Conversion Process scalability
Display

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A/D Conversion - Example

Analog
Continuous
(Time, Amplitude)

Sampled sig.
Digital Cont. amplitude
Discrete Disc. time
(Time, Amplitude)

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Sampling and Aliasing

x * (t ) = x * (nT ) = å x(t )d (t - nT )
¥
L( x * (nT ) ) = å X ( s - jn 2pf s )
-¥

fs/2

Ø Ideal impulse generation?

§ Sampling is done at the transition edge of the sampling clock.

Ø Anything above fs/2 is folded into the signal band

§ Anti-aliasing filter needed

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Nyquist Sampling

q Nyquist sampling
Ø fsample >= 2BWsignal

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Sampling Circuit

q Track-and-Hold

Ø Sample the input at the falling edge of CLK

§ Track during CLK = 1, Hold it during CLK = 0.

Ø Good
§ Simple structure: one switch + one capacitor.
§ High speed operation.
Ø Bad
§ Limited charge: Output driver may be needed.
§ Many nonlinearities.
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A/D Conversion

q Implementation example: 2bit ADC

VREF
11
3/4 VREF
10
1/2 VREF
01
1/4 VREF
00
0

Ø Generate decision thresholds (reference voltages).

Ø Comparators compare the input signal with their references at every cycle.
Ø Encoder generates binary output using the outputs from the comparators.

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D/A Conversion

q Reference division or multiplication

Ø R-string DAC: reference voltage division (Vout = VREF/2N * D)
Ø Current-steering DAC: reference multiplication (Iout = IREF * D)

q Ex: R-string DAC

VREF
Analog
R
111
R
110
R
101
R
100
R
011
R
010
R
001
R
000
Digital
000 001 010 011 100 101 110 111

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Nonidealities in Signal Conversion

q Noise, Nonlinearity

Ideal Noise Distortion Distortion + Noise

SNR, DR THD, SFDR, INL SNDR, ENOB

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Noise

q Noise
Ø Quantization
Ø Noise from devices
§ Thermal (resistive)
§ Flicker (1/f)
Ø Sampling jitter

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Noise: Quantization Noise

q Quantization error: Difference between input and quantized output

111
110
101
100
011
010
001
000

• For resolution above 4 bits, • Probability density function of eq

eq can be regarded as random noise
1/D

• Assume eq is x
-D/2 D/2
- a random variable uniformly distributed
between -D/2 and +D/2 • Quantization noise power
- independent of the analog input D/2 1 D2 2
Vref
2 2
εq = ò x dx = =
- D/2 D 12 12 × 22N
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Noise: Quantization Noise

q Quantization noise limited SNR (Sampling frequency = fs)

2
æV 2 ö
Signal power(Psig ) = ç ref ÷
è 2 ø
Vref2
FS = Vref Noise power(Pnoise ) =
12 × 2 2N
P 3
SNR = sig = 2 2N
Pnoise 2

10 log SNR = ( 6.02N + 1.76 ) dB ~ ( 6N + 1.8 ) dB

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Noise: kT/C Noise

q Thermal noise in RC low pass network

Ø One sided spectral density of noise by R.

Up to THz à Up to THz à ?

¥ 2
1 Vn2,out =
2
V / Hz = 4kTR
n
H (s) = ò H (s) 4kTRdf
0
1 + sRC ¥ 4kTR
=ò 2
df
2 2 2
4p R C f + 1
0

kT
= , Or
C
1 p kT
Vn2,out = 4kTR ´ ´ =
2pRC 2 C
Noise BW
Sig. BW

Ø R is noise source, why kT/C?

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Noise: Sampling Jitter

q Wrong signal @ right time = Right signal @ wrong time

(when reconstructed with ideal clock)

Wrong signal @ right time Right signal @ wrong time

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Noise: Sampling Jitter

q Required jitter spec for N-bit ADC

Ø SNRjitter > SNRquantization
1 2
Dt rms <
2pfBW 2 N 3

[The Data Conversion Handbook,

Analog Devices, Elsevier2005]

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Nonlinearity

q Nonlinearity
Ø Circuit nonlinearity
§ Nonlinear switch on-resistance
§ Charge injection
§ Junction capacitance
§ Opamp nonlinearity
Ø Device mismatch
§ Resistor, capacitor, current source, differential pair offset and etc.

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 Nonlinearity: Sampling Circuit Nonlinearity

q T/H nonlinearity
Clock feedthrough
COV
ΔVo ~ - (VIN + VTH )
C + C j + COV

Charge injection (Vth)

Cox
ΔVo ~ - WL(VDD - VIN - VTH )
2(C + C j )

Ron nonlinearity Cj nonlinearity

(Vth, m)
C jo
Ron,P Ron,N Cj =
Vbias
1+
fbi

when tox = 10nm (0.35um process),

Ron,eq Cjo = 1 ~2 fF/u2
Vin
|VTHP| VDD-VTH Cox = 3.8fF/u2

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Nonlinearity: DAC Nonlinearity

q Example: R-DAC

Vout

Vref

Vj,ideal

Vj

D
j

Ø Device mismatch
Ø Transfer curve change à Harmonic distortion

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Nonlinearity: Differential/Integral Nonlinearity

tuptuO latigiD
D
DDNL - D
DNL = D (LSB)

Vref
DDNL where D = 2N

Analog Input

- DNL (Differential Nonlinearity)

. Maximum deviation from the ideal value of 1 LSB. Local error.
. Critical in control and video
- INL (Integral Nonlinearity)
. Maximum deviation from a straight line passes through end points. Global
error. INL = SDNL
. Critical in communications application (harmonic distortion).

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DNL/INL Profile Example

q 10b ADCs
<Ryu, ISSCC06> <Elzakker, ISSCC08>

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Other Errors

Offset error,
Gain error

Missing code,
Non-monotonic

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Performance Metrics

[dB] S Quantization noise limit SNR

SFDR 10 log SNR = ( 6.02N + 1.76 ) dB

D
N

S +D
SNR =
fs/2 N(= NQnoise + NCircuit )
SMAX
SFDR =
[dB] SNR Max tone
S
SNDR =
N+D
SNDR SNDR dB - 1.76
ENOB =
6.02
DR SMAX
DR =
Input SMIN@SNR = 0dB
0 [dBFS]

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Speed vs. Resolution

A VTH
DVTH = [mV] kT/C, 1/f,
WL

1/ WL 1/WL

Size vs. matching & noise

Resolution [bit] Settling accuracy

Speed [MS/s]
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Data Converter Performance Trend

q B. Murmann, "ADC Performance Survey 1997-2011” (ISSCC, VLSI)

(http://www.stanford.edu/~murmann/adcsurvey.html.)

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Speed vs. Resolution of Various ADC Types

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Figure of Merit (FoM)

q Walden, JSAC99, Apr.

P = Universal measure
of ADC performance

q Figure of merit for data converters

• Noise and linearity (SNDR, ENOB)
Power
• Accurate decision (conversion) in a give time: Speed FoM = ENOB
• Power consumption 2 fS

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