Cmos 혼성모드시스템설계 Adc

CMOS 혼성모드 시스템
설계 및 실습 - ADC
서강대학교 이 승 훈
[참고문헌] “CMOS 아날로그/혼성모드 집적시스템 설계,” 6장, 9장,
이승훈, 김범섭, 송민규, 최중호: 시그마프레스 1999년.
System-
System-on
on-
-a-Chip / ADC OVERVIEW
군사분야 가전/정보분야 통신/SDR분야
의료/영상분야
기계/MEMS 및 자동차분야
컴퓨터/멀티미디어분야
기타 미래의 첨단 정보기술산업의 많은 분야
반도체 IC 없이 가능한 일은 ?
System-
System-on
on-
-a-Chip ((SoC
SoC)) Concept
SoC
• Logic : CPU, DSP

• Memory y : SRAM,, Flash , ROM,, EPROM,,
FeRAM, MRAM, DRAM
• Analog (FILTERS, ADC, DAC, PLL, SENSOR)
• CMOS RF
• Embedded FPGA
• MEMS
• Optoelectronic Function
Ubiquitous Digital Convergence
Mobiles
Communication MP3, Cellular phone,
MP3 phone
ATM, CDMA PDA, Notebook PC
High Speed Low Power

Consumer Multimedia Fusion
+
IC Card
Card, Lab Top PC
PC, C
Connectivity
ti it Products
Electronic Money +
Mobility “(SoC)”
Low Cost Reliability
Graphics
DTV,, Digital
g Camera,,
Networking
DVD, CMOS Image WLAN
A/D 변환기 (ADC) 및 D/A 변환기 (DAC) 응용 사례
■ 무선 통신 회로
RF 신호 아날로그 디지털
LNA ADC DSP

PA SYN DAC
입출력 : 수 GHz의 RF (Radio Frequency) 신호 LNA : Low Noise

Amplifier
기 능: PA : Power
P Amplifier
A lifi
SYN : Synthesizer
- RF 수신 신호의 정보를 디지털 신호로 변환 및 처리
DSP : Digital Signal
- 처리된 디지털 정 를 RF 신
정보를 신호로 변환하여 송신 Processor
A/D 변환기 (ADC) 및 D/A 변환기 (DAC) 응용 사례
■ Camcorder 응용 회로 (A/D Interface Circuit : CCD, CIS 등)
CCD IMAGE SENSOR INTERFACE CIRCUIT
C S
CDS AGC
GC ADC
C DSP DAC
아날로그 신호
디 지 털 신호
기능 : CCD (Charge-Coupled Devices) Image Sensor로부터의

아날로그 영상 신호를 디지털 신호로 변환
CDS : Correlated
C l t d Double
D bl Sampler
S l
AGC : Automatic Gain Controller
응용 분야 : 캠
캠코더,
더, 디지털 스틸
틸 카메라, 스캐너
캐너 등
A/D 및 D/A 변환의 배경 및 필요성
아날로그 디지털 아날로그
A/D Digital Signal D/A

자연계 인간
변환기 Processor 변환기
자연계의 대표적 디지털 시스템

인간이 인식할 수
Computer, CD Player, DVD
모든 신호는 있는 신호는
MODEM, Telephone …
아날로그 (C
(Computer가
t 가 인식할 수 있는 아날로그
언어 사용)
디지털 처리 기술의 장점을 이용하기 위해서는 자연계의 아날로그 입력을 디지털 신호로
변환하는 A/D 변환기와 신호 처리후 디지털 출력을 아날로그 신호로 변환하는 D/A 변환기 등의
interface 회로가 반드시 필요
A/D 변환기 (ADC) 의 응용 분야 및 사양
■ 응용 분야 :
- 개인 휴대용 통신 기기, 고속 디지털 통신망, HDTV, 디지털 캠코더, DVD, LCD
모니터 컬러 스캐너 등 제반 시스템 IC (혹은 비메모리 IC) 응용분야
모니터,
- 최근 상용 전자 제품들의 성능이 크게 향상됨에 따라 고속도, 고해상도 및 특히
저전력, 소면적 A/D 변환기에 대한 요구가 급속히 증가
■ 응용 분야에 따른 A/D 변환기 사양 (예) :
해상도 속 도
응용 분야 (bits) (Sampling Frequency)
Modem 8 – 10 64 KHz
Digital Audio 16 44.1 KHz
HDTV 통신,
HDTV, 통신 Video 10 – 16 1 – 100 MHz
DVD 8-9 104 MHz
LCD 8 205 MH
MHz
Detailed ADC Applications
High energy physics MRI

16 Instrumentation Multicarrier/Multimode Cellular
Automatic test equipment Spectrum Analysis
Low amplitude signal
communication
Wireless communication Wireless infrastructure
XDSL WCDMA/TD-SCDMA/GSM 802.16d/e
highly integrated communication
14 phased array antenna system
Wi-Max Software Define Radio
Ultrasound Equipment HD Video
bit]
imaging system
CCD imaging
UTION [b
digitization
HDTV
Fax machine Cellular Cable Head-End Receiver
Medical imaging
12 Telecommunications
and digital video
base station
Communication
Digital communication Radar and satellite subsystem
Radar systems
applications receiver
RESOLU
Secure communication
Set-top boxes Digital oscilloscopes Multichannel /Multimode receiver
Test
10 IF and baseband equipment
Battery-powered Instruments
high speed modem, broadband wireless
Broadband communication
communications Cable modem Digital Beam
Scanners communication subsystems
Camcorder CCD Imaging
QAM/QPSK Video digitizing Digital oscilloscope

Gigabit ethernet LCD display systems
8 DIGITAL TV High speed digital
Code conversion for RGB video systems Direct RF downconverter
VIDEO PROCESSING communication Digital read-channel system
flat panel display Gigabit ethernet
Electro-Optics Disk-drive control for DVD SOC
DBS/
VSTAT Receiver Digital receivers
6 WLAN for high-bit-rate
communications
1 40 80 120 160 200 500 1600

SPEED [MSample/s]
Current Status of ADC Development
JSSC
[’00]
20 ISSCC
[’03] [’05][’08][’03] [’05] [’11] [’09] [’10] [’10] CICC
16
[[’04]
04][[’10]
10] [[’06]
06][[’04]
04][[’07]
07] [[’07]
07]
VLSI Symp.
AP-ASIC
[’06] [’04][’03] [’04] [’07][’01][’06] [’06] [’06][’10][’06][’08][’06][’06] [’07] APCCAS
14
[’01][’07] SGU IC Lab.
LUTION [[bit]
[’04] [’03] [’08][’10] [’08]

[’04] [’00] [’00]
[[’07]
07] [[’09]
09][’10]
[’06] [’06] [’96][’10] [’10][’08] [’01] [’03] [’04] [’06] [’05][’09] [’11] [’11]
12
[’03] [’00] [’96][’08][’07][’09][’04][’09] [’07] [’10] [’08] [’07][’06]
[’08]
[’10]
[’08] [’08] [’06][’07] [’06] [’09] [’07][’09][’08] [’07][’09] [’02] [’04] [’07] [’07][’04] [’10] [’06] [’09] [’07][’10] [’11]
10
RESOL
[’05] [’03] [’10] [’07] [’10] [’09][’07] [’07] [’07] [’10] [’10] [’05] [’03] [’07] [’08][’06] [’09]
[’09] [’11] [’09]
[’08] [’10]
[’07] [’07] [’01] [’00] [’04] [’04][’01] [’02] [’05] [’11][’07] [’08] [’10][’04] [’02]
8
[[’10]
10] [[’07]
07] [[’00]
00] [[’05]
05] [ 03] [[’04]
[’03] 04] [[’04]
04]
[’03] [’02] [’07] [’10]
[’03] [’09] [’08] [’02] [’02] [’01][’10][’06][’09][’10][’03] [’10] [’10][’08][’10]

6
[’04] [’06][’10][’08][’02][’10][’09] [’10]
[’08] [’08] [’06] [’07]
[’09] [’03][’03] [’08] [’06][’07]

4
0.25 1 50 100 150 200 500 1000 2000 10000

SPEED [MSample/s]
아날로그 신호와 디지털 신호 특성 비교
■ 기본적인 신호의 표현방법

아날로그 신호 샘플링된 아날로그 신호 디지털 신호
1 1 1
V(t) V(t) 1 1 0
1 0 1
1 0 0
0 1 1
t t 0 1 0
0 0 1
0 0 0
연속적 (Continuous) 이산적 (Discrete)
아날로그 시
■ 아날 시스템과 시스템
템과 디지털 시 혼성모드 시
템 및 혼성 시스템
템
아날로그 시스템 디지털 시스템 혼성모드 시스템

프로그램화
신호의 고밀도 집적 아날로그 시스템과
필터링, 증폭 등 설계 용이 디지털 시스템을
아날로그 경제적 하나의 칩으로
신호처리 높은 정밀도 구현
A/D 변환기 (Analog IC) 설계 및 제작 과정
ARCHITECTURE FUNCTION CIRCUIT DESIGN

SCHEMATIC AND SIMULATION
FLASH
BEHAVIORAL FREQUENCY AND
MULTI-STEP SIMULATION
PIPELINED TIME DOMAIN
YIELD ANALYSIS
FABRICATION LAYOUT
PHYSICAL IMPLEMENTATION PATTERN GENERATION

OF INTEGRATED CIRCUITS OF INTEGRATED CIRCUITS
PACKAGING TESTING EVALUATION
I.C. BONDING MEASUREMENTS REDESIGN

ON LEAD FRAME AND VERIFICATION OR NOT ?
A/D 변환기의 기본 설계 예제
Vin
+Vref
N-bit
디코더 디지털 출력
(Binary Code)
2N-1
-Vref
V f 비교기
비교기 출력 3-bit
예) 3-bit (Thermometer 디지털 출력
+Vref Code) (Binary Code)
Flash A/D 변환기
1111111 111
0111111 110
Vin 0011111 101 출력 = 101
0001111 100
0000111 011
0000011 010
0000001 001
0000000 000
-Vref
A/D 변환기 기본 회로 이해 (비교기 : Comparator)
 비교기의 정의 :
- 비교기는 작은 아날로그 입력 신호를 감지, 이를 증폭하여 디지털 신호를 출력하는 회로
 비교기의 용도 :
- A/D 변환기,
변환기 데이타 전송기,
전송기 스위칭 파워 정류기,
정류기 메모리 감지 증폭기 등
 비교기의 성능 척도 :
- 속도, 해상도, 전력 소모, 면적 등을 적절히 고려하여 설계하여야 고성능
 증폭기와의
폭기와의 차이점 :
- 증폭기 : 큰 DC 이득을 가지면서 닫힌 루프 구조로 동작하여 단위 이득 대역폭에

의해 속도
속 결정
- 비교기 : 열린 루프 구조이므로 신호 경로상의 –3dB 폴(pole)의 위치에 의해 속도

결정
비교기의 동작 원리
 Q2 HIGH :
CML
- 기준 전압 샘플링
Q2
C1
Q2
REFT
AMP LATCH  Q1 HIGH :
REFC
Q2
C2 - 입력 전압 샘플링 (INT, INC)
Q2
- AMP 출력단에 전압차 증폭
CLOCK
[(INT-INC)-(REFT-REFC)] * Amp Gain
CML
- 래치 출력단 리셋
C1
Q1
INT
AMP LATCH
INC  CLOCK HIGH :
Q1
C2
- 래치의 정궤환 동작으로 래치
CLOCK 출력 단에 디지털 신호 출력
- 버퍼단을 통해 최종 디지털
신호 출력
비교기의 회로도
VDD
INT CML TN TP
RESET
C1
REFT
REFC
C2
LATCH
FBIAS
INC CML
VSS
VDD
OUTC OUTT
VSS
INPUT SWITCH PREAMP LATCH

HSPICE 시뮬레이션 (Simulation)
Frequency Domain Analysis

Wave Symbol
A0:vdb( tn,tp ) 20
Voltage [dB]
10
0
1K 100K 10M 1G
Frequency [log]
Time Domain Analysis : Input of Comparator
Wave Symbol 70m
A1:v( int )
A1:v( inc )
Voltage [[lin]
A1:v( reft )
A1:v( refc ) 0
-70m
50n 60
60n 70
70n
Time [lin]
Time Domain Analysis : Output of Comparator
Wave Symbol
1.5
A1:v( outt )
A1:v( outc )
n]
Voltage [lin
-1.5
5
50n 60n 70n
Time [lin]
비교기의 회로도와 레이아웃 (Layout)
VDD
회로도 INT CML

TN TP
C1 RESET
REFT
REFC
C2
LATCH
FBIAS
INC CML VSS
VDD
OUTC OUTT
레이아웃 (CADENCE TOOL 사용)
VSS
INPUT SWITCH PREAMP LATCH

A/D Converter 시제품 (Prototype) 제작 및 Packaging
■ 시제품 제작
- 응용 분야. 시스템 사양 및 비용 등을 고려한 제작 공정 결정 및 설계
- 결정된 공정상의 소자 변수를 이용한 시제품 칩 설계 및 레이아웃
- CMOS 공정, BJT 공정, BiCMOS 공정 등 특정 공정으로 제작
■ Packaging
- 칩 동작 시 발생하는 열과 외부로부터의 충격에서 칩을 보호함
- 응용 분야, 비용 열 임피던스* (thermal impedance) 칩의 전력소모 등에 의한 패키징 형태 결정

분야 비용,
(*여기서 열 임피던스는 패키지가 칩으로부터 열을 발산시킬 수 있는 능력을 의미함)

Packaging 기법 및 종류
[ DIP : Dual
D l In
I line
li Package
P k ] [ QFP : Quad Flat Package ]
[ BGA : Ball Grid Array ]
[ CHIP ]
[ PGA : Pin Grid Array ]
시제품 A/D 변환기 측정 보드
Digital Power Buffer Power

g Input
Analog
Digital Outputs
O
( PC 또는 디지털측정
시스템 )
DUT D BUFFER
D.
Analog Power
시제품 성능 DEMO 및 측정 방법
D.S.P.
Processor
Data Acquisition PC
D.U.T. Screen
Board
Developed
Programs
(DNL, INL, FFT, etc.)
Clock, Signal,
Power Supply
ADC DESIGN BACKGROUND [1/9]
A. Transfer
a s e Function
u ct o
ENCODING
bN-1 D
Vin 11
ADC
b0 10 Mid-Tread
Analog Input Digital Output
01
00 A
1/4 2/4 3/4 4/4
Vin bN-1 bN-2

N2 b0 D
Dout = = + + + 11
VFS 2 22 2N
10 Mid-Rise
Vo = 1 LSB = VFS / 2N
01
00 A
1/4 2/4 3/4 4/4
B. Qua
Quantization
t at o Error
o
bN-1
Vin (t) A/D D/A Vout(t)

b0
+ -

Quantization Error !!
Vin (t) - Vout(t)
Vin(t) Vout((t))
 E
2
=
Vo2
=
VFS2
12 (12)( 22N)
t t
SNR 
2 X
2
=
E
Vin (t) - Vout(t)
and SNR increase by factor
0 of 2 for each bit or 6dB/bit
t
C. Finite Conversion Time
Analog
voltage VA(t) Aperture error
VX VX
For sinusoidal signal with A = VFS / 2
For N bit resolution A/D :

t
VX < VO = VFS / 2 N+1 = A/ 2N
Aperture time t
VX
Example : t =
2fA
VA(t) = Asin2
A i 2 ft VX
VX = A / 2N f
dVA(t) 1 1
= 2Af  t =
dt 2N+1 ff
MAX
 Need sample & hold
 Aperture error VX = 2fAt for high speed
D. Terminologies
① DNL (Differential nonlinearity)
- How uniform the transfer function step size are.
DNL = LSBwidth - CODEwidth

V(x) - V(x+1)
=1-
LSB
where V(x) and V(x+1) are the two bounding transition levels of output code x.
Fig.1 Illustration of DNL.

② INL (Integral nonlinearity)
- The deviation of code midpoints from their ideal location.

- The ideal code midpoint location :
Straight line between the first and last code midpoints.
Fig.2 Illustration of INL. Fig.3 Relationship of DNL and INL.

③ Offset error
- The deviation from the ideal location of the lowest
transition level on the ADC transfer function.
Voff = Vz - Videal
where Vz = first transition level voltage
Videal = 0.5 LSB
Fig.4 Illustration of offset error.

④ Gain error
- The difference in the slope of the actual and the ideal code center lines.
Fig 5 Illustration of
Fig.5
gain error.
⑤ Full scale
Fig.6 Illustration of
full scale range.
⑥ Resolution
- The number of distinct analog levels corresponding

to the different digital
g words.
- An N-bit resolution implies that the converter can

resolve 2N distinct analog levels.
⑦ Accuracy
- Absolute accuracy (includes the offset, gain and linearity errors)

The difference between the expected and actual
transfer responses
responses.
- Relative accuracy (excludes the offset and gain errors)

The maximum integral nonlinearity error
error.
Ex) 12-bit accuracy :

Error of converter < Full scale
212
⑧ Monotonicity
- The digital code is continuously increasing as
the analog input is continuously increased.
- Critical in control applications.
Fig.7 A nonmonotonic ADC

transfer function.
⑨ Stability
- The performance of an ADC can change with time,

temperature, and supply voltage.
- It is important to know whether the converter is monotonic
over its full temperature and supply voltage range.
ADC ARCHITECTURES (1/20)
A Charge Balancing ADC

A.
Vref -Vin
Slope: Slope:
RC RC
Vin
R Detect 0

Vin - Comparator
R + 0V Voltage-to-Frequency
 
Pulse
T
DN-1
Counter
-Vref D0 Vin X T = Vref X 
  RC RC
1 Vin 1
T = f = Vref X 
B Slope Type ADC
B.
C
① Dual slope
R
Vin - Vo
+
-Vref
Clock Counter
Vo slope 0 < t < t1 ;

Vin Vref
RC RC dVo = Vin
dt RC
t t1 < t < t2 ;
t1 t1 + t2 dVo = Vref
dt RC
dual slope
Vin Vref  Vin = Vref t2 Measured in digital

RC t1 =
RC t2 t1
Used for slow panelmeter or multimeter

② Triple
T i l slope
l  No
N op amp used d
( comparator only )
Vin
Vc
Vref
GND
I C
C
Comparator
t
slope : I -VA : IVAI > IVOSI

C
VC
Vref
Vin
0 t
-VA VTH
t1 t2 t3 Comparator
threshold voltage
~ - VA ( < 0 )
dVc = I ; must be kept constant

VC dt C
Vref ( cascode current source )
Vin
t1 = Vreff - VTH ; t2 = Vin
i - VTH
0 t dV/dt dV/dt
-VA VTH
t3 = - VTH
t1 t2 t3 Comparator dV/dt
threshold voltage
~ - VA ( < 0 ) Vin t2 - t3 Two digital subtracts
=
Vref t1 - t3 one divide
Current source ;
CV = I X t
Switch C
10V I 3
4ms = C = 2.5 X 10
Imin = 10 nA
A
I
C = 10-8 / 2.5X103
 4 pF
-Vcc
③ Tracking
ac g A/D
/ (servo / )  very
(se o A/D) e ysslow
o in msec
sec
Vin D/A
Track
Digital
up
Counter
down
Clock (very fast)
C. Successive Approximation ADC

f( )
f(x) f( ) = 0
f(x)
S/H D/A
Vin
digital ②④ ①
or
out 11
③ 2
1 x
T/H
SAR
VA
Vref
3
Vref
4
1 1 5 Vreff
8 8
4
Vin
1 9 Vref
Vref
2 16
t
1 0 0 1
Continue until you reach LSB
Vin Need not be linear “C”

VC = Vin - Voff
VA VC VA to VC match
D Weighted-C SAR ADC

D.
Initialization
① For unipolar inputs
VX
i. Initialization Top : VX = VOS 2N-1C 2C C C Cp

Bottom : Vin
ii. Switch bottom to GND VX = VOS - Vin
iii. Switch bottom of 2N-1C to Vref Total C = 2NC
Vin
VOS VOS - Vin Vref
2NC VX
2N-1C Vref Vin

iv VX = Vref
iv. = Vref to GND Vref Vref
2NC 2 VOS - Vin + VOS - Vin + +
2 2 8
check comp output go ahead VOS
Vref
4
+ back to ground
t
C Vref Vreff
V MSB to Vref Vref
v. LSB C to Vref VX = Vref = N 2
N
2 C 2 Vref 8 16
VOS-Vin 1 0 0 1
S/H MSB LSB
■ Advantages
- Insensitive to CP since VX start from VOS ends at VOS
- Only comparator required
- 10bit capacitor matching used
- 100 kHz ~ 1 MHz voice digitizer good

telephone ch
② For bipolar () inputs ; - Vref  Vin  Vref
SIGN MSB VX
C C C
2 4
i. Sign bit samples Vref

ii. Other bits sample Vin
Vref Vin
iii Parasitic at VX is negligible
iii.
(a) Positive input ; 0  Vin  Vref
VX
SIGN 1 0 0 1
VOS
0 t
Vref Vref Vref Vref

4 8 16 32
VOS - Vin
2 sign bit not
not-changed
changed
(digital 0)
(b) Negative input ; -Vref  Vin  0
Return SIGN bit to GND!
VX
VOS - Vin
2
Vref
2
VOS
0 t
Vref Vref
4 8
SIGN MSB
“0” “1”
Two’s complement for negative number
C ( a little large ) C ( a little small )

D D
A A
Vref Vref
Gain error Missing code!

Gain error
E R+C or C+R ADC
E.
Vref LSB
MSB
R+C
R C
ADC
C+R
ADC
Vref
MSB
LSB
F High-Speed ADC
F.
① Parallel Processing : Time Interleaved
8 Bit
Vin 8 Bit Dig out
8 Bit
N Bit (8) Problems: Clock skew

M way Interleaved (4) Feedthrough
M2Nunits
it off C (1024) VOS matching
t hi
M comparators (4) DAC gain error
’93. April. JSSC

② Flash ADC : Fastest in all of the current architectures
Vref
N Bit (8)
0
2N R (256R)
0 (2N-1) comp. (255)
complete
1 conversion (1 cycle)
1
cf 10 bit  200 MHz
cf.
1 2W ECL
Vin
③ Pipelined ADC
2 2
2Vin-Vref >0
Vin + +
 
- -
S/H Vref S/H MSB 1
MSB=1
Vref
0 1 Vref Vin
GND 2
Vref
(a) Reference Restoring Method
① 2Vin - Vref > 0 Bit = 1

Next stage samples 2Vin - Vref
② 2Vin - Vref < 0 Bit = 0
Next stage samples 2Vin
Vres = Residual Voltage = 2Vin - Vref or 2Vin
(b) Reference Non-Restoring Algorithm
① 2Vin - Vref > 0 Bit = 1

Next stage samples 2Vin-Vref
② 2Vin - Vref < 0 Bit = 0
N t Stage
Next St Samples
S l 2Vin
2Vi - Vref
V f
Use -Vref in the next stage
2(2Vin) - Vref = 2(2Vin - Vref) - ( -Vref)
= 4Vin - Vref
(c) MOS Implementation
C C
2C 2C
Vin - -
+ + 2Vin-V
Vref
Vref
C C
Sampling Amplifying
① Charge Injection ③ Required OP Finite Gain

② C Mismatch 10 Bits A0 > 1000
14 Bits A0 > 16000
(d) Better MOS implementation (only 2C used)
C
-
+ -
Vin Vin +
+ -
C
Vin
- +
Vin
+ -
+ Vref -
2Vin Vref
- Vref +
④ Compromise between speed vs. size (chip) power

 Two-Step Flash
10 bit
25
5 bit
bits
Vin
Flash Flash
5 bit DAC 5 bit
S/H
ADC - +
ADC
MSB S
LSB
Residual Voltage
Digital
① 2 Decision
Q ② Differential Amp
① ③ D/A Delay
after
A/D
Residual
Vin
② Vref  N bits
 2N/2 R
after D/A
 (2N/2 - 1) comp
 1 op amp
 two cycles
l
③
G Smallest (Area Effective) ADC ( algorithmic,
G. algorithmic cyclic or pipelined ADC)
① Sampled inverter
C2 

Vin C1 Vin
Vin
- GND
GND +
Vin
Vo GND
② D/A converter
1
2
Vx C C C
Vref - C (a) Start from LSB
-
GND +
Vy(out) + (b) S
Sample
l Vref , Sample
S l GND
C/2
( 2C for ADC) Bit = “1” Bit = “0”
( Vin for ADC )
Vz
HIGH-
HIGH-RESOLUTION ADC [1/21]
A. Oversampled  ADC
DIGITAL
Fs ENCODING
ANTI-ALIAS
LP FILTER
HIGH
ANALOG DIGITAL RESOLUTION
INUPUT MODULATOR PROCESSOR
DIGITAL
(DECIMATOR) 16 OUTPUT
ANALOG DIGITAL
Oversampling A/D Converter System
 16
16-bit
bit SNR over audio band (20 kHz)
 High tolerance to analog circuit imperfections
 Sample low-order prefilter
 Digital decimation filter (LPF)
HIGH-
① First order interpolative modulator (Delta sigma)
1-bit
ADC
+ -
X(t) + Y(t)
Analog +
Input - Digital
O
Output
1-bit
DAC
E(z)
X(z)
+ + Y(z)
+ + Z-1 +
- + ADC
DAC
Linearized Model
HIGH-
② Second order interpolative modulator
+ + 1 bit
1-bit
X(t) + + Vi(z) + (1-z-1)2 E(z)
Input ADC
- - Vo(z) =
1+ (1-z-1) + (1-z-1)2
1-bit
1 bit
DAC (z= jT)
Y(t)
Output
Quantization Noise Response

From Linearized Model
HIGH-
③ Linearized model of N-th order interpolative modulator

E(z)
+ W(z)
X(z) + H(z) + z-1 Y(z)
-
1-bit ADC
1-bit DAC
Y(z) = Hx(z)X(z) + HE(z)E(z)
 Ai (z-1)N-i
N
i=0
HX(z) =
z[(z-1)N -  Bi(z-1)N-i ] +  Ai(z-1)N-i
N N
i=1 i=0
(z-1)N -  i=1 Bi (z-1)N-i

N
HE(z) =
z[(z-1)N -  i=1 Bi(z-1)N-i ] +  i=1Ai(z-1)N-i
N N
E(z) (j)N
YX(z)  X(z) +
AN
HIGH-
Fourth Order Loop

Quantization Noise Response
HIGH-
B. Calibrated SAR-type ADC
10b Capacitor Main DAC
MSB LSB
8 Bit Resistor sub DAC

Vref
Measure C mismatch error using Resistor sub DAC.  Digitize !

HIGH-
① Sample 0V ;
C1 C2
Vref
② Swapp Vref ; Vx
C1 C2
Vref
C2  C1
① Complexity
C1 = C2
t
② Need longg calibration cycle
y due to noise
C2  C1 ③ Slow 15bit 8kHz
12bit 80kHz
Digitize this error to compensate !
HIGH-
C. High-Resolution Algorithmic ADC

① Ratio Independent ;
t=0
Must be diff. !!
C2
- C1 - Sample & integrate
C1 Vo = 2 Vin Vin twice !
+ C2
Vin
- Swap C1 & C2 2Vin
C1
Vref - C1
Vo = 2Vin - Vref C2
C2 +
HIGH-
* Error sources
- Switch feedthrough error
- kT/C error
- Finite gain error
- Slow ; 10Bit ~ 12Bit 8kHz
② Reference Recycling ;
Let Vref go through the same error as Vin !
Vo = 2 (1+)Vin - (1+ )Vref
= (1+ )(2Vin
i - Vreff)
- No finite gain error

- Same as Ratio Independent
- Slow ; 12Bit 8kHz
HIGH-
D. Capacitor Error-Averaged ADC
- Equal capacitors are used for the X2 function (C1=C2, but mismatched).
C1
Sampling
Vin C2
C2
Amplifying
C1
Vref 2Vin - Vref + 

Error
HIGH-
Averaging C1
C2
Vref 2Vin - Vref - 

Error
- Capacitor errors , - are averaged using a separated amplifier to obtain

12bits at 1 MHz.
MHz ( possibly up to 14 bits at 3 MHz )
HIGH-
* Error-Averaging Amplifier
A lif i
Amplifying 2C
C
2Vin - Vref + 
C
2C
2C
Averaging
C 2Vin - Vref +  - 
2Vin - Vref - 
C = 2Vin - Vref
2C
- Total input voltage change is (2Vin - Vref -  ) - (2Vin - Vref +  ) = -2

HIGH-
■ Advantage : - Can be done in fewer clock cycles than the ratio-independent

or reference-recycling methods
- Can be used with a correlated double sampling technique
■ Disadvantage : - Extra amplifier for error averaging
- Too Complex
HIGH-
E. Digital-Domain Self-Calibration ADC
DIGITAL IDEAL IDEAL

DIGITAL
OUTPUT
OUTPUT
ANALOG ANALOG
INPUT INPUT
CODE
ERROR
COARSE
DIGITAL
OUTPUT
HIGH-
- Feedthrough Measurement
VO = VOS
2NC 2C C 2C
Vref
1 0 0
INPUT = Dj
2NC 2C C 2C
Vref
1 0 0
VO = VFT
INPUT = Dj
HIGH-
- Code-Error Measurement
VO = VOS
2NC 2C C 2C
Vref
1 0 0
INPUT = Dj
2NC 2C C 2C
Vref Vref
1 0 1
INPUT = Dj+1 ( = Dj+1 ) VO = -1/2 Vref + VFT + V(Dj+1)
HIGH-
- Digital Calibration and Correction
2 HOLD DIGITAL
(N+1)
CALIBRATION
BITS 2N BITS
1 (N+1)-BIT (N+1)-BIT LOGIC
MDAC FLASH DIGITAL
CORRECTION
LOGIC
(N+1) BITS
3
CORRECTION
2N-1 N+1 N N-1 1 0

COARSE BITS
FINE BITS
CALIBRATION CODE ERRORS
2N-BIT
2N BIT OUTPUT
HIGH-
Recycling
calibrated ADC
HIGH-
Differential
Capacitor-array MDAC
HIGH-
Before calibration After calibration

HIGH-
Beforecalibration
Before calibration Aftercalibration
After calibration
HIGH-
HIGH-SPEED ADC DESIGN EXAMPLE
A 12b 10MHz 250mW

DIGITALLY CALIBRATED STAND
STAND-ALONE
ALONE
CMOS A/D CONVERTER
[ISSCC 1996 Presented]

ELECTRONIC CAMERA FRONT
FRONT-
-END
BLOCK DIAGRAM
OF FRONT-END
DIGITAL VIDEO
DAC OUT1
CCD CDS AGC ADC CAMERA
SIGNAL VIDEO
PROCESSING DAC OUT1
CCD : Charge-Coupled Device

CDS : Correlated Double Sampling
AGC : Automatic Gain Control
ADC : Analog-to-Digital Converter
DAC : Digital-to-Analog Converter
DESIGN OF A/D CONVERTER
ADC BLOCK
DIGITAL DAC
CAMERA
AGC A/D CONVERTER
SIGNAL
PROCESSING DAC
* Design Issues :
- Speed, Resolution, Power Dissipation
- Chip Area
- Yield
- Cycle Time
- What Process (Bipolar, MOS)
- etc.
DESIGN EXAMPLE OF A/D CONVERTER
DESIGN
EXAMPLE
DIGITAL DAC
CAMERA
AGC A/D CONVERTER
SIGNAL
PROCESSING DAC
Example Target Specifications :
12-Bit,
12 Bit 10
10-MHz,
MHz 250mW
250mW, and more
0.8 um Full CMOS A/D Converter
(’96 ISSCC published)
A 12b 10MHz 250mW A/D CONVERTER
FLASH A/D CONVERTER SCHEMATIC
FLASH ADC
TOP SCHEMATIC
FLASH ADC TIMING
Q2 Q1 Q2 Q1
PREAMP SAMPLE REF AMPLIFY

PREAMP_LATCH PRECHARGE LATCH
F1_LATCH TRACK LATCH
ROM RESET ENCODING
Q1 Q1P
Q2 Q2P
AN EXAMPLE OF FLASH ADC SPEC
TECHNOLOGY 0.8 um DOUBLE-POLY DOUBLE-METAL CMOS
REFERENCE 2 Vp-p
RESOLUTION 4 BITS
ACCURACY 5 BITS ( 2/16 = 125 mV ) + SAFETY MARGIN
SPEED 100 ns / 2 / 2 = 25 ns ?
POWER, AREA 5V, << 0.5 mW, REQUIRED
ARCHITECTURE PREAMP + LATCH
TIMING Q1 AND Q2 (NONOVERLAPPED)
TOLERANCE
WITH TEMP, SUPPLY, SIMULATE AND CHECK
AND MODEL PARAMETER
COMP1N
PRE-
PRE-AMP
gm5
DC gain =
gm1-gm2
1
f-3dB =
2 RTCT
RT = 1/(g
1/( m1-gm2)
CT = Cdb1 + Cgs1 + Cdb2

+ Cgs33 + 2Cgd2
d2 + 2Cgd3
d3
+ Cgd5 + Cdb5
Power = Vsupply
l * Ibias
bi
COMP1P
F1_BIAS
F1_NAND
F1_LATCH
LATCH_1
F1_ROM
Comparator Operation Principle
제안된 비교기의 동작 원리
CML1
C1
 Q2 HIGH
- 기준 전압 샘플링
REFT
(REFT, REFC)
amp
a p latch
atc
REFC  Q1 HIGH
C2 - 입력 전압 샘플링
CML1 LATCH
C (INP INN)
(INP,
- 래치 입력단에 차이 전압 생성
(INP-INN)-(REFT-REFC)
C1
- 래치의 출력단 LN과 LP는 VDD로 충전
INP
amp latch  LATCH HIGH
INN - 래치의 정궤환 동작으로 래치 출력단에
C2 디지털 신호 출력
LATCH - 버퍼단을 통해 최종 디지털 신
신호 출력
PRE-
PRE-AMP OUTPUT (AC ANALYSIS)
WAVEFORM OF PRE-
PRE-AMP INPUT (1)
WAVEFORM OF PRE-
PRE-AMP INPUT (2)
WAVEFORM OF PRE-
PRE-AMP OUTPUT (1)
WAVEFORM OF PRE-
PRE-AMP OUTPUT (2)
WAVEFORM OF FLASH LATCH
WAVEFORM OF FLASH OUTPUT
FLOORPLANNING
ANALOG DIGITAL
FERENCE
E
W ARRAY
F _ LATCH
F _ NAND
REAMP
LATCH
ROM
PR
REF
S.W
■ LINE LOCATIONS AND WIDTHS

- POWER LINES
- CLOCK LINES
- INPUTS AND OUTPUTS
■ WHERE IS A BIAS BLOCK ?
LAYOUT PRINCIPLES
1 G
1. Good
d isolation
i l ti off analog
l and
d digital
di it l circuit
i it blocks
bl k
2. Isolation of analog and digital power supplies
3. Minimized line crossings of analog and digital signals
4. Use of n-well (or p-well) for low substrate noise coupling
5. Good analog and digital pad grouping
p y
6. Employment of separate
p current mirrors and bias circuits
7. Many well and subst contacts required
8. Fully differential layout techniques
9 Minimization of proximity problems
9.
10. Isolation of clock generators from other blocks
11. Consideration of mismatch effects
12. Use of metal2 rather than metal1 for power lines
13. Multiple pads for inputs
g yield
14. At least two vias and contacts for high y and reliability
y
15. Prevention of layers on well edges
16. Modular approach for easy verification of functional blocks
17 Don’t
17. Don t mix pmos and nmos transistors
18. More…..
FLASH LAYOUT
MORE WORK TO DO
 Check design target specifications in details
 Consideration
C id ti process variations
i ti for
f design
d i and
d layout
l t
- Safety margin, yield, application fields, etc.
- Fast, nominal, slow model parameters (+- 30%)
- Extra devices for minimum design and layout cost
- Multiple pads and test pins for isolated problems
 Add test circuits for worst-case conditions
 Set up performance evaluation kits in parallel with design
 More ... SHOULD BE FUNCTIONAL, FIRST !!!

High-Speed High-
High- High-Resolution
Low--Power Fine
Low Fine--Line CMOS ADCs
January
y 2011
SEUNG--HOON LEE
SEUNG
D t off El
Dept. Electronic
t i Engineering
E i i
SOGANG UNIVERSITY,, KOREA
System-
System-on
on-
-a-Chip(SoC) Applications
군사분야 가전/정보분야 통신/SDR분야
의료/영상분야
기계/MEMS 및 자동차분야
컴퓨터/멀티미디어분야
기타 미래의 첨단 정보기술산업의 많은 분야
반도체 IC 없이 가능한 일은 ?
System R&D with Digital Convergence
Mobiles
Communication MP3, Cellular phone,
MP3 phone
ATM, CDMA PDA, Notebook PC
High Speed Low Power

Consumer Multimedia Fusion
+
IC Card
Card, Lab Top PC
PC, C
Connectivity
ti it Products
Electronic Money +
Mobility “(SoC)”
Low Cost Reliability
Graphics
DTV,, Digital
g Camera,,
Networking
DVD, CMOS Image WLAN
Contents
 Recent Trend of ADC IP’s

-> High Speed and Low Power
-> High Resolution and Small Area
-> How to trade off various conflicts ?
 Case1 - A Calibration-Free 14b 70MS/s CMOS ADC
 Case2
C 2 - A 10b 25MS/s
25MS/ 4.8mW
4 8 W 0.13um
0 13 CMOS ADC
 Case3 - A Re-Configurable 10b, 10MS/s - 100MS/s,
0.5V - 1.2V, Low-Power, 0.13um CMOS ADC
 Case4 - A 10b 100MS/s 24.2mW CMOS ADC With
Various Circuit Sharing Techniques
 Case5 - A 12b 160MS/s 65nm CMOS ADC Based
on Multi-Stage Amplifier
Low-
Low-Power ADC (Circuit Sharing) [1]
VDD
Sampling C1 Amplifying C3
Bi+1*VREF
VRES(n-1) 1st stage 1st stage
C2 1 2nd
stage 2
VSS CC C4
VRES(n+1)
1 + 2
S1 ON
VIP+ VIP- (Phase 1) VIPC
s2 s2
VIPC VIPC VIP+ VIP-
s1 s1 VIN+ - VO+ VIN-
s2 - VO+ s2 - VO+
VINC VINC
s1 s1 S2 ON VINC
VIN VIN (Phase 2)
+ -
 The 2nd stage

g opamp
p p shared by
y opposite
pp phase
p stages
g
 The 1st stage opamps merged with a single bias branch
[1] S. T. Ryu, B. S. Song, and K. Bacrania, “AA 10-bit

10 bit 50
50-MS/s
MS/s Pipelined ADC with opamp current reuse,
reuse,”
IEEE J. Solid-State Circuits, vol. 42, pp. 475-485, March 2007.
[ Pow. (18mW), Area (1.43mm2), DNL/INL (0.2/0.4), SNDR (56.9dB) ]
Low-
Low-Power ADC (Capacitor Sharing) [2]
Cf
±Vref,
0
Cs = 4·Cf
Cs Vres2(N-1)
Vres1((N))
Vin(N) Vin(N) ±Vref, 0
To 3rd stage
Ccom1 Ccom1
3-bit
Latch1 Latch1 Latch1 Flash
Vth1
Ccom4 Ccom4
Latch4 Latch4 Latch4
Vth4
(a) Φ1 is high (b) ΦDis(ΦLat) is high (c) Φ2 is high
Φ1 Φ1
c
ΦDis
ΦLat
Φ2
 Capacitors
C it shared
h d by
b two
t successive
i pipeline
i li stages
t
 Additional reset phase required due to memory effect of shared capacitors
[[2]] B.G. Lee and R.M. Tsang,
g, “A 10-bit 50-MS/s p
pipelined
p ADC with capacitor-sharing
p g and variable-gm
g
opamp,” IEEE J. Solid-State Ckts, pp. 883-890, Mar. 2009.
[P. (12mW), Area (0.86mm2), DNL/INL (0.4/0.8), SNDR (58.4dB), 0.18um CMOS]
Low-
Low-Power ADC (Time Sharing) [3]
- Opamp
O
+ sharing
Vin+/-
i / MDAC1 MDAC2 MDAC3 4b
flash
4
2.5b driver 2.5b driver 2.5b driver
ADC ADC ADC
3 3 3
10
Digital correction Dout
MDAC1 T/2
evaluation
MDAC2 T/4
evaluation
MDAC3 T/4
evaluation MDAC2&3 share the half
period
 Single opamp shared 4-stage

4 stage pipeline ADC
 Half clock period shares the evaluation time of MDAC2 and MDAC3
[[3]] Y. C. Huangg and T. C. Lee, “A 10b 100MS/s 4.5mW pipelined
pp ADC with a time sharing
g technique,”
q in
ISSCC Dig. Tech. Papers, Feb. 2010, pp. 300-301.
[ P. (4.5mW), Area (0.058mm2), DNL/INL (0.8/1.0), SNDR (55.0dB), 90nm CMOS ]
Low-
Low-Power ADC (CBSC & ZCBC) [4]
* CBSC : Comparator-Based Switched-Capacitor

VO[n]
C1
C2 VX t
CL
VX IX VCM
VCM + VO - VX
VCM
VCM O t
Improved
* ZCBC : Zero Crossing Based Circuit
C1
C2
CL
VX ZCD IX
VCM + VO -
VCM
VCM
 Opamp
O replaced with a comparator(ZCD)
( C ) and a current source
 Comparator(ZCD) detects virtual ground condition and turns off current source
[4] L. Brooks and H. S. Lee, “A
A zero-crossing-based
zero crossing based 8b 200MS/s pipelined ADC,
ADC,” in ISSCC Dig. Tech.
Papers, Feb. 2007, pp. 460-461.
[ P. (8.5mW), Area (0.05mm2), DNL/INL (0.75/1.0), 0.18um CMOS ]
Low-
Low-Power ADC (Switched Bias Power Reduction) [5]
VDD VD
M4 M5 D
MP1 MP2 MP3 MP4 MP5 MP6
30%Ⅰ
reduced 2
M6 M7 BIAS1
IN IN OUT 70 : 30
BIAS2
Q1
M1 M2 + +
M8 M9 IREF
BIAS4
100%Ⅰ
reduced M10 M11 1
M3 MN1 MN2 MN3 MN4
VSS VSS
Amplifying
Current Reduction in Sampling Sequence Delay Cell
 Sampling - Currents reduced by 30% with BIAS1 & 2 and by 100% with BIAS4
 Holding - Currents resumed with switching sequence;
first BIAS4, then BIAS1 and BIAS2
- Timing delay needed by MP3 and MN3
[5] Y. J. Cho, et al., “A 10b 25MS/s 4.8mW 0.13um CMOS ADC for digital multimedia broadcasting
applications,” in Proc. CICC, Sept. 2006, pp. 497-500.
[ Pow. (4.8mW), Area (0.8mm2), DNL/INL (0.42/0.91), SNDR/SFDR (56dB/65dB) ]
Low-
Low-Power ADC (SHA
(SHA-
-FREE Architecture) [6]
CLK
60MHz 30MHz
Q1 CLK DFF Clock BGR Reference
Generator Generator
Q2
QS
QL Q2 AMP2 Q1
Vin 3b 3b 3b
MDAC1 MDAC2 MDAC3
3b 3b 3b 4b
Resisto
Shared
Ladderr
FLASH FLASH FLASH FLASH
ADC1 ADC2 ADC3 ADC4
d
(F1) (F2) (F3) (F4)
or
3b 3b 3b 4b
DIGITAL CORRECTION LOGIC (DCL) 10b
 SHA consumes a large portion of the ADC overall power consumption

 Similar RC time constant between MDAC1 and FLASH ADC1 required due to
sampling
li mismatch
i t h
 Additional clock phase required for the residue amplification of MDAC1
[[6]] Y. D. Jeon,, et al.,, “A 4.7mW 0.32mm2 10b 30MS/s p
pipelined
p ADC without a front-end S/H in 90nm
CMOS,” in ISSCC Dig. Tech. Papers, Feb. 2007, pp. 456-457.
[ P. (4.7mW), Area (0.32mm2), DNL/INL (0.5/0.8), SNDR/SFDR (58dB/75dB) ]
Low-
Low-Power ADC (SAR ADC) [7]
Vref
S1p S2p S3p S4p S5p S6p S7p S8p S9p
Bootstrapped
B t t d C1 C2 C3 C4 C5 C6 C7 C8 C9 C10
Switch
Vip + Digital 10 Digital

g
Vin - Controller Output
C1 C2 C3 C4 C5 C6 C7 C8 C9 C10
Clk_in
S1n S2n S3n S4n S5n S6n S7n S8n S9n Ci=2Ci+1, i=1~8, C9=C10
Vref
 SAR ADC power consuming sources :

- Digital control circuit, Comparator, DAC capacitor array
 Set-and-down switching method reduces the average switching energy
[7] C. C. Liu, et al., “A 0.92mW 10-bit 50-MS/s SAR ADC in 0.13um CMOS Process,” in Symp. VLSI Circuits
Dig. Tech. Papers, June 2009, pp. 236-237.
[ P. (0.92mW), Area (0.075mm2), DNL/INL (1.0/2.2), SNDR/SFDR (52.8dB/67.7dB) ]
Low-
Low-Power ADC (Pipelined
(Pipelined-
-SAR ADC) [8]
Stage 1: 6b MDAC
+ Stage 2:
Vin ∑ 16 7b SAR
ADC
-
6b SAR 6b
ADC DAC
7 Dout,2
±Vref
6 Dout,1
12
Digital Error Correction Block Dout,final
 SAR ADCs used in the 1st and 2nd pipeline stages instead of flash ADCs
 Reduced capacitors compared with a conventional 12b SAR ADC
 Enhanced
E h d sampling
li rate
t andd resolution
l ti b pipeline
by i li architecture
hit t
 Reduced op-amp power and increased loop-gain by a half-gain MDAC
[8] C. C. Lee and M. P. Flynn, “A
A 12b 50MS/s 3.5mW SAR assisted 2-stage
2 stage pipeline ADC,
ADC,” in Symp. VLSI
Circuits Dig. Tech. Papers, June 2010, pp. 239-240.
[ Pow. (3.5mW), Area (0.16mm2), DNL/INL (0.75/1.5), SNDR/SFDR (65.5dB/78.0dB), 65nm CMOS ]
Small-
Small-Area ADC (Circuit Sharing) [9]
Q2 AMP1 Q1 Q2 AMP2 Q1
3-Bit 3-Bit 3-Bit

Vin SHA
MDAC1 MDAC2 MDAC3
3-Bit 3-Bit 3-Bit 4-Bit
REGISTER
REGISTER
SHARED
SHARED
LADDER
LADDER
FLASH FLASH FLASH FLASH
ADC ADC ADC ADC
((F1)) ((F2)) ((F3)) ((F4))
R
R
3bits 3bits 3bits 4bits
Q1
Q2 Digital Correction Logic 10bits
 SHA shares AMP1 with the 1st stage MDAC1

 The 2nd stage
g MDAC2 shares AMP2 with the 3rd stage
g MDAC3
 Flash ADCs share the resistor ladder work on opposite clock phase
[9] Y. D. Jeon, et al., “A 5mW 0.26mm2 10bit 20MS/s pipelined CMOS ADC with multi-stage amplifier
sharing technique,” in Proc. ESSCIRC, Sept. 2006, pp. 544-547.
[ Pow. (5mW), Area (0.26mm2), DNL/INL (0.8/1.7), SNDR/SFDR (56dB/69dB) ]
Small-
Small-Area ADC (Cyclic Architecture) [10]
AIN F
From T&H
Analog 2.5-bit 2.5-bit
MUX MDAC1 MDAC2
S&H MX2
+

Reference -
Generator
2.5-bit
2 5 bit 2.5-bit
2 5 bit
FLASH FLASH 1.5b 1.5b
MUX ADC1 ADC2 ADC DAC
STC
Control 2.5 bit 2.5 bit
Clock Digital EOC 1b

CKIN To Digital Error
Generator Correction Logic DOUT ADC
16 bit Correction
 The minimum function blocks recycled to acquire pipeline

performance with small size and low
low-power
power consumption
[10] H. C. Choi, et al., “A calibration-free 3V 16b 500kS/s 6mW 0.5mm2 ADC with 0.13um CMOS,” in Symp.
VLSI Ci
Circuits
it Dig.
Di T Tech.
h PPapers, June
J 2004
2004, pp. 76
76-77.
77
High Resolution ADC (3D Fully Symmetric Layout) [11]
MET4
VIA3
MET3
VIA2
MET2
VIA1
MET1
: MIM Capacitor
C Top Plate
: Stacked metals of M1, 2, 4
: Stacked metals of M1, 3, 4
: Stacked metals from M1 to M4
 Only MDAC capacitors isolated

 High-matching capacitors insensitive to neighboring signals
[11] Y. J. Cho, et al., “A calibration-free 14b 70MS/s 3.3mm2 235mW 0.13um CMOS pipeline ADC with high-
matching 3-D symmetric capacitors,” in Proc. CICC, Sept. 2006, pp. 485-488.
[ Pow. (235mW), Area (3.3mm2), DNL/INL (0.65/1.8), SNDR/SFDR (65.7dB/80.6dB) ]
High Resolution ADC (Digital Calibration) [12]
((1)) Background
g Calibration
Vi ra Back-end ADC
1/8
ADC DAC
raes Do = ((Vi+Q
QN+(1/8)P
( ) N))raes
DO -(QN+(1/8)PN)ra+ON
PN
e = (1/8)(ra
(1/8)( es-ra))
Digital Domain e ra = raes-8e
 Binary pseudorandom noise sequence injected at the input of the sub-ADC

 ADC digital output correlated with the same pseudorandom sequence
to get the radix error
 Background calibration technique can continuously monitor the transfer
f
characteristics and correct the digital output codes accordingly
[12] J. Li, et al., “A 0.9V 12-mW 5-MSPS algorithmic ADC with 77-dB SFDR,” IEEE J. Solid-State Circuits,
vol. 40, No. 4, pp. 960-969, April 2005.
High Resolution ADC (Digital Calibration) [13]
((2)) Foreground
g Calibration
Acc & Avg
VGND
T/H Sub-ADCi Z-1 N 1/N bi
g
*Offset error foreground calibration ctl
Correction
T/H Sub-ADCi I.I Acc &Avg

Vref_cal
LMS
bi
Gain error foreground calibration
*Gain ei IViI
ai Z-1 u
IVOI
 Foreground (power-up) calibration performed to estimate initial values

for the gain/offset by configuring the circuit
[[13]] C. C. Hsu,, et al.,, “An 11b 800MS/s time-interleaved ADC with digital
g background
g calibration,”
, in ISSCC
Dig. Tech. Papers, Feb. 2007, pp. 464-465.
[ Pow. (350mW), Area (1.4mm2), DNL/INL (0.5/1.6), SNDR (58dB) ]
High Resolution ADC (Analog Calibration) [14]
Calibration Engine with

Permutation Generator and Spread Detector
S/H St
Stage 1 St
Stage 2 St
Stage 3 B k E d ADC
Back-End
3 3 3 7
Digital
Digital Error Correction Logic
Output
p
C4
Permutation
Address C3
2 x 32 C2
C1
ADC Decoder Select best matched

array by permutation
3b
 Each Unit DAC capacitor break into smaller element

 DAC capacitors reconstructed by grouping for the cancellation of error
[14] S. Rayy and B. S. Song,
g “A 13b linear 40MS/s pipelined ADC with self-configured
g capacitor matching,”
g
in ISSCC Dig. Tech. Papers, Feb. 2006, pp.228-229.
High-
High-Speed ADC (Full Flash ADC) [15]
Ref Ladder
Ref. Preamp Comparator NAND ROM Latch
Digitall Output
coder
Enc
Vin_plus Vin_min clk
Analog Input
 High speed, simplicity, and parallelism
 The number of comparators increases exponentially with the resolution
 Resolution limited less than or equal to 6 bits
[15] K. Uyttenhove and M. S. J. Steyaert, “A 1.8-V 6-bit 1.3-GHz flash ADC in 0.25-um CMOS,” IEEE
J. Solid-State Circuits, vol. 38, no. 7, pp. 1115-1122, July 2003.
High-
High-Speed ADC (Multi Channel) [16]
f s/ 2 fs
Channel 1
Flash Digital
1ststage 2ndstage 3rdstage
S/H ADC
(3bit) (3bit) (3bit) (3bit) Logic
T1~ D1~D10
ver
T10
Output Driv
Vin
MUX
Channel 2
O
DB1~DB10
Flash Digital
1ststage 2ndstage 3rdstage
S/H ADC
(3bit) (3bit) (3bit) (3bit) Logic
 Operating speed enhanced with acceptable power consumption

 Channel mismatch of parallel ADCs demands complex and bulky calibration
circuits for high resolution
[16] S. C. Lee, et al., “A 10-bit 400-MS/s 160-mW 0.13-um CMOS dual-channel pipeline ADC without channel
mismatch calibration,” IEEE J. Solid-State Circuits, vol. 41. no. 7, pp. 1596-1605, July, 2006.
High-
High-Speed ADC (Multi Channel & SAR ADC) [17]
Ref. tnov
1X ADC Dr
Φ 1 2
Φr(599.4KHz)
1002
Φ1 1
ADC1 ADF1
D1
Vin Φ2
T/H 1X 2
Φ1(60MHz) 1002
Φ
(600MH )
(600MHz) Φ10
Φ1
ADC10 ADF10
Φ’ D10
DLL Φr 1
(60MHz)
Φ10 Φ10((60MHz)) Software 1002
 Time-interleaved SAR ADC achieve high speed operation

 Channel
Ch l mismatch
i t h off parallel
ll l ADCs
ADC demands
d d a low-speed
l d high-resolution
hi h l ti
ADC for calibration
[17] W. Liu, et al., “A
A 600MS/s 30mW 0.13um CMOS ADC array achieving over 60dB SFDR with adaptive
digital equalization,” in ISSCC Dig., Feb. 2009, pp.82-83.
[ P. (30mW), Area (1.1mm2), DNL/INL (0.3/1.7), SNDR (46.7dB) ]
High-
High-Speed ADC (Asynchronous ADC) [18]
Vin
>
Comp > Comp (3∥7/8)
(6/8)
< <
OR
Comp >
(4/8)
< Comp > >
Comp (1∥5/8)
(2/8)
< <
Vclk
OR
if Vin > 4 → 5 & 7 Switching

if Vin > 4 → 1 & 3 Network
4
Reference
voltages
 Clock signal applied only the first comparator
 Output signal of current comparator triggers the next comparator
[18] Y. Z.
Y Z Lin,
Li ett al.,
l “A 5b 800MS/
800MS/s 2
2mW
W asynchronous
h bi
binary-searchh ADC iin 65
65nm CMOS
CMOS,”” in
i ISSCC Di
Dig.
Tech. Papers, Feb. 2009, pp.80-81.
[ P. (2mW), Area (0.018mm2), DNL/INL (0.56/0.61), SNDR (29dB) ]
CURRENT STATUS OF ADC R&D
JSSC
[’00]
20 ISSCC
[’03] [’05][’08][’03] [’05] [’11] [’09] [’10] [’10] CICC
16
[[’04]
04][[’10]
10] [[’06]
06][[’04]
04][[’07]
07] [[’07]
07]
VLSI Symp.
AP-ASIC
[’06] [’04][’03] [’04] [’07][’01][’06] [’06] [’06][’10][’06][’08][’06][’06] [’07] APCCAS
14
[’01][’07] SGU IC Lab.
LUTION [[bit]
[’04] [’03] [’08][’10] [’08]

[’04] [’00] [’00]
[[’07]
07] [[’09]
09][’10]
[’06] [’06] [’96][’10] [’10][’08] [’01] [’03] [’04] [’06] [’05][’09] [’11] [’11]
12
[’03] [’00] [’96][’08][’07][’09][’04][’09] [’07] [’10] [’08] [’07][’06]
[’08]
[’10]
[’08] [’08] [’06][’07] [’06] [’09] [’07][’09][’08] [’07][’09] [’02] [’04] [’07] [’07][’04] [’10] [’06] [’09] [’07][’10] [’11]
10
RESOL
[’05] [’03] [’10] [’07] [’10] [’09][’07] [’07] [’07] [’10] [’10] [’05] [’03] [’07] [’08][’06] [’09]
[’09] [’11] [’09]
[’08] [’10]
[’07] [’07] [’01] [’00] [’04] [’04][’01] [’02] [’05] [’11][’07] [’08] [’10][’04] [’02]
8
[[’10]
10] [[’07]
07] [[’00]
00] [[’05]
05] [ 03] [[’04]
[’03] 04] [[’04]
04]
[’03] [’02] [’07] [’10]
[’03] [’09] [’08] [’02] [’02] [’01][’10][’06][’09][’10][’03] [’10] [’10][’08][’10]

6
[’04] [’06][’10][’08][’02][’10][’09] [’10]
[’08] [’08] [’06] [’07]
[’09] [’03][’03] [’08] [’06][’07]

4
0.25 1 50 100 150 200 500 1000 2000 10000

SPEED [MSample/s]
Successive Approximation
Register (SAR) ADCs
January
y 2011
SEUNG--HOON LEE
SEUNG
D t off El
Dept. Electronic
t i Engineering
E i i
Contents
 High
High--Speed SAR ADCs
 Speed and Resolution Improvement
 Performance Comparison of
Low--Speed SAR and Algorithmic ADCs
Low
 Recently Reported SAR ADCs

High-
High-Speed SAR ADCs (1/3)
■ 9b 100MS/s SAR ADC [19]

▪ Resolution : 9b, Sampling rate : 100MS/s
▪ Power consumption
p : 1.46mW,, Area : 0.12mm2, Process : 65nm CMOS
C-DAC Comparator
- 5b-4b 2-stage architecture - Only dynamic latch

- Off-chip C-DAC calibration (w/o pre-amplifier)
- CU=11.25fF - No comparator offset
- CIN=180fF calibration
SAR Logic Chip Photograph
- DAC : 0.0082mm2
- Asynchronous control
- - Power : 1.2mW
- SAR Logic : 0.0024mm2
- Comparator : 0.0003mm2
[19] Y. Chen, S. Tsukamoto, and T. Kuroda, “A 9b 100MS/s 1.46mW SAR ADC in 65nm CMOS,” in Proc.
ASSCC, Nov. 2009, pp. 145-148.
High-
■ 10b 50MS/s SAR ADC [20]

p : 0.83mW,, Area : 0.052mm2, Process : 0.13um CMOS
C-DAC Comparator
- Binary-weighted C-array - Only dynamic latch

- Reducing input cap. (w/o pre-amplifier)
- CU=4.8fF - No comparator offset
- CIN=2457.6fF calibration
- DAC : 0.0359mm2
- Asynchronous control
- SAR Logic : 0.0116mm2
- Power : 0.42mW
- Comparator : 0.0012mm2
[20] C. C. Liu, et al., “A 10-bit 50-MSs SAR ADC with a monotonic capacitor switching procedure,” IEEE J.
Solid-State Circuits, vol. 45, no. 4, pp. 731-740, Apr. 2010.
High-
■ 10b 100MS/s SAR ADC [21]

p : 3.0mW,, Area : 0.18mm2, Process : 90nm CMOS
C-DAC Comparator
- 5b-5b 2-stage
- Reducing input cap. - Preamp gain = 22.4
- CU=50fF (27dB)
- CIN=800fF
- Self-timing method - DAC : 0.0247mm2

- Custom logic - SAR Logic & Comparator
- Power : 1.7mW : 0.0101mm2
[21] Y. Zhu, et al., “A 10-bit 100-MSs reference-free SAR ADC in 90nm CMOS,” IEEE J. Solid-State Circuits,
vol. 45, no. 6, pp. 1111-1121, June 2010.
Speed and Resolution Improvement for SAR ADCs
■ Conventional SAR ADCs :

▪ Limited resolution due to exponentially increased capacitors
▪ Increased clock cycles depending on resolution
▪ Process-dominated operating speed and chip area
■ Recently reported SAR ADCs to improve speed and resolution :
▪ Pipelined SAR ADC
▪ Sub-ranged SAR ADC
▪ Time-interleaved SAR ADC

Pipelined SAR ADC
■ 12b 50MS/s pipelined SAR ADC [[22]]

Stage 1: 6b MDAC
+ Stage 2:
Vin ∑ 16 7b SAR
ADC
-
6b SAR 6b
ADC DAC
7 Dout,2
±Vref
6 Dout,1
12
Digital Error Correction Block Dout,final
▪ SAR ADCs used in the 1st and 2nd pipeline stages instead of flash ADCs
▪ Reduced capacitors compared with a conventional 12b SAR ADC
▪ Enhanced
E h d sampling
li rate
t andd resolution
l ti byb pipeline
i li architecture
hit t
▪ Reduced op-amp power and increased loop-gain by a half-gain MDAC
[22] C. C. Lee and M. P. Flynn, “A 12b 50MSps 3.5mW SAR assisted 2-stage pipeline ADC,” in Symp. VLSI
Subranged SAR ADC
■ 9b 150MS/s subranged SAR ADC [[23]]
CCi = CC(i+1) = CF5 and 2CFj = CF(j+1) where j=1~14 and j=1~5
Vrefn
Vrefp
Vinp
CC1p CC2p CC14p CF1p CF2p CF3p CF4p CF5p
Vrefp 14 5
Cinp
4 6
3.5b Flash ADC DEC SAR Comp.
Cinn 14 9 5
Vrefn Vclkp Vclkr
CC1n CC2n CC14n CF1n CF2n CF3n CF4n CF5n
Vinn
Vclks
Vrefp
Vrefn
▪ Flash ADC for thermometer MSBs and SAR ADC for binary LSBs
▪ Improved speed and resolution without power
power-hungry
hungry amplifiers
▪ Additional capacitors needed for coarse A/D conversion
[23] Y. Z. Lin, et al., “A 9-bit 150-MSps 1.53-mW subranged SAR ADC in 90-nm CMOS,” in Symp. VLSI
Time-
Time-Interleaved SAR ADC
■ 6b 1
1.25GS/s
25GS/s time-interleaved SAR ADC [[24]]
ADC1
ADC2 2nC 2C C
Vin(t) Xout(n) Control
Logic
Vin
Vref
ADCM
▪ Parallel connected SAR ADCs to increase operating speed with low power
▪ Calibration,
C lib ti error correction,
ti and
d postt processing
i needed
d d for
f high
hi h resolution
l ti
[24] Z. Cao, S. Yan, and Y. Li, “A 32mW 1.25GS/s 6b 2b/Step SAR ADC in 0.13um CMOS,” IEEE J. Solid-
State Circuits, vol. 44, no. 3, pp. 862-873, Mar. 2009.
Performance Comparison of Low
Low-
-Speed SAR and Algorithmic ADCs
■ Resolution > 10b,

10b Sampling rate < 1MHz
Resolution Speed Supply Power Area Process
Year Architecture
(bit) (kHz) (V) (uW) (㎟) (CMOS)
[25] Pavia Univ. 10 100 1.0 3.8 0.700 0.18um ISSCC’08

ISSCC 08 SAR
[26] National Taiwan Univ. 10 500 1.0 4.2 0.240 0.18um ASSCC’09 SAR
[27] Samsung 10 500 1.5 1000 1.260 0.25um ISCAS’00 SAR
[28] Univ. of Twente 10 1000 1.3 1.9 - 65nm ISSCC’08 SAR
[29] Tokyo Institute of Tech. 10 1000 1.8 110 0.050 0.18um ASSCC’07 SAR
[30] STMicroelectronics 10 1000 2.4 2700 0.400 0.35um ESSCIRC’04 SAR
[31] Helsinki Univ. 12 40 1.8 68 0.041 0.13um ISCAS’07 Algorithmic
[32] Helsinki Univ. 12 42 1.8 32 0.055 0.13um VLSI’06 Algorithmic
[33] National Semiconductor 12 100 1.0 25 0.630 0.18um JSSC’07 SAR
[34] Sogang Univ. 12 200 1.8 936 0.468 0.18um IEICE’07 Algorithmic
[35] Texas Instruments 12 200 3.3 6600 2.000 0.13um ISCAS’06 SAR
[36] Sogang Univ 12 1000 1.8 2016 0.558 0.18um - Algorithmic
[37] Austria Mikro System 12 1000 5.0 15000 1.500 0.6um JSSCC’01 SAR
[38] Sogang
S Univ.
U i 14 8 25
2.5 16 0 783
0.783 0 35
0.35um AICSP’10 Al
Algorithmic
ith i
[39] Samsung 16 500 3.0 6000 0.500 0.13um VLSI’04 Algorithmic

References
[25] A. Agnes, et al., “A 9.4-ENOB 1V 3.8μW 100kS/s SAR ADC with time-domain comparator,” in ISSCC Dig. Tech. Papers, Feb. 2008, pp. 246-248.
[26] W. Y. Pang, et al., “A 10-bit 500-KS/s low power SAR ADC with splitting comparator for bio-medical applications,” in Proc. ASSCC, Nov. 2009,
pp. 149-152.
[27] J
J. P
Park,
k ett al.,
l “A 1 mW
W 10
10-bit
bit 500KSPS SAR A/D converter,”
t ” IEEE IInternational
t ti l Symposium
S i on Circuits
Ci it and
d Systems,
S t M 2000,
May 2000 pp. 581
581-584.
584
[28] M. V. Elzakker, et al., “A 1.9μW 4.4fJ/conversion-step 10b 1MS/s charge-redistribution ADC,” in ISSCC Dig. Tech. Papers, Feb. 2008, pp. 244-246.
[29] Y. Kuramochi, et al., “A 0.05-mm2 110-μW 10-b self-calibrating successive approximation ADC core in 0.18-μm CMOS,” in Proc. ASSCC,
Nov. 2007, pp. 224-227.
[30] P. Confalonieri, et al., “A 2.7mW 1MSps 10b analog-to-digital converter with built-in reference buffer and 1LSB accuracy programmable input ranges,”
in Proc. ESSCIRC, Feb. 2004, pp. 255-258.
[31] J. A. M. Jarvinen, et al., “A 12-bit ratio-independent algorithmic ADC for a capacitive sensor interface,” IEEE International Symposium on Circuits and
Systems, May 2007, pp. 1713-1716.
[32] J. A. M. Jarvinen, et al., “A 12-bit 32-μW ratio-independent algorithmic ADC,” in Symp. VLSI Circuits Dig. Tech. Papers, June 2006.
[33] N.
N Verma,
V ett al.,
l “An
“A ultra
lt low
l energy 12-bit
12 bit rate-resolution
t l ti scalable
l bl SAR ADC for
f wireless
i l sensor nodes,”
d ” IEEE J.
J Solid-State it vol.
S lid St t Circuits,
Ci l 42,
42 no. 6
6,
pp. 1196-1205, June 2007.
[34] Y. J. Kim, et al., “A 12b 200kS/s 0.52mA 0.47mm2 algorithmic A/D converter for MEMS applications,” IEICE Trans. on Electronics, vol. E91-C, no. 2,
pp. 206-212, Feb. 2008.
[[35]] A. Shrivastava,, et al.,, “12-bit non-calibrating
g noise-immune redundant SAR ADC for system-on-a-chip,”
y p, IEEE J. Solid-State Circuits,, vol. 42,, no. 6,,
pp. 1515-1518, June 2006.
[36] http://eeic7.sogang.ac.kr/[44]ADC12b1M18_pulsus.htm
[37] G. Promizer, et al., “12-bit low-power fully differential switched capacitor noncalibrating successive approximation ADC with 1 MSs,” IEEE J. Solid-
State Circuits, vol. 36, no. 7, pp. 1138-1143, July 2001.
[38] Y. J. Kim, et al., “A 12b 8kS/s 16uW 0.35um CMOS algorithmic ADC for sensor interface in ubiquitous environments,” Analog Integrated Circuits and
Signal Processing, vol. 62, no. 2, pp. 205-213, Feb. 2010.
[39] H. C. Choi, et al., “A calibration-free 3V 16b 500kS/s 6mW 0.5mm2 ADC with 0.13um CMOS,” in Symp. VLSI Circuits Dig. Tech. Papers, June 2006,
pp. 76-77.
Recently Reported SAR ADCs (1/2)
■ Architecture
A hit t
▪ Mostly based on conventional SAR operation
▪ Pipelined SAR ADCs to reduce total capacitance and pre-amplifier gain
: [48], [54], [58]
▪ Sub-ranged SAR ADCs to increase operating speed without amplifiers
: [43]
[43], [55]
▪ Asynchronous clock to improve operating speed with low power
: [40]-[42], [49], [50]
■ Capacitor
Capacitor-DAC
DAC
▪ Binary-weighted capacitor array
▪ Two-step architecture : [42] , [53], [55]
▪ Three-step
Th t architecture
hit t with
ith calibration
lib ti : [51]
▪ Removed MSB capacitor : [43], [45], [46], [49], [50], [52], [53]
Recently Reported SAR ADCs (2/2)
■ SAR L Logic
i
▪ Conventional logic with D-F/F
▪ Custom logic instead of D-F/F : [53]
▪ Self-timing scheme to improve operating speed : [53]
▪ Asynchronous or internal clock timing without external high-speed clock
: [40]
[40]-[42],
[42] [49]
[49]-[53]
[53]
■ Comparator
▪ Mostly based on a comparator without pre-amplifiers
: [40], [41], [51] (with offset calibration),
[42], [45], [49], [50], [52] (without offset calibration)
▪ Pre-amplifiers (<30dB gain) used in a comparator
: [46], [53], [57], [58] (single-stage pre-amplifier),
[55] (three-stage pre-amplifier)
Performance Comparison of Recently Reported SAR ADCs
■ Resolution : 9
9~12b,
12b, Sampling Rate : 6~150MHz
6 150MHz
Resol. Speed Supply Input Power Area Ctotal Cunit DNL/INL Process
Year Architecture & techniques
(bit) (MHz) (V) (Vpp) (㎽) (㎟) (pF) (fF) (LSB) (CMOS)
0.70 Time-interleaved S/H, Offset calibration,
[40] IMEC 9 40 1.0 0.8 0.82 0.090 - - 90nm ISSCC’08
/0.65 Asynchronous
0.60 S/H, Offset calibration, Asynchronous,
[41] IMEC 9 50 1.0 - 0.70 0.080 2.048 64 90nm ISSCC’07
/0.60 Modified capacitor array
0.30 2-step binairy-weighted C-array, Asynchronous,
[42] Keio Univ. 9 100 1.2 - 1.46 0.012 0.18 11.25 65nm ASSCC’09
/0.40 Tri-level based switching technique, C calibration
[43] National 0.48
9 150 1.2 2.0 1.53 0.028 - 2.2 90nm VLSI’10 S/H, Subranged SAR ADC (3.5b-6b)
Cheng-Kung Univ. /0.48
0.60
[44] Pavia Univ. 10 6 1.2 1.0 3.20 0.750 51.20 50 0.13um ESSCIRC’06
ESSCIRC 06 On-chip
On chip reference voltage buffer
/0.55
[45] National 0.34 Reducing input cap., Set-and-down capacitor
10 10 1.0 - 0.10 0.086 2.5 5 0.18um VLSI’10
Cheng-Kung Univ. /0.38 switching, Using coarse comparator
[46] National 1.27 Low input capacitance
10 12 1.2 - 0.32 0.070 10.24 20 0.13um ASSCC’09
Cheng-Kung Univ. /2.97 (Additional input cap. : 1.2pF)
2-step binary-weighted C-array,
[476] Infineon 10 20 1.2 - 12.00 0.080 0.8 1.5 -/- 0.13um ISSCC’02
Non-binary
Non binary successive approximation
[48] Toshiba 10 40 1.1 1.0 1.21 0.060 4.8 100 -/- 65nm ISSCC’10 Pipelined SAR ADC (4b SAR-6b SAR)
[49] National 0.91 Reducing input cap., Asynchronous,
10 50 1.2 2.0 0.83 0.052 2.458 4.8 0.13um JSSC’10
Cheng-Kung Univ. /1.36 Set-and-down capacitor switching
[50] National 1.00 Reducing input cap., Asynchronous,
10 50 1.2 - 0.92 0.075 5.12 10 0.13um VLSI’09
Cheng-Kung Univ. /2.20 Set-and-down capacitor switching
0 82
0.82 Split C-DAC,
C-DAC Offset calibration,
calibration C-DAC linearity
[51] Fujitsu 10 50 1.0 1.2 0.82 0.052 0.53 - 65nm ISSCC’10
/0.72 error calibration, Internal clock generator
[52] National 0.58 Reducing input cap., Set-and-down capacitor
10 100 1.2 - 1.13 0.026 1.86 3.2 65nm ISSCC’10
Cheng-Kung Univ. /0.69 switching, Binary-sclaed error compensation
0.79 Reducing input cap., Commom-mode based
[53] Shanghai Univ. 10 100 1.2 1.2 3.00 0.180 2.75 50 90nm JSSC’10
/0.86 charged recovery switching, Self timing
0.94 Pipelined SAR ADC (2.5b pipelined stage followed
[54] STMicronics 11 100 12
1.2 10
1.0 15 00
15.00 0 300
0.300 - - 65nm CICC’08
CICC 08
/1.50 by 9b parallel 12 SAR ADC)
[55] National 1.20
12 10 - - 3.00 0.096 3.2 25 0.13um ASSCC’09 Subranged SAR ADC
Taiwan Univ. /4.50
0.80
[56] Univ. of Michigan 12 11 1.0 - 3.57 0.700 - - 0.13um VLSI’09 Two comparator architecture
/3.00
[57] Univ. of Illinois
12 45 1.2 2.4 3.02 0.059 - - -/- - ISSCC’10 Perturbation-based calibration
at Urbana-Champaign
0.75
[58] Univ. of Michigan 12 50 1.3 2.0 3.50 0.160 - 15.63 65nm VLSI’10 Pipelined SAR ADC (6b SAR-7b SAR)
/1.50
Brief Review of Recently Reported SAR ADCs (1/5)
SAR ADC ADC architecture DAC Comparator SAR Logic
[40] 9b 40MHz - Binary-weighted capacitor array - Asynchronous control logic
- Comparator
p without p
pre-amp
p
- Offset calibration
by controlling output C
[41] 9b 50MHz - Asynchronous control logic
- Comparator without pre-amp

by controlling output C
- Asynchronous control logic

[42] 9b 100MHz - MSB- and LSB-side capacitor
calibration (off-chip)
- 4b-5b 2-stage architecture - Comparator without pre-amp

[43] 9b 150MHz - Binary-weighted capacitor array -
- 12 clock cycles for 10-bit A/D

[44] 10b 6MHz - Binary-weighted capacitor array - conversion
(sampling : 2 clock cycles)
- Comparator
C t without
ith t pre-amp
- Binary-weighted capacitor array
- Reducing input capacitance
- 12 clock
l k cycles
l for
f 10b A/D
[46] 10b 12MHz conversion
(sampling : 2 clock cycles)
- Additional capacitors
- Reducing input capacitance - Pre-amp to reduce kickback noise
[47] 10b 20MHz - -
- 8b-2b 2-stage architecture

(8b : unary, 2b : binary weighted)
- 1st stage : 4b binary-weighted

capacitor array (CU=100fF)
[48] 10b 40MHz - 2nd stage : 6b non binary-
- -
weighted capacitor array (CU=60fF)
[49] 10b 50MHz
- Asynchronous control logic

- Binary-weighted capacitor array - 12 clock cycles for 10b
- Reducing input capacitance (sampling : 2 clock cycles)
- Binary-weighted capacitor array - Comparator without pre-amp

- Internal clock generator

[51] 10b 50MHz - Internal clock calibration
- Spilt capacitor array
- Additional calibration capacitor
array

- Additional 3 compensation cap. - Comparator without pre-amp
[53] 10b 100MHz
- 5b-5b
5b 5b 2-stage
2 t architecture
hit t
- Reducing input capacitance - Pre-amp gain = 22.39 (27dB)
- Self timing method
[54] 11b 100MHz - - -
[55] 12b 10MHz -
- 7b-5b 2-stage architecture

- Coarse conversion = 1-stage
- 30C dummy capacitor for a 2C
- Fine
Fi conversion
i = 3-stage
3 t
attenuation capacitor
[56] 12b 11MHz - - - -
[57] 12b 45MHz -
- Sub-radix DAC
- Additional cap. for calibration - Pre-amp gain = 31.62 (30dB)
[58] 12b 50MHz -
- Pre-amp gain = 2 (6dB)

=>7b SAR ADC (Stage 2)
References
[40] V. Giannini, et al., “An 820μW 9b 40MS/s noise-tolerant dynamic-SAR ADC in 90nm digital CMOS,” in ISSCC Dig. Tech. Papers, Feb. 2008, pp. 238-239.
[41] J. Craninckx and G. Van der Plas, “A 65fJ/Conversion-step 0-to-50MSs 0-to-0.7mW 9b charge-sharing SAR ADC in 90nm digital CMOS,” in ISSCC Dig.
Tech. Papers, Feb. 2007, pp. 246-247.
[[42]] Y. Chen, S. Tsukamoto, and T. Kuroda, “A 9b 100MSs 1.46mW SAR ADC in 65nm CMOS," in Proc. ASSCC, Nov. 2009, pp. 145-148.
[43] Y. Z. Lin, et al., “A 9-bit 150-MSps 1.53-mW subranged SAR ADC in 90-nm CMOS,” in Symp. VLSI Circuits Dig. Tech. Papers, June 2010, pp.243-244.
[44] G. Borghetti, et al., “A programmable 10b up-to-6MSs SAR-ADC featuring constant-FoM with on-chip reference voltage buffers,” in Proc. ESSCIRC,
Sept. 2006, pp. 500-503.
[45] C. C. Liu, et al., “A 1V 11fJp/Conversion-step 10bit 10MSps asynchronous SAR ADC in 0.18μm CMOS,” in Symp. VLSI Circuits Dig. Tech. Papers,
June 2010, pp.241-242.
[46] G. Y. Huang, C. C. Liu, Y. Z. Liu, and S. J. Chang, “A 10-bit 12-MS/s successive approximation ADC with 1.2-pF input capacitance,” in Proc. ASSCC,
Nov. 2009, pp. 157-160.
[47] F. Kuttner, “A 1.2V 10b 20MSample/s non-binary successive approximation ADC in 0.13μm CMOS,” in ISSCC Dig. Tech. Papers, Feb. 2002, pp. 176-177.
[48] M. Furuta, M. Nzawa, and T. Itakura, “A 0.06mm2 8.9b ENOB 40MS/s pipelined SAR ADC in 65nm CMOS,” in ISSCC Dig. Tech. Papers, Feb. 2010,
pp. 382-383.
[49] CC. C
C. Li
Liu, ett al.,
l “A 10
10-bit
bit 50-MSs
50 MS SAR ADC withith a monotonic
t i capacitor
it switching
it hi procedure,”
d ” IEEE J.
J Solid-State it vol.
S lid St t Circuits,
Ci l 45,
45 no. 4
4, pp. 731
731-740,
740
Apr. 2010.
[50] C. C. Liu, S. J. Chang, G. Y. Huang, and Y. Z. Lin, “A 0.92mW 10-bit 50-MS/s SAR ADC in 0.13μm CMOS process,” in Symp. VLSI Circuits Dig. Tech.
Papers, June 2009, pp.236-237.
[51] M. Yoshioka, K. Ishikawa, and T. Takayama, “A 10b 50MS/s 820μW SAR ADC with on-chip digital calibration,” in ISSCC Dig. Tech. Papers, Feb. 2010,
pp 384-385.
pp. 384 385
[52] C. C. Liu, et al., “A 10b 100MS/s 1.13mW SAR ADC with binary-scaled error compensation,” in ISSCC Dig. Tech. Papers, Feb. 2010, pp. 386-387.
[53] Y. Zhu, et al., “A 10-bit 100-MSs reference-free SAR ADC in 90 nm CMOS,” IEEE J. Solid-State Circuits, vol. 45, no. 6, pp. 1111-1121, June 2010.
[54] P. N. Singh, A. Kumar, C. Debnath, and R. Malik, “A 1.2v 11b 100Msps 15mW ADC realized using 2.5b pipelined stage followed by time interleaved SAR
in 65nm digital CMOS process,” in Proc. CICC, Sept. 2008, pp. 305-308.
[55] H. W. Chen, Y. H. Liu, Y. H. Lin, and H. S. Chen, “AA 3mW 12b 10MS/s sub-range
sub range SAR ADC,”
ADC, in Proc. ASSCC, Nov. 2008, pp. 153153-156.
156.
[56] J. J. Kang and M. P. Flynn, “A 12b 11MSps successive approximation ADC with two comparators in 0.13μm CMOS,” in Symp. VLSI Circuits Dig. Tech.
Papers, June 2009, pp. 240-241.
[57] W. Liu, P. Huang, and Y. Chiu, “A 12b 22.5/45MS/s 3.0mW 0.059mm2 CMOS SAR ADC achieving over 90dB SFDR,” in ISSCC Dig. Tech. Papers,
Feb. 2010, pp. 380-381.
[58] C. C. Lee and M. P. Flynn, “A 12b 50MSps 3.5mW SAR assisted 2-stage pipeline ADC,” in Symp. VLSI Circuits Dig. Tech. Papers, June 2010, pp.239-240.
A Calibration-
Calibration-Free 14b 70MS/s
0.13um CMOS Pipeline ADC
with High-
High-Matching 3D
3 Symmetric
S C
C’s
Sept. 2006 (CICC)
SEUNG-HOON LEE
D t off El
Dept. Electronic
t i Engineering
E i i
Proposed 3
3-
-stage Pipeline ADC
AIN SHA MDAC1 MDAC2
I/V REFERENCE
FLASH
H
FLASH
FLASH
ADC1
ADC3
ADC2
WITH OFF-CHIP 5-b 5-b
CAP FILTERS
TIMING CIRCUIT 5-b 5-b 6-b
DIGITAL CORRECTION LOGIC

Q1P
Q1 14 b
14-b
Q2P
Q2 OPT. DECIMATOR ( 1/1, 1/2, 1/4 fs ) 14-b
DOUT
Sample-
Sample-and-
and-Hold Amplifier (SHA)
Q1 Q1B
MP3 OUT+
MN3
GT Q2PB Q2
GATE- C3
BOOTSTRAPPING BIAS T1
C1 MG1 MS1
IN+ Q1B
MN1 AT ACC Q2PB
AMP1 MP1 MP2 AMP2
MN2 AC ACT
IN- MT
C2 MG2 MS2
GATE- BIAS T2 C4
BOOTSTRAPPING GC
Q2PB Q2
MN4
Q1P MP4
Q1 OUT
OUT-
Q2 : SAMPLING PHASE
Q2 Q1 : HOLDING PHASE Q1 Q1B
 14b SHA with a DC gain of 95dB, f-3dB of 246MHz, and φPM of 74°
 Gate-bootstrapped sampling switches for low input distortion with 4pF

sampling capacitors
3D Symmetric C Layout of MDAC (V1)
MET4
VIA3
MET3
VIA2
MET2
VIA1
MET1
: MIM Capacitor Top Plate

: Stacked metals of MET1, 2, 4
: Stacked metals from MET1
to MET4
 MDAC capacitor mismatch critical to ADC non-linearity
 Both MDAC capacitors and signal lines isolated

3D Symmetric C Layout of MDAC (V2)
MET4
VIA3
MET3
VIA2
MET2
VIA1
MET1

: Stacked metals from MET1
to MET4
 Only MDAC capacitors isolated
 High-matching
Hi h t hi capacitors
it insensitive
i iti tot neighboring
i hb i signals
i l
Proposed On
On-
-Chip I/V References
ON- CHIP VDD VDD OFF- CHIP

I/V REFERENCES EXTRFB FILTERS
MPS
( Required )
IVCN
T1
OP
REFTO
AMPT MPB
CB1
IREF & REFT
Cc1 Rc1
VREF LEVEL
SHIFTER
REFC Cc2 Rc2
REFBOT
T
CB2
AMPC` MNB
EXTRF EXTRFB T2
MNS
EXTRF
Optional Ext. Voltage References VSS VSS
Available with “EXTRF” High
Simulated Voltage Driver Outputs
0.57 -0.43
off-chip 0.1uF C off-chip 0.1uF C

TOP [ V ]
T/2 = 7.14ns
7 14
BOT [ V ]
T/2 = 7.14ns
+ 0.06mV + 0.06mV
0.50 -0.50
REFB
REFT
- 0.06mV - 0.06mV
- 0.06mV
Settling time = 2.72ns Settling time = 2.27ns

38% of T/2 32% of T/2
Ideal = GND + 0.5 Ideal = GND - 0.5

0 43
0.43 0 57
-0.57
98 100 102 98 100 102
Time [ ns ] Time [ ns ]
Prototype ADC Chip Photo
FLASH1
FLASH2
FLASH3
 Designed and laid out with
DCL
a 0.13um
0 13 1P7M CMOS :
D
( Only 4 metals employed )
CLK
 Occupied die area : 3.3mm2

IVREF ( = 1.65mm  2.01mm )
 Decoupling capacitors ( )
CML
SHA MDAC1 MDAC2

laid out in each functional block
to reduce coupling noise
Evaluation Board
Digital Power Latch Power
 Design issues :
Voltage
g
Regulator - High speed digital latch
Digita
at outputs
Crystal Digital
DUT
al Outputts
Oscillator L t h
Latch - Passive filters at inputs
Analog
Input - Crystal Oscillator with a
ji
jitter off 1ps
1 level
l l
- Voltage regulators with

low glitch
Analog Power
Measured DNL & INL of ADC (V1)
1
DNL [ LSB/14b ]
-1
0 CODE 16383
10
b]
LSB/14b
0
INL [ L
-10
0 CODE 16383
Measured DNL & INL of ADC (V2)
1
DNL [ LSB/14b ]
-1
0 CODE 16383
2
b]
LSB/14b
0
INL [ L
-2
0 CODE 16383
Measured FFT Plot of ADC (V2)
0
Latch
fin = 1MHz fs
fs = 70MHz DUT
(16384 FFT) (fs) ½fs Outputs
-50 ¼fs
dB ]
Harmonic distortions closely related

[d
to the signal generator performance
-100
100
-150
0 17.5
F
Frequency [ MHz
MH ]
Measured SFDR & SNDR vs. Sampling Freq.
90
80 SFDR(V2)
SFDR(V1)
dB ]
70
[d
SNDR(V2)
SNDR(V1)
60
f in = 1MHz
0
0 20 40 60 80
Sampling
p g Frequency
q y [ MHz ]
Measured SFDR & SNDR vs. Input Freq.
80
SFDR(V2)
70
SFDR(V1)
dB ]
[d
SNDR(V2)
60 SNDR(V1)
f s = 70MHz
0
1 10 20 30 40
Input Frequency [ MHz ]
Measured ADC Performance
VERSION1* VERSION2*
Resolution 14bits
Max. Conversion 70MS/s
Process 0.13um CMOS ( Lmin = 0.35um for 2.5V systems
y )
Input Range 2.0Vp-p
SNDR (at fin = 1MHz) 63.4dB 65.7dB
SFDR (at fin = 1MHz) 72.2dB 80.6dB
DNL - 0.66LSB / + 0.77LSB - 0.60LSB / + 0.65LSB
INL - 4.62LSB / + 9.82LSB - 0.98LSB / + 1.80LSB
ADC Core Power 235mW at 70MS/s and 2.5V
Active Die Area 3.3mm2 (= 1.65mm × 2.01mm)
* VERSION1 : MDACs with both capacitors and signal lines isolated

* VERSION2 : MDACs with only capacitors isolated
Power vs. Speed of 14b to 16b ADCs
1000 CICC03-16b
ISSCC00-14b
Consumption [ mW ]
ISSCC04-15b
SSCC0 5b
JSSC05-15b
ISCAS01-15b ISSCC04-14b ISSCC01-14b
JSSC02-14b
ISSCC04-15b
VLSI96-14b
ESSCIRC05-14b This Work
ISCAS00 14b
ISCAS00-14b ((= 3.36mW/MHz)
Power C
ISSCC04-14b
100 JSSC04-14b CALIBRATION-FREE ADC
CALIBRATED ADC
P
10 100
Sampling Rate [ MHz ]
A 10b 25MS/s 4.8mW 0.13um CMOS
ADC
for DMB Application
for
Sept. 2006 (CICC)
SEUNG-HOON LEE
D t off El
Dept. Electronic
t i Engineering
E i i
Proposed 2
2-
-step Pipeline ADC
AIN SHA MDAC
DNCK PDOWN PDOWN

I/V References
With Optional Off-chip FLASH FLASH
Cap Filters 5-b
ADC1 ADC2
Timing Generator
PDOWN PDOWN
5-b 6-b
Q1P
Q1
Digital Correction Logic 10-b
Q2P DOUT
Q2
 PDOWN : Power Down Mode
 DNCK : 25MS/s and 10MS/s Sampling Clock Selection`

Switched-
Switched-Bias Power Reduction for SHA
<AMP = 68% of SHA power> <BIAS = 32% of SHA power>

VDD
M4 M5 VDD
MP1 MP2 MP3 MP4 MP5 MP6
30%Ⅰ
reduced 2
M6 M7 BIAS1
IN IN OUT 70 : 30
BIAS2
Q
+ + 1
M1 M2 M8 M9 IREF
BIAS4
100%Ⅰ
reduced
M10 M11 1
M3 MN1 MN2 MN3 MN4
VSS Amplifying
VSS
Current Reduction in Sampling Sequence Delay Cell
 Sampling - Currents reduced by 30% with BIAS1 & 2 and by 100% with BIAS4
g
 Holding - Currents resumed with switching
g sequence;
q ;
 Total (= AMP + BIAS) power consumption reduced by 10%
Switched-
Switched-Bias Power Reduction for MDAC
<AMP = 96% of MDAC power> <BIAS = 4% of MDAC power>

VDD VDD
M4 M5 M12 M13
2 MP1 MP2 MP3 MP4 MP5 MP6
20%Ⅰ
reduced OUT BIAS1
+ BIAS2 80 : 20
M6 M7
IN IN
AMP1 AMP2 Q2
+ M14 M15 IREF
M1 M2 M8 M9
BIAS4
100%Ⅰ
reduced
M10 M11 M16 1
M3 MN1 MN2 MN3 MN4
VSS
Amplifying VSS
Current Reduction in Sampling
p g Sequence
q Delay
y Cell
 Sampling - Currents reduced by 20% with BIAS1 & 2 and by 100% with BIAS4
 Amplifying - Currents resumed with switching sequence;

 Total (= AMP + BIAS) power consumption reduced by 10%
Switched-
Switched-Bias Power Reduction for FLASH
<All PREAMPS = 45% <BIAS + DIGITAL = 55%

of FLASH ADC power> of FLASH ADC power>
VDD
M1 M2 M3 M4 VDD
MP1 MP2 MP3
OUT 75 : 25
+ CK
IN IN
AMP 75%Ⅰ IREF
+ reduced
M5 M6
M7 M8 BIAS1 MN1
VSS
VSS
 Sampling - Currents reduced by 75% with BIAS1
 Amplifying - Currents resumed with BIAS1 fully turned on
 Total (= PREAMPS+BIAS+DIGITAL) power reduced by 17%

Merged Capacitor Switching (CICC’
(CICC’02)
T1
VOUT Conventional 5b
AMP
MDAC
C1 C2 C3 C4 C5 C6 C29 C30 C31 C32
+VREF +VREF +VREF -VREF -VREF -VREF -VREF -VREF
1 1 1 0 0 0 0 0
+VREF GND -VREF -VREF F/B
T1
VOUT Proposed
AMP
5b MDAC
C1' C2' C3' C15' C16'
+VREF GND -VREF -VREF
 Reduced number of capacitors by 50% :
- Increases operating speed of amplifiers with less power
- Improves C matching accuracy and noise performance

DCL
SH1
SH2
 Designed and laid out with
FLAS
FLAS
a 0.13um 1P8M TSMC CMOS :
CLK
p
 Occupied die area : 0.80mm2
(= 0.67mm  1.18mm)
 Decoupling capacitors
IVREF (PMOS : , NMOS : ) laid out
separately in each functional block
MDAC t reduce
to d coupling
li noise
i
CML
L
SHA
Measured DNL & INL
b]
DNL [ LSB/10b 1.0
-1.0
0 CODE 1023
1.0
SB/10b ]
0
INL [ LS
-1.0
0 CODE 1023
NOMINAL MODE DOWN-CLOCK MODE

Resolution 10bits
Max. Conversion 25MSample/s 10MSample/s
Process 0.13um CMOS ( with MIM Capacitors )
Input Range 1.0Vpp
SNDR 56dB (at fin = 1MHz)
SFDR 65dB (at fin = 1MHz)
DNL - 0.42LSB / + 0.41LSB
INL - 0.89LSB / + 0.91LSB
ADC Core Power 4.8mW @ 1.2V 2.4mW @ 1.2V
Active Die Area 0.8mm2 (= 0.67mm × 1.18mm)
Power vs. Speed Comparison
100
: 1.5b/stage ISCAS01
: 2.5b/stage ISSCC03 CICC03
ESSCIRC05
: 3b-3b-3b-4b
mption [[mW]
ISCAS00 ESSCIRC05
: 4b-3b-3b-3b ISSCC05
: 2b-3b-3b-3b-3b
2b 3b 3b 3b 3b ISSCC04
VLSI 04
: 3b-3b-3b-3b-2b
JSSC03
ISSCC06
Consum
ISSCC02
ISSCC06
ESSCIRC02
Power C
This Work
ISSCC05 (5b--6b p
((5b pipeline
p : 0.19mW/MHz))
P
1
2 Speed
p [MHz]
[ ] 100 200
A Re-
Re-configurable 0.5V to 1.2V,
10MS/s to 100MS/s, Low-
Low-Power
10b
10 00.13um
13 C
CMOS
OS Pipeline ADC C
Sept. 2007 (CICC)
SEUNG-HOON LEE
D t off El
Dept. Electronic
t i Engineering
E i i
Proposed 2
2-
-step ADC Architecture
AIN SHA MDAC
I/V REFERENCE
WITH OPTIONAL OFF- FLASH FLASH
CHIP C FILTERS 5-b
ADC1 ADC2
TIMING GENERATOR
5-b 6-b
Q1P
Q1
Q2P DIGITAL CORRECTION LOGIC 10-b
10 b
Q2 & DECIMATOR DOUT
Sample-
Sample-and-
and-Hold Amplifier (SHA)
Q1 Q1B
MP3 OUT+
MN3
GT Q2PB Q2
GATE- C3
T1
BOOTSTRAPPING BIAS
C1 MG1 MS1
IN+
MN1 AT ACC Q2PB Q1B
AMP1 MP1 MP2 AMP2
MN2 AC ACT
IN- MT
C2 MG2 MS2
GATE- BIAS T2 C4
BOOTSTRAPPING GC Q2PB Q2
MN4
Q1P MP4
Q1 OUT-
Q2 : SAMPLING PHASE
Q2 Q1 : HOLDING PHASE Q1 Q1B
 10b SHA based on a 2-stage low-voltage amp with 69° φPM
 Gate-bootstrapped sampling SWs for 10b accuracy at 0.5V to 1.2V supply

All Directionally-
Directionally-isolated MDAC Cs
MET4
VIA3
MET3
VIA2
MET2
VIA1
MET1

: Stacked Metals of MET1, 3, 4
: Stacked Metals of MET1, 2, 4
z
: Stacked Metals from MET1
to MET4
 MDAC capacitor mismatch critical to ADC non-linearity
 Both MDAC capacitors and signal lines isolated

Proposed On
On-
-Chip I/V References
IREF VREF LEVEL SHIFTER VREF DRIVER ON-CHIP FILTER
POFF VDD VDD VDD VDD
EXTRFB EXTRFB Rf2 Cf2

IVCN
MRS MPS
VREFIN
IREF TR1 T1
AMPR MR1 AMPT MPB
Rf1 Cf1
REFT
AMP_BIAS Cc1 Rc1

C1
R1
BIAS TR2
Cc2 Rc2
R2
EXTRF EXTRFB EXTRFC AMPC MNB

REFC REFTOP
T2
IR3 R3 TO on-
on-chip
MNS
ADC
EXTRFC
REFBOT
VSS VSS VSS
 Optional external voltage reference employed

LK
CL
DCL
ASH2
ASH1
 Implemented with a 0.13um
1P6M Samsung CMOS :
FLA
FLA  Occupied die area : 0.98mm2
( = 0.82mm  1.20mm )
IVREF  Decoupling
p g capacitors
p
( PMOS : , NMOS : )
CML
laid out separately in each

SHA MDAC functional block to reduce
coupling noise
Measured DNL & INL of ADC
0b ]
DNL [ LSB/10 1.0
-1.0
0 CODE 1023
1.0
b]
LSB/10b
0
INL [ L
-1.0
0 CODE 1023
Resolution 10bits
Process Samsung 0.13um CMOS ( MIM Cap. )
Input
p Range
g / On-Chip
p REF 0.8Vpp ((Fixed,, Off-Chip
p Ref Optional)
p )
Power Supply 0.5V (Min.) 0.8V (Typ.) 1.2V (Max.)

Max. Conversion Rate 10MS/s 60MS/s 100MS/s
SNDR 52.9dB 56.0dB 53.3dB
SFDR 64 9dB
64.9dB 69 6dB
69.6dB 70 2dB
70.2dB
ADC Power 3.0mW 19.2mW 45.6mW
DNL INL
DNL, 0 35LSB / 0
0.35LSB 0.49LSB
49LSB
Active Die Area 0.98mm2 ( = 0.82mm × 1.20mm )

Comparison to Previous 10b ADCs
Supply Speed Power Area DNL / INL

[V] [ MS/s ] [ mW ] [ mm2 ] [ LSB ]
This Work 0.5~1.0 10~100 3~45.6 0.98 0.35 / 0.49
ISSCC’07 0.8 80 6.5 0.64 0.80 / 1.00
ISSCC’07
ISSCC 07 10
1.0 30 47
4.7 0 32
0.32 0 47 / 0
0.47 0.80
80
VLSI’06 1.0 100 30.0 4.03 0.50 / 0.80
CICC’05 1.0 100 40.0 0.52 0.38 / 0.96
ISSCC’07 1.0 160 84.0 0.42 -/-
ISSCC’07 1.0 205 111.0 1.00 0.50 / 0.50

A 10b 100MS/s 24
24.2mW
2mW 0 0.80mm
80mm2
0.18um CMOS ADC
With Various
V i Circuit
Ci it Sharing
Sh i Techniques
T h i
Oct. 2009 (IET)
SEUNG-HOON LEE
D t off El
Dept. Electronic
t i Engineering
E i i
Proposed 10b 100MS/s Pipeline ADC
1.8V
1.8V power supply region Programmable from 1.2~1.8V
4b
FLASH
CLOCK ADC2
GENERATOR
4b
Q1P
PREAMPS
S
CORRECTION LOGIC C
R-STRING
G
SHARED
SHARED
TOR (1/1, 1/2, 1/4 fs)

Q1
Q2P MDAC2
Q2
MDAC2
C_ARRAY 4b
FLASH
AS1 AS2
ADC3
MDAC1
AIN SHA 10b
C_ARRAY
DOUT
DECIMAT
DIGITAL C
R-STRING
SHARED
MDAC1
4b
ON-CHIP I/V
4b
REF FLASH
WITH FILTERS ADC1
Proposed OP
OP-
-AMP Sharing Technique
Q2
MDAC1 CF1 CC Q1 Q1P
Q1
VIN1 Q2P
Q1
Q2
IN1
Q2 Q1P Q2B
VDAC1 CS1
AS1 AS2
VCOM VOUT Q1B
IN2
Q1
MDAC2 MDAC1 S A
Q2
CF2 MDAC1 & MDAC2
VOUT MDAC2 A S
Q2
Q2P (IN1+) & (IN1-) : VCOM @ Q1 S : SAMPLING INPUT
VDAC2 Q1 CS2
Phase A : AMPLIFYING RESIDUE
VCOM (IN2+) & (IN2-) : VCOM @ Q2
Phase
 AS1 with two of differential input pair based on a switched OP-AMP

 No additional switch and series resistance improve signal settling of MDAC
 Inactive input-pair transistors reset to a fixed bias voltage → No memory effect
OP-
OP-AMP Implementation in MDAC
AS1 AS2
Q1 Q1P
Q
BS1 BS1
BS4 Q2 Q2P
BS2 - VO1+ BS2
Q2B
BS3 BS3 VO1+
- VO2 + Q1B
IN1+ OVERLAP
IN2-
VO1- MDAC1 S A
IN1- IN2+
MDAC2 A S
Q1B Q2B
CMFB2
S : SAMPLING INPUT
STATIC CMFB1 A : AMPLIFYING RESIDUE
CURRENT
 Shared amplifiers, AS1, based on an OP-AMP reusing bias currents

 Slightly overlapped clock phase Q1B and Q2B used in the switched OP-AMP,
AS1, to reduce glitch signals for fast settling behavior
Structure of the Proposed FLASH ADC
FLASH1 (4-bit) FLASH2 & FLASH3 (4-bit)

LATCH1 PREAMP1 REFTOP PREAMP2 LATCH2 LATCH3
16 LATs 10 DDAs 8 DDAs 14 LATs 14 LATs A single
g shared
resistor string
Shared
Sh d Preamps
P
(DDA)
Kickback-reduced
Ki kb k d d
dynamic latch
MDAC’s load Interpolation

REFBOT For LATCH1, 2, 3
 Single resistor ladder shared among three sub-ranging flash ADCs

 Differential Difference Amplifier(DDA) as shared preamp operating continuously
 Number of preamps reduced in half with interpolation technique
CML
SHA
A
IV
VREF
MDA
AC1
FLA
ASH1
Chip Photo of the Prototype ADC
1.08mm
SHAR
RED R-STRING
OP-A
AMP SHA
ARED
PRE
EAMPS
- Active Area : 0.80mm2 - FLA

ASH2
&
MDA
AC2
FLA
ASH3
CLOCK
K DCL
L
0.74
4mm
Measured DNL & INL
10b ]
L [ LSB/1 1.0
0
DNL
-1.0
0 CODE 1023
1.0
INL [ LSB/10b ]
-1.0
0 CODE 1023
80
SFDR VDDA=1.8V, VDDD=1.8V
SNDR VDDA=1.8V, VDDD=1.2V
70 68 8dB
68.8dB
dB ]
64.9dB
60
[d
54.2dB
50 51.3dB
fIN = 4MHz
40
20 40 60 80 100
Sampling frequency (=fS) [ MHz ]
80
SFDR VDDA=1.8V, VDDD=1.8V
SNDR VDDA=1.8V, VDDD=1.2V
70
65.8dB
dB ]
60 62 2dB
62.2dB
[d
52.4dB
50
49.4dB
fS = 100MHz
40
20 40 60 80 100
Input frequency (=fIN) [ MHz ]
Resolution0 10bits
Conversion Rate 100MS/s
Process 0.18um CMOS
Input Range 1.2Vp-p
DNL - 0.49LSB / + 0.58LSB
INL - 0.84LSB / + 0.76LSB
Supply Voltage VDDA = 1.8V VDDD = 1.2V VDDA = 1.8V VDDD = 1.8V
51.3dB (at fin = 4MHz) 54.2dB (at fin = 4MHz)
SNDR

SFDR
Total With On-chip

O hi REFs
REF 22 4 W
22.4mW 24 2 W
24.2mW
Power With Off-chip REFs 19.0mW 20.8mW
Active Die Area 0.80mm
0 80mm2 ((= 1.08mm
1 08mm × 0.74mm)
0 74mm)
Comparison of 10b ADCs
fs VDD Power Area SNDR FoM Tech

(MHz) (V) (mW) (mm2) (dB) (pJ/step) (nm)
This Work 100 1.8 24.2 0.80 54.2 0.58 180
ISSCC 03 80 1.8 69.0 1.85 58.8 1.21 180
JSSC 08 100 3.0 27.0 1.21 51.5 0.78 180
ASSCC 08 100 1.8 31.0 1.28 56.2 0.59 180
JSSC 04 100 1.8 67.0 2.52 54.0 1.64 180
ISSCC 05 125 1.8 40.0 0.66 53.7 0.79 180
ISSCC 03 140 1.8 65.0 0.95 55.4 0.96 180
VLSI 09 80 1.2 22.4 0.16 53.8 0.69 65

ISSCC 08 100 1.2 4.5 0.07 59.0 0.06 65
JSSC 07 100 1.0 33.0 4.03 55.3 0.69 90
CICC 05 100 1.0 40.0 0.52 56.5 0.73 90
ISSCC 06 120 1.2 36.0 0.30 58.5 0.50 90
ISSCC 04 120 1.2 90.0 1.34 57.5 1.22 130
A 9.43-
9.43-ENOB 160MS/s 1.2V 65nm
CMOS ADC
Based on Multi-
Multi-Stage
S Amplifiers
f
Sept. 2009 (CICC)
SEUNG-HOON LEE
D t off El
Dept. Electronic
t i Engineering
E i i
Proposed 12
12-
-b ADC Architecture
A1 A2 A3 A1 A2
AIN SHA MDAC1 MDAC2 MDAC3
CURRENT & Sub- Sub- 4-b

Sub- Sub-
3-b 4-b
VOLTAGE ADC1 ADC2 ADC3 ADC4
REFERENCE
3-b 4-b 4-b 4-b
DIGITAL CORRECTION LOGIC

TIMING
GENERATOR 12-b 12-b
DOUT
OPT DECIMATOR ( 1/1
OPT. 1/1, 1/2,
1/2 1/4 fs )
Sample-
Sample-and-
and-Hold Amplifier (I)
◈ Input Sampling Mode

Q2 Q2B Q1 Q1B
VCM
OUTT
GATE- CD1
BOOTSTRAPPING Q2PB
VCM Cc3
C1 Cc1
INT
AMP1 Q2PB AMP2 Q2PB AMP2 Q2B
INC
Cc2
C2 VCM Cc4
GATE- Q2PB
BOOTSTRAPPING CD2
Q1P OUTC
VCM Q1
Q2 : SAMPLING PHASE
Q2
Q Q1 : HOLDING PHASE
Q2 Q2B Q1 Q1B
 Gate-bootstrapping
pp g input-sampling
p p g switches
 Reset output nodes of amplifiers
Sample-
Sample-and-
and-Hold Amplifier (II)
◈ Holding Mode
OUTT-OUTC
Q2 Q2B Q1 Q1B
= {C1/(C1+CD1)} x (INT
(INT-INC)
INC)
VCM
OUTT
GATE- CD1
BOOTSTRAPPING Q2PB
VCM Cc3
C1 Cc1
INT
AMP1 Q2PB AMP2 Q2PB AMP2 Q2B
INC
Cc2
C2 VCM Cc4
GATE- Q2PB
BOOTSTRAPPING CD2
Q1P OUTC
VCM Q1
Q2 : SAMPLING PHASE
Q2
Q Q1 : HOLDING PHASE
Q2 Q2B Q1 Q1B
 Adjusted
j signal
g swing
g range
g from 1.4Vp-p
p p to 1.0Vp-p
pp
 Three-stage amplifier with multi-path RNMC
3-Stage Amplifier with RNMC
Cm1
Cm2
Vin Vout
gm1 -gm2 gm3
R1 C1 R2 C2 R3 CL
Cm 2 C C
(1  s  s 2 m1 m 2 )
g m1 g m 2 g m3 R1R2 R3 g m2 g m 2 g m3
) RNMC 
H ( s ), ·
(1  sg m 2 g m 3 R1R2 R3Cm1 ) {1  s Cm 2 ( g m 2 (Cm1  C L )  g m3Cm1 )  s 2 Cm 2C L }
Cm1 g m 2 g m3 g m 2 g m3
 Reversed nested miller compensation
p ((RNMC))
 Three poles and two zeros
3-Stage Amp with Multi
Multi-
-path RNMC
Cm1
-g
gmf
Cm2
Vin Vout
gm1 -gm2 gm3
R1 C1 R2 C2 R3 CL
Cm1
(1  s )
g m1 g m 2 g m3 R1R2 R3 gm2
) MRNMC 
H ( s ), ·
(1  sg m 2 g m 3 R1R2 R3Cm1 ) {1  s Cm 2 ( g m 2 (Cm1  C L )  g m3Cm1 )  s 2 Cm 2C L }
Cm1 g m 2 g m3 g m 2 g m3
 Additional feed-forward p
path to remove the RHP zero
 Three poles and one zero
Fully Differential 3-
3-Stage Amplifier
1st-amp 2nd-amp 3rd-amp

VDDA
VB2 VB5 VB8
VB6
VB3
OUTT OUTC
+
VB7
INC INT
+
VB4
VB1 CMFB1 CMFB2 CMFB3
VSSA
 Multi-path 3-stage amplifier excluding compensation capacitors

Prototype 12-
12-b ADC Chip Photo
CLOCK DCL
IVREF
Sub ADCs
Sub-ADCs MDAC3
mm
0.73m
CML
SHA MDAC1 MDAC2

C
0.99mm
Evaluation Board
Analog Digital PAD

Power Power Power  PCB design
issues :
- Socket for a ball

type package
- Single-ended
Single ended and
Socket
differential inputs
Output
Digital
available (both)
Digital
Buffer - Passive filters at
Analog analog inputs
Input
- High-speed
High speed digital
PAD
Power
buffer at outputs
Test Point
Measured DNL and INL
1.5
b]
LSB/12b
0
DNL[ L
-1.5
0 CODE 4095
1.5
2b ]
INL[ LSB/12
-1.5
0 CODE 4095
Measured FFT Plot
• SNDR = 58.5dB
• SFDR = 76.0dB
• Fin = 4
4.2MHz
2MHz
• Fs = 160MHz (1/4 fs sampled)
B]
- 50 • 4096-points
p
[ dB
- 100
0 Frequency [ MHz ] 20
90
SFDR
80
SNDR
70
[ dB ]
60
50
f in = 4.2MHz
40
30
10 50 100 150 160 180 200
Sampling Frequency [ MHz ]
90
SFDR
80
SNDR
70
[ dB ]
60
50
f s = 160MHz
40
30
5 10 20 30 40 50 60 70 80
Input Frequency [ MHz ]
Resolution 12-b
Speed 160MSample/s 200MSample/s
Process 65nm CMOS
Supply 1.2V (Analog & Digital)
Input Range 1.4Vp-p (Differential)
58.5dB (at fin = 4.2MHz)
SNDR 53 1dB (at fin = 4.2MHz)
53.1dB 4 2MHz)
54.2dB (at fin = 80MHz)
76.0dB (at fin = 4.2MHz)

SFDR 67 8dB (at fin = 4.2MHz)
67.8dB 4 2MHz)
67.2dB (at fin = 80MHz)
DNL - 0.61LSB / + 0.69LSB
INL - 1.00LSB / + 0.94LSB
Power 82mW @ 1.2V
Die Area 0.72mm2 (0.99mm × 0.73mm)
Comparison to Previous 12-
12-b ADCs
Supply Speed Power Area DNL / INL FoM

Process
[V] [ MS/s ] [ mW ] [ mm2 ] [ LSB ] [ pJ/conv. ]
0.69 / 65nm
This Work 1.2 160 82 0.72 0.75
1.00 CMOS
0.35um
VLSI’06 3.0 75 273 7.90 0.64 / 0.95 2.34
CMOS
0.18um
ESSCIRC’02 3.0 80 259 5.46 0.85 / 1.70 2.40
CMOS
90nm
SSCIRC’06 1.2 100 55 5.78 1.00 / 3.40 0.70
CMOS
0.18um
JSSC’05 1.8 110 97 0.86 1.20 / 1.50 0.67
CMOS
0.13um
ISCAS’08
ISCAS 08 12
1.2 120 52 0 56
0.56 0 30 / 0
0.30 0.95
95 0 46
0.46
CMOS
HIGH--SPEED CMOS COMPARATORS
HIGH
AS A DESIGN EXAMPLE
SEUNG--HOON LEE
SEUNG
D t off El
Dept. Electronic
t i Engineering
E i i
COMPARATORS
A. DEFINITION
VDD Vo
+
+
Vi VO Vi
VOS
- -
TRANSFER FUNCTION
VSS
“1 BIT A/D CONVERTER”
Vi Vo
A
1mV
t t
WAVEFORMS
IN A REAL CIRCUIT
COMPARATORS
B. COMPARISON BETWEEN OP AMPS AND COMPARATORS
GAIN IN dB GAIN IN dB
B.W.
 
 ① UNCOMPENSATED
② OPEN-LOOP OPERATION
-135º
135 ③ WIDER BANDWIDTH (B
(B.W.)
W)
 FASTER
OP AMP (
( COMPENSATED)
COMPARATORS
C. REQUIREMENTS OF COMPARATORS
(1) HIGH DIFFERENTIAL GAIN
(2) LOW OFFSET VOLTAGE
(3) HIGH COMMON MODE REJECTION

POWER SUPPLY REJECTION
(4) HIGH BANDWIDTH

FOR HIGH-SPEED OPEN-LOOP RESPONSE
((5)) LOW POWER CONSUMPTION,, SMALL AREA
(6) LOW INPUT CAPACITANCE
(7) LOW NOISE OPERATION

NON-
NON-SAMPLING AND SAMPLING COMPARATORS
A. NON-SAMPLING COMPARATORS
Vi VO
Vi LATCH VO
STROBE
“1”
1 “0”
0
DON’T CARE
NON-
NON-SAMPLING AND SAMPLING COMPARATORS
B. SAMPLING COMPARATORS
1
1
Vi LATCH VO
2 STROBE
① PROS ; OFFSET CAN BE CANCELLED
② CONS ; NEED CLOCKS AND COMPLICATED
③ A GOOD SOLUTION FOR HIGH-SPEED OPERATION

(~10 MHz ~1 GHz LEVEL)
AMPLIFIER ARCHITECTURE OF COMPARATORS
A. SINGLE-STAGE WITH HIGH GAIN ( OP-AMP STYLE )
VDD
Vi
Vo
Vbias
VSS
LOW POWER, BUT SLOW
(EX) x1000
AMPLIFIER ARCHITECTURE OF COMPARATORS
B. MULTI-STAGE WITH AUTO-ZEROED ARCHITECTURES
x10 x10 x10
MEDIUM POWER, BUT FASTER
C. OPTIMIZATION OF POWER AND STAGES
Vo
t
POSITIVE FEEDBACK LATCH CIRCUITS
A. COMPARATOR LATCH
STROBE
COLUMN COLUMN
R 1 R
ROW ROW
V
~ 100 mV
0 01 pF
0.01 0 01 pF
0.01
2
CCOLUMN
0.5  1 pF
Vo GAIN=1
TWO-STABLE POINTS
(Bi STABLE)
Vi
B. OPERATION
5 V (“1”)
( 1 )
① DYNAMIC ERRORS
V1, V2  MINIMUM LATCH INPUT VOLTAGES
~ 100 mV
V ERRORS
TO GET RIGHT ANSWERS !!
0 V ((“0”))
1 on 2 on
② CALCULATE REGENERATION TIME

R R IN THE LATCH CIRCUITS
V1((0)) V2((0))
WHAT IS
S THE EQUATION
Q O OF
O (V
( 2(t)
( ) - V1(t))
( )) ?
C M1 M2 C
gm1 gm2
C. VARIATIONS OF LATCH CIRCUITS
gm2 > gm1
① ②
VDD  LATCH
 
gm1 gm1 gm2 gm2
S
SELF - BIASED
S
OFFSET AND FEEDTHROUGH (F.T.) CANCELLATION
A. ORIGIN
RANDOM
① VOS  BY DEVICE MISMATCH
SYSTEMATIC
② F.T. ERRORS FROM SWITCHES
 
Cov VTH
VCK-
COL
VI C  VF.T. = (VTH - VCK-)
C
FOR SLOW TRANSITION CLOCKS

VCK+
VCK-
1/2Q 1/2Q Q = COXWL
VI C
1 Q IS MOVED TO C FOR FAST
2
TRANSITION CLOCKS
B. Vos CANCELLATION
① USE CLOSED-LOOP OFFSET CANCELLATION WITH

SAMPLING CAPACITORS
1
1
Vos
VO
A
2
VIN
(UNITY-GAIN STABLE !)
Vos Vos Vos

VO Vin VO
A A
((=VOS ) AVIN
(a) 1 ((b)) 2
SIMPLE, BUT F.T. ERRORS ARE NOT CANCELLED
② OPEN-LOOP OFFSET CANCELLATION
Vos A1Vos
A1 A2
SLOW
((UNITY-GAIN STABLE REQUIRED))
C. Vos AND F.T. SIMULTANEOUS CANCELLATION

(CORRELATED DOUBLE SAMPLING : CDS)
1 2 3
4
V1 A1 A2 A3
4
1 2 3
1
2 Vos1 SAMPLE
3 Vos2 SAMPLE & VFT1 SAMPLE
4 Vos2 SAMPLE & Ai VFT1 + VF2 SAMPLE
AMPLIFY
F.T. ERROR CORRECTION
① BOTH OF Vos AND VF.T. CANCELLED
② 1/f NOISE REDUCED, BUT
③ WIDE-BAND kT/C NOISE DOUBLED

④ AMPLIFIERS CAN BE SATURATED DEPENDING ON
MAGNITUDES OF A1, A2, A3
⑤ OPEN-LOOP Vos SAMPLING CAN BE USED TO AVOID

UNITY-GAIN STABLE OPERATIONS OF OP AMPS
D. AUXILIARY INPUT OFFSET & F.T. ERROR CANCELLATION

1
3 Vos1
A1
Vos2
A2
COFF COFF
2
1
2 VOS AND VF.T.

SAMPLING IN COFF
3
A1VOS1 + A2VOS2
VOS(input-referred) =
A1(1+A2) PROVE IT !!
A1 A2
E. DESIGN TECHNIQUES FOR HIGH PERFORMANCE
(1) USE FULLY DIFFERENTIAL ARCHITECTURE

(2) USE AS MINIMUM STAGES AS POSSIBLE
WITH HIGH-SPEED
HIGH SPEED LATCH FOR
- GOOD CMRR, PSRR
- LOW TRANSIENT NOISE COUPLING FROM SUBSTRATE
- FIRST-ORDER CHARGE F.T. CANCELLATION

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CMOS 혼성모드 시스템

군사분야 가전/정보분야 통신/SDR분야

• Logic : CPU, DSP

High Speed Low Power

LNA ADC DSP

입출력 : 수 GHz의 RF (Radio Frequency) 신호 LNA : Low Noise

■ Camcorder 응용 회로 (A/D Interface Circuit : CCD, CIS 등)

CCD IMAGE SENSOR INTERFACE CIRCUIT

기능 : CCD (Charge-Coupled Devices) Image Sensor로부터의

아날로그 디지털 아날로그

A/D Digital Signal D/A

자연계의 대표적 디지털 시스템

■ 응용 분야에 따른 A/D 변환기 사양 (예) :

Digital Audio 16 44.1 KHz

DVD 8-9 104 MHz

High energy physics MRI

QAM/QPSK Video digitizing Digital oscilloscope

1 40 80 120 160 200 500 1600

[’04] [’03] [’08][’10] [’08]

[’03] [’09] [’08] [’02] [’02] [’01][’10][’06][’09][’10][’03] [’10] [’10][’08][’10]

[’09] [’03][’03] [’08] [’06][’07]

0.25 1 50 100 150 200 500 1000 2000 10000

■ 기본적인 신호의 표현방법

아날로그 시스템 디지털 시스템 혼성모드 시스템

ARCHITECTURE FUNCTION CIRCUIT DESIGN

PHYSICAL IMPLEMENTATION PATTERN GENERATION

PACKAGING TESTING EVALUATION

I.C. BONDING MEASUREMENTS REDESIGN

- 속도, 해상도, 전력 소모, 면적 등을 적절히 고려하여 설계하여야 고성능

- 증폭기 : 큰 DC 이득을 가지면서 닫힌 루프 구조로 동작하여 단위 이득 대역폭에

- 비교기 : 열린 루프 구조이므로 신호 경로상의 –3dB 폴(pole)의 위치에 의해 속도

INPUT SWITCH PREAMP LATCH

Frequency Domain Analysis

회로도 INT CML

INPUT SWITCH PREAMP LATCH

- 응용 분야. 시스템 사양 및 비용 등을 고려한 제작 공정 결정 및 설계

- 결정된 공정상의 소자 변수를 이용한 시제품 칩 설계 및 레이아웃

- CMOS 공정, BJT 공정, BiCMOS 공정 등 특정 공정으로 제작

- 칩 동작 시 발생하는 열과 외부로부터의 충격에서 칩을 보호함

- 응용 분야, 비용 열 임피던스* (thermal impedance) 칩의 전력소모 등에 의한 패키징 형태 결정

(*여기서 열 임피던스는 패키지가 칩으로부터 열을 발산시킬 수 있는 능력을 의미함)

[ BGA : Ball Grid Array ]

Digital Power Buffer Power

Vin bN-1 bN-2

Vin (t) A/D D/A Vout(t)

For N bit resolution A/D :

DNL = LSBwidth - CODEwidth

Fig.1 Illustration of DNL.

- The deviation of code midpoints from their ideal location.

Fig.2 Illustration of INL. Fig.3 Relationship of DNL and INL.

Fig.4 Illustration of offset error.

- The number of distinct analog levels corresponding

- An N-bit resolution implies that the converter can

- Absolute accuracy (includes the offset, gain and linearity errors)

- Relative accuracy (excludes the offset and gain errors)

Ex) 12-bit accuracy :

Fig.7 A nonmonotonic ADC

- The performance of an ADC can change with time,

A Charge Balancing ADC