CMOS 혼성모드 시스템

설계 및 실습 - ADC
서강대학교 이 승 훈
[참고문헌] “CMOS 아날로그/혼성모드 집적시스템 설계,” 6장, 9장,
이승훈, 김범섭, 송민규, 최중호: 시스마프레스 1999년.
System-
System-on
on-
-a-Chip / ADC OVERVIEW

군사분야 가전/정보분야 통신/SDR분야

의료/영상분야

기계/MEMS 및 자동차분야

컴퓨터/멀티미디어분야

기타 미래의 첨단 정보기술산업의 많은 분야
반도체 IC 없이 가능한 일은 ?
System-
System-on
on-
-a-Chip (SoC) Concept

SoC

• Logic : CPU, DSP

• MEMORY : SRAM,, Flash , ROM,, EPROM,,
FeRAM, MRAM, DRAM
• Analog (FILTERS, ADC, DAC, PLL, SENSOR)
• CMOS RF
• Embedded FPGA
• MEMS
• Optoelectronic Function
Ubiquitous Digital Convergence

Mobiles
Communication MP3, Cellular phone,
MP3 phone
ATM, CDMA PDA, Notebook PC

High Speed Low Power

Consumer Multimedia Fusion
+
IC Card
Card, Lab Top PC
PC, C
Connectivity
ti it Products
Electronic Money +
Mobility “(SoC)”
Low Cost Reliability

Graphics
DTV,, Digital
g Camera,,
Networking
DVD, CMOS Image WLAN
A/D 변환기 (ADC) 및 D/A 변환기 (DAC) 응용 사례

■ 무선 통신 회로

RF 신호 아날로그 디지털

LNA ADC DSP

PA SYN DAC

입출력 : 수 GHz의 RF (Radio Frequency) 신호 LNA : Low Noise Amplifier

PA : Power Amplifier
기 능: SYN : Synthesizer
- RF 수신 신호의 정보를 디지털 신호로 변환 및 처리 DSP : Digital Signal
Processor
- 처리된 디지털 정
정보를
를 RF 신
신호로 변환하여 송신
A/D 변환기 (ADC) 및 D/A 변환기 (DAC) 응용 사례

■ Camcorder 응용 회로 (A/D Interface Circuit : CCD, CIS 등)

CCD IMAGE SENSOR INTERFACE CIRCUIT

CDS AGC ADC DSP DAC

아날로그 신호
디 지 털 신호

기 능 : CCD (Charge-Coupled Devices) Image Sensor로부터의

아날로그 영상 신호를 디지털 신호로 변환
CDS : Correlated Double Sampler
AGC : Automatic Gain Controller
응용 분야 : 캠코더, 디지털 스틸 카메라, 스캐너 등
A/D 및 D/A 변환의 배경 및 필요성

아날로그 디지털 아날로그

A/D Digital Signal D/A

자연계 인간
변환기 Processor 변환기

자연계의 대표적 디지털 시스템

인간이 인식할 수
Computer, CD Player, DVD
모든 신호는 있는 신호는
MODEM, Telephone …
아날로그 (C
(Computer가가 인식할 수 있는 아날로그
언어 사용)

디지털 처리 기술의 장점을 이용하기 위해서는 자연계의 아날로그 입력을 디지털 신호로
변환하는 A/D 변환기와 신호 처리후 디지털 출력을 아날로그 신호로 변환하는 D/A 변환기
등의 interface 회로가 반드시 필요
A/D 변환기 (ADC) 의 응용 분야 및 사양

■ 응용 분야 :
- 개인 휴대용 통신 기기, 고속 디지털 통신망, HDTV, 디지털 캠코더, DVD, LCD
모니터 컬러 스캐너 등 제반 시스템 IC (혹은 비메모리 IC) 응용분야
모니터,
- 최근 상용 전자 제품들의 성능이 크게 향상됨에 따라 고속도, 고해상도 및 특히
저전력, 소면적 A/D 변환기에 대한 요구가 급속히 증가

■ 응용 분야에 따른 A/D 변환기 사양 (예) :

해상도 속 도
응용 분야 (Sampling Frequency)
(bits)

Modem 8 – 10 64 KHz

Digital Audio 16 44.1 KHz

HDTV 통신,
HDTV, 통신 Video 10 – 16 1 – 100 MHz

DVD 8-9 104 MHz

LCD 8 205 MH
MHz
Detailed ADC Applications

High energy physics MRI

16 Instrumentation Multicarrier/Multimode Cellular
Automatic test equipment Spectrum Analysis
Low amplitude signal
communication
Wireless communication Wireless infrastructure
XDSL WCDMA/TD-SCDMA/GSM 802.16d/e
highly integrated communication
14 phased array antenna system
Wi-Max Software Define Radio
Ultrasound Equipment HD Video
bit]

imaging system
CCD imaging
UTION [b

digitization
HDTV
Fax machine Cellular Cable Head-End Receiver
Medical imaging
12 Telecommunications
and digital video
base station
Communication
Digital communication Radar and satellite subsystem
Radar systems
applications receiver
RESOLU

Secure communication
Set-top boxes Digital oscilloscopes Multichannel /Multimode receiver
Test
10 IF and baseband equipment
Battery-powered Instruments
high speed modem, broadband wireless
Broadband communication
communications Cable modem Digital Beam
Scanners communication subsystems
Camcorder CCD Imaging

QAM/QPSK Video digitizing Digital oscilloscope

Gigabit ethernet LCD display systems
8 DIGITAL TV High speed digital
Code conversion for RGB video systems Direct RF downconverter
VIDEO PROCESSING communication Digital read-channel system
flat panel display Gigabit ethernet
Electro-Optics Disk-drive control for DVD SOC

DBS/
VSTAT Receiver Digital receivers
6 WLAN for high-bit-rate
communications

1 40 80 120 160 200 500 1600

SPEED [MSample/s]
Current Status of ADC Development

[’00]
20 JSSC
[’03] [’05][’08] [’03] [’05] [’09]
ISSCC
16
[’04] [’08] [’06] [’07] [’07] CICC
[’04] VLSI Symp.
[’06] [’03] [’04] [’07] [’06] [’06] [’06] [’06] [’06] [’07]
14 AP-ASIC
[’04] [’07] [’01] [’04] [’03] [’08] [’09]
[’04] [’00] [’00] [’08] APCCAS
bit]

[’08]
SGU IC Lab.
Lab
UTION [b

[’08] [’07]
[’06] [’06] [’00][’96] [’07][’08] [’09][’03] [’04] [’09] [’06] [’05] [’09]
12
[’03] [’09] [’96][’08] [’09] [’04] [’07] [’08] [’08] [’07] [’06]

[’08]
09] [[’07]
07][[’09] 07][[’09]
07][[’07]
09][[’07] 09] [[’02]
02] [[’01]
01] [[’04]
04] [[’08]
08] [[’06]
06]
RESOLU

[[’08]
08] [[’08]
08] 06] [[’07]
[[’06] 07] [[’05]
05][[’09] [[’04]
04] [[’07]
07] [[’09]
09] [[’07]
07]
10
[’05] [’03] [’07] [’06] [’07] [’09] [’09] [’04] [’07] [’08] [’03] [’05] [’03] [’07][’07] [’06] [’09]
[’09]

[’08]
[’07] [’07] [’01] [’00] [’04] [’04] [’01] [’02][’05] [’07] [[’04]] [[’02]]
8
[’07] [’00] [’05] [’03] [’04] [’04]
[’03] [’02] [’07] [’09]

[’03] [’09] [’08] [’02] [’02] [’01] [’06] [’03] [’03] [’09] [’08]
6
[’04] [’06] [’09][’08] [’09]
[’08] [’08] [’06] [’07]

[’08] [’09] [’03] [’03][’08] [’06] [’07]

4

0.25 1 50 100 150 200 500 1000 2000 5000

SPEED [MSample/s]
아날로그 신호와 디지털 신호 특성 비교

■ 기본적인 신호의 표현방법

아날로그 신호 샘플링된 아날로그 신호 디지털 신호
1 1 1
V(t) V(t) 1 1 0
1 0 1
1 0 0
0 1 1
t t 0 1 0
0 0 1
0 0 0
연속적 (Continuous) 이산적 (Discrete)

아날로그 시
■ 아날 시스템과 시스템
템과 디지털 시 혼성모드 시
템 및 혼성 시스템
템

아날로그 시스템 디지털 시스템 혼성모드 시스템

프로그램화
신호의 고밀도 집적 아날로그 시스템과
필터링, 증폭 등 설계 용이 디지털 시스템을
아날로그 경제적 하나의 칩으로
신호처리 높은 정밀도 구현
A/D 변환기 (Analog IC) 설계 및 제작 과정

ARCHITECTURE FUNCTION CIRCUIT DESIGN

SCHEMATIC AND SIMULATION
FLASH
BEHAVIORAL FREQUENCY AND
MULTI-STEP SIMULATION
PIPELINED TIME DOMAIN
YIELD ANALYSIS

FABRICATION LAYOUT

PHYSICAL IMPLEMENTATION PATTERN GENERATION

OF INTEGRATED CIRCUITS OF INTEGRATED CIRCUITS

PACKAGING TESTING EVALUATION

I.C. BONDING MEASUREMENTS REDESIGN

ON LEAD FRAME AND VERIFICATION OR NOT ?
A/D 변환기의 기본 설계 예제

Vin
+Vref

N-bit
디코더 디지털 출력
(Binary Code)

2N-1
-Vref
V f 비교기

비교기 출력 3-bit
예) 3-bit (Thermometer 디지털 출력
+Vref Code) (Binary Code)
Fl h A/D 변환기
Flash
1111111 111
0111111 110
Vin 0011111 101 출력 = 101
0001111 100
0000111 011
0000011 010
0000001 001
0000000 000
-Vref
A/D 변환기 기본 회로 이해 (비교기 : Comparator)

g 비교기의 정의 :
q 비교기는 작은 아날로그 입력 신호를 감지, 이를 증폭하여 디지털 신호를 출력하는
회로

g 비교기의 용도 :

q A/D 변환기, 데이타 전송기, 스위칭 파워 정류기, 메모리 감지 증폭기 등

g 비교기의 성능 척도 :

q 속도, 해상도, 전력 소모, 면적 등을 적절히 고려하여 설계하여야 고성능

g 증폭기와의 차이점 :

q 증폭기 : 큰 DC 이득을 가지면서 닫힌 루프 구조로 동작하여 단위 이득 대역폭에

의해 속도 결정

q 비교기 : 열린 루프 구조이므로 신호 경로상의 –3dB

3dB 폴(pole)의 위치에 의해 속도
결정
비교기의 동작 원리

g Q2 HIGH :
CML
q기준 전압 샘플링
Q2
C1
Q2
REFT
AMP LATCH g Q1 HIGH :
REFC
Q2
C2 q입력 전압 샘플링 (INT, INC)
Q2
qAMP 출력단에 전압차 증폭
CLOCK
[(INT-INC)-(REFT-REFC)] * Amp Gain
CML
q래치 출력단 리셋

C1
Q1
INT
AMP LATCH
INC g CLOCK HIGH :
Q1
C2
q래치의 정궤환 동작으로 래치
CLOCK 출력 단에 디지털 신호 출력
q버퍼단을 통해 최종 디지털
신호 출력
비교기의 회로도

VDD

INT CML TN TP

RESET

C1
REFT
REFC
C2
LATCH
FBIAS
INC CML
VSS
VDD

OUTC OUTT

VSS

INPUT SWITCH PREAMP LATCH

HSPICE 시뮬레이션 (Simulation)

Frequency Domain Analysis

Wave Symbol
A0:vdb( tn,tp ) 20

Voltage [dB]
10

0
1K 100K 10M 1G
Frequency [log]
Time Domain Analysis : Input of Comparator
Wave Symbol 70m
A1:v( int )
A1:v( inc )
[lin]

A1:v( reft )
Voltage [

A1:v( refc ) 0

-70m
50n 60
60n 70
70n
Time [lin]
Time Domain Analysis : Output of Comparator
Wave Symbol
1.5
A1:v( outt )
A1:v( outc )
n]
Voltage [lin

-1.5
1.5
50n 60n 70n
Time [lin]
비교기의 회로도와 레이아웃 (Layout)

회로도 INT CML

TN TP

C1 RESET
REFT
REFC
C2
LATCH
FBIAS
INC CML VSS
VDD

OUTC OUTT
레이아웃 (CADENCE TOOL 사용)
VSS

INPUT SWITCH PREAMP LATCH

A/D Converter 시제품 (Prototype) 제작 및 Packaging

■ 시제품 제작

- 응용 분야. 시스템 사양 및 비용 등을 고려한 제작 공정 결정 및 설계

- 결정된 공정상의 소자 변수를 이용한 시제품 칩 설계 및 레이아웃

- CMOS 공정, BJT 공정, BiCMOS 공정 등 특정 공정으로 제작

■ Packaging

- 칩 동작 시 발생하는 열과 외부로부터의 충격에서 칩을 보호함

- 응용 분야, 비용 열 임피던스* (thermal impedance) 칩의 전력소모 등에 의한 패키징 형태 결정

분야 비용,

(*여기서 열 임피던스는 패키지가 칩으로부터 열을 발산시킬 수 있는 능력을 의미함)

Packaging 기법 및 종류

[ DIP : Dual
D l IIn liline P
Package
k ] [ QFP : Quad Flat Package ]

[ BGA : Ball Grid Array ]

[ CHIP ]
[ PGA : Pin Grid Array ]
시제품 A/D 변환기 측정 보드

Digital Power Buffer Power

g Input
Analog

Digital Outputs
O
( PC 또는 디지털측정
시스템 )
DUT D BUFFER
D.

Analog Power
시제품 성능 DEMO 및 측정 방법

D.S.P.
Processor

Data Acquisition PC
D.U.T. Screen
Board

Developed
Programs
(DNL, INL, FFT, etc.)
Clock, Signal,
Power Supply
ADC DESIGN BACKGROUND [1/9]
A. Transfer Function
ENCODING

bN-1 D
Vin A/D 11

b0 10 Mid-Tread
Analog Input Digital Output 01

00 A
1/4 2/4 3/4 4/4

Vin bN-1 bN-2

N2 b0 D
Dout = = + + 11
VFS 2 22 2N
10 Mid-Rise
ΔVo = 1 LSB = VFS / 2N
01

00 A
1/4 2/4 3/4 4/4
ADC DESIGN BACKGROUND [2/9]
B. Quantization Error
bN-1

Vin (t) A/D D/A Vout(t)

b0

+ -
∑
Quantization Error !!
Vin (t) - Vout(t)

Vin(t) Vout(t)

σE2 = ΔVo2
=
VFS2
12 (12)( 22N)
t t
σ2 X
SNR Δ
σ2
=
E
Vin (t) - Vout(t)
and SNR increase by factor
0 of 2 for each bit or 6dB/bit
t
ADC DESIGN BACKGROUND [3/9]
C. Finite Conversion Time

Analog
voltage VA(t) Aperture error

ΔVX ΔVX
For sinusoidal signal with A = VFS / 2

For N bit resolution A/D :

Δt
ΔVX < ΔVO = VFS / 2 N+1 = A/ 2N
Aperture time t
ΔVX
Example : Δt =
2πfA
VA(t) = A
Asin2π
i 2 ft ΔVX
ΔVX = A / 2N f
dVA(t) 1 1
= 2Aπf ∴ Δt =
dt 2N+1 πff
MAX
∴ Need sample & hold
∴ Aperture error ΔVX = 2πfAΔt for high speed
ADC DESIGN BACKGROUND [4/9]
D. Terminologies
① DNL (Differential nonlinearity)
- How uniform the transfer function step size are.

DNL = LSBwidth - CODEwidth

V(x) - V(x+1)
=1-
LSB
where V(x) and V(x+1) are the two bounding transition levels of output code x.

Fig.1 Illustration of DNL.

ADC DESIGN BACKGROUND [5/9]
② INL (Integral nonlinearity)

- The deviation of code midpoints from their ideal location.

- The ideal code midpoint location :
Straight line between the first and last code midpoints.

Fig.2 Illustration of INL. Fig.3 Relationship of DNL and INL.

ADC DESIGN BACKGROUND [6/9]
③ Offset error
- The deviation from the ideal location of the lowest
transition level on the ADC transfer function.
Voff = Vz - Videal
where Vz = first transition level voltage
Videal = 0.5 LSB

Fig.4 Illustration of offset error.

ADC DESIGN BACKGROUND [7/9]
④ Gain error
- The difference in the slope of the actual and the ideal code center lines.

Fig 5 Illustration of
Fig.5
gain error.
⑤ Full scale

Fig.6 Illustration of
full scale range.
ADC DESIGN BACKGROUND [8/9]
⑥ Resolution

- The number of distinct analog levels corresponding

to the different digital
g words.

- An N-bit resolution implies that the converter can

resolve 2N distinct analog levels.

⑦ Accuracy

- Absolute accuracy (includes the offset, gain and linearity errors)

The difference between the expected and actual
transfer responses
responses.

- Relative accuracy (excludes the offset and gain errors)

The maximum integral nonlinearity error
error.

Ex) 12-bit accuracy :

Error of converter < Full scale
212
ADC DESIGN BACKGROUND [9/9]
⑧ Monotonicity

- The digital code is continuously increasing as

the analog input is continuously increased.
- Critical in control applications.

Fig.7 A nonmonotonic ADC

transfer function.
⑨ Stability

- The performance of an ADC can change with time,

temperature, and supply voltage.
- It is important to know whether the converter is monotonic
over its full temperature and supply voltage range.
ADC ARCHITECTURES (1/20)

A Charge Balancing ADC

A.

Vref -Vin
Slope: Slope:
RC RC

Vin
R Detect 0
τ
Vin - Comparator
R + 0V
Voltage-to-Frequency
τ τ

Pulse
T
DN-1
Counter
-Vref D0 Vin X T = Vref X τ
τ τ RC RC

1 Vin 1
T = f = Vref X τ
ADC ARCHITECTURES (2/20)

B Slope Type ADC

B.
C
① Dual slope
R
Vin - Vo
+
-Vref

Clock Counter

Vo slope 0 < t < t1 ;

Vin Vref
RC RC dVo = Vin
dt RC

t t1 < t < t2 ;
t1 t1 + t2 dVo = Vref
dt RC
dual slope

Vin Vref ∴ Vin = Vref t2 Measured in digital

RC t1 =
RC t2 t1

Used for slow panelmeter or multimeter

ADC ARCHITECTURES (3/20)

② Triple
T i l slope
l → NNo op amp usedd
( comparator only )

Vin
Vc
Vref
GND
I C
C
Comparator
t

slope : I -VA : IVAI > IVOSI

C
VC
Vref
Vin

0 t
-VA VTH
t1 t2 t3 Comparator
threshold voltage
~ - VA ( < 0 )
ADC ARCHITECTURES (4/20)

dVc = I ; must be kept constant

VC dt C
Vref ( cascode current source )
Vin
t1 = Vreff - VTH ; t2 = Vin
i - VTH
0 t dV/dt dV/dt
-VA VTH
t3 = - VTH
t1 t2 t3 Comparator dV/dt
threshold voltage
~ - VA ( < 0 ) Vin
=
t2 - t3 Two digital subtracts
Vref t1 - t3 one divide
Current source ;
CΔV = I X t
Switch C
10V I
C = 2.5 X 10
= 3
4ms

Imin = 10 nA
A
I
C = 10-8 / 2.5X103
≅ 4 pF
-Vcc
ADC ARCHITECTURES (5/20)
③ Tracking A/D (servo A/D) → very slow in msec

Vin D/A
Track
Digital
up
Counter
down

Clock (very fast)

C. Successive Approximation ADC

f( )
f(x) f( ) = 0
f(x)

S/H D/A
Vin
digital ②④ ①
or
out 11
③ 2
1 x
T/H
SAR
ADC ARCHITECTURES (6/20)

VA
Vref
3
Vref
4
1 5 Vreff
1 8
4 8
Vin
1 9 Vref
Vref
2 16

t
1 0 0 1
Continue until you reach LSB

Vin Need not be linear “C”

VC = Vin - Voff
VA VC VA to VC match
ADC ARCHITECTURES (7/20)

D Weighted-C
D. Weighted C SAR ADC

Initialization
① For unipolar inputs
VX

i. Initialization Top : VX = VOS 2N-1C 2C C C Cp

Bottom : Vin
ii. Switch bottom to GND VX = VOS - Vin
iii. Switch bottom of 2N-1C to Vref Total C = 2NC
Vin
VOS VOS - Vin Vref
2NC VX

2N-1C Vref Vin

iv ΔVX = Vref
iv. = Vref to GND Vref Vref
2NC 2 VOS - Vin + VOS - Vin + +
2 2 8
check comp output go ahead Vref
VOS
4
+ back to ground
t
C Vref Vref MSB to Vref Vref
v. LSB C to Vref ΔVX = Vref = 2
N
2 C 2N Vref 8 16

VOS-Vin 1 0 0 1
S/H MSB LSB
ADC ARCHITECTURES (8/20)

■ Advantages

- Insensitive to CP since VX start from VOS ends at VOS

- Only comparator required

- 10bit capacitor matching used

- 100 kHz
kH ~ 1 MHz
MH voice
i didigitizer
ii good
d
telephone ch
ADC ARCHITECTURES (9/20)

② For bipolar (±) inputs ; - Vref ≤ Vin ≤ Vref

SIGN MSB

C C C
2 4

i. Sign bit samples Vref

ii. Other bits sample Vin
Vref Vin
iii Parasitic at VX is negligible
iii.
(a) Positive input ; 0 ≤ Vin ≤ Vref

VX
SIGN 1 0 0 1

VOS
0 t

Vref Vref Vref Vref

4 8 16 32

VOS - Vin sign bit not

not-changed
changed
2
∴(digital 0)
ADC ARCHITECTURES (10/20)
Vref ≤ Vin ≤ 0
(b) Negative input ; -V
Return SIGN bit to GND!
VX
VOS - Vin
2

Vref
2
VOS
0 t
Vref Vref
4 8

SIGN MSB
“0” “1”

Two’s complement for negative number

C ( a little large ) C ( a little small )

D D

A A
Vref Vref

Gain Missing code!

error Gain error
ADC ARCHITECTURES (11/20)

E R+C or C+R ADC

E.

Vref LSB
MSB
R+C
ADC

C+R
ADC
Vref

MSB

LSB
ADC ARCHITECTURES (12/20)

F High-Speed
F. High Speed ADC

① Parallel Processing : Time Interleaved

8 Bit

Vin 8 Bit Dig out

8 Bit

N Bit (8) Problems: Clock skew

M way Interleaved (4) Feedthrough
M2Nunits
it off C (1024) VOS matching
t hi
M comparators (4) DAC gain error

’93. April. JSSC

ADC ARCHITECTURES (13/20)

② Flash ADC : Fastest in all of the current architectures

Vref

N Bit (8)
0
2N R (256R)
0 (2N-1) comp. (255)
complete
1 conversion (1 cycle)
1
cf 10 bit → 200 MHz
cf.
1 2W ECL

Vin
ADC ARCHITECTURES (14/20)

③ Pipelined ADC

×2 2
2Vin-Vref >0
Vin + +
Σ Σ
- -
S/H Vref S/H MSB 1
MSB=1
Vref

0 1 Vref Vin
GND 2

Vref
ADC ARCHITECTURES (15/20)

(a) Reference Restoring Method

① 2Vin - Vref > 0 Bit = 1

Next stage samples 2Vin - Vref
② 2Vin - Vref < 0 Bit = 0
Next stage samples 2Vin
Vres = Residual Voltage = 2Vin - Vref or 2Vin

(b) Reference Non-Restoring Algorithm

① 2Vin - Vref > 0 Bit = 1

Next stage samples 2Vin-Vref
② 2Vin - Vref < 0 Bit = 0
N
Next S
Stage S
Samples
l 2Vi2Vin - Vref
V f
Use -Vref in the next stage
2(2Vin) - Vref = 2(2Vin - Vref) - ( -Vref)
= 4Vin - Vref
ADC ARCHITECTURES (16/20)

(c) MOS Implementation

C C

2C 2C
Vin - -
+ + 2Vin-V
Vref
Vref
C C

Sampling Amplifying

① Charge Injection ③ Required OP Finite Gain

② C Mismatch 10 Bits A0 > 1000
14 Bits A0 > 16000
ADC ARCHITECTURES (17/20)

(d) Better MOS implementation (only 2C used)

C
-
+ -
Vin Vin +
+ -
C

Vin
- +
Vin
+ -
+ Vref -
2Vin Vref
- Vref +
ADC ARCHITECTURES (18/20)

④ Compromise between speed vs. size (chip) power

⇒ Two-Step Flash

10 bit
25
5 bit
bits

Vin
Flash Flash
5 bit DAC 5 bit
S/H
ADC - +
ADC

MSB LSB

Residual Voltage
ADC ARCHITECTURES (19/20)

Digital
① 2 Decision
Q ② Differential Amp
① ③ D/A Delay
after
A/D
Residual
Vin
② ㉧ Vref • N bits
• 2N/2 R
after D/A
• (2N/2 - 1) comp
• 1 op amp
• two cycles
l

③
ADC ARCHITECTURES (20/20)

G Smallest (Area Effective) ADC (≡ algorithmic,

G. algorithmic cyclic or pipelined ADC)

① Sampled inverter
C2 Φ
Φ

Vin C1 Vin
Vin
- GND
GND +
Vin
Vo GND

② D/A converter Φ1
Φ2

Vx C C C
Vref - C (a) Start from LSB
-
GND +
+ (b) S
Sample
l Vref , Sample
S l GND
Vy(out)
C/2
(→ 2C for ADC) Bit = “1” Bit = “0”
( Vin for ADC )
Vz
HIGH-
HIGH-RESOLUTION ADC [1/21]

A. Oversampled ΔΣ ADC
DIGITAL
Fs ENCODING
ANTI-ALIAS
LP FILTER

HIGH
ANALOG DIGITAL RESOLUTION
INUPUT MODULATOR PROCESSOR DIGITAL
(DECIMATOR) 16 OUTPUT

ANALOG DIGITAL

Oversampling A/D Converter System

{ 16 bit SNR over audio band (20 kHz)

16-bit
{ High tolerance to analog circuit imperfections
{ Sample low-order prefilter
{ Digital decimation filter (LPF)
HIGH-
HIGH-RESOLUTION ADC [2/21]

① First order interpolative modulator (Delta sigma)

1-bit
ADC
+ -
X(t) + Y(t)
Analog +
Input - Digital
Output

1-bit
DAC

E(z)

X(z)
+ + Y(z)
+ + Z-1 +
- + ADC

DAC

Linearized Model
HIGH-
HIGH-RESOLUTION ADC [3/21]

② Second order interpolative modulator

+ + 1 bit
1-bit
X(t)
() + + Vi(z) + (1-z-1)2 E(z)
Input ADC
- - Vo(z) =
1+ (1-z-1) + (1-z-1)2
1-bit
1 bit
DAC (z= jωT)

Y(t)
Output

Quantization Noise Response

From Linearized Model
HIGH-
HIGH-RESOLUTION ADC [4/21]

③ Linearized model of N-th order interpolative modulator

E(z)

+ W(z)
X(z) + H(z) + z-1 Y(z)
-
1-bit ADC

1-bit DAC

Y(z) = Hx(z)X(z) + HE(z)E(z)

Σ Ai (z-1)N-i
N

i=0
HX(z) =
z[(z-1)N - Σ Bi(z-1)N-i ] + Σ Ai(z-1)N-i
N N
i=1 i=0

Σ Bi (z-1)N-i
(z-1)N - N

HE(z) = i=1

z[(z-1)N - Σ Bi(z-1)N-i ] + Σ Ai(z-1)N-i

N N
i=1 i=1

E(z) (jΩ)N
YX(z) ≈ X(z) +
AN
HIGH-
HIGH-RESOLUTION ADC [5/21]

Fourth Order Loop

Quantization Noise Response
HIGH-
HIGH-RESOLUTION ADC [6/21]

B. Calibrated SAR-type ADC

10b Capacitor Main DAC

MSB LSB

8 Bit Resistor sub DAC

Vref

Measure C mismatch error using Resistor sub DAC. ⇒ Digitize !

HIGH-
HIGH-RESOLUTION ADC [7/21]

① Sample 0V ;
C1 C2

Vref

② Swapp Vref ; Vx
C1 C2

Vref

C2 > C1

① Complexity
C1 = C2
t
② Need long calibration cycle due to noise
C2 < C1 ③ Slow 15bit 8kHz
12bit 80kHz
Digitize this error to compensate !
HIGH-
HIGH-RESOLUTION ADC [8/21]

C. High-Resolution Algorithmic ADC

① Ratio Independent ;
t=0

Must be diff. !!
C2
- C1 - Sample & integrate
C1 Vo = 2 Vin Vin twice !
+ C2
Vin
- Swap C1 & C2 2Vini

C1

Vref - C1
Vo = 2Vin - Vref C2
C2 +
HIGH-
HIGH-RESOLUTION ADC [9/21]

* Error sources
- Switch feedthrough error
- kT/C error
- Finite gain error
- Slow ; 10Bit ~ 12Bit 8kHz

② Reference Recycling ;
Let Vref go through the same error as Vin !
Vo = 2 (1+α)Vin - (1+ α)Vref
= (1+ α)(2Vin
i - Vreff)

- No finite gain error

- Same as Ratio Independent
- Slow ; 12Bit 8kHz
HIGH-
HIGH-RESOLUTION ADC [10/21]

D. Capacitor Error-Averaged ADC

- Equal capacitors are used for the X2 function (C1=C2, but mismatched).

C1
Sampling

Vin C2

C2
Amplifying
C1

Vref 2Vin - Vref + Δ

Error
HIGH-
HIGH-RESOLUTION ADC [11/21]

Averaging C1

C2

Vref 2Vin - Vref - Δ

Error

- Capacitor errors Δ, -Δ are averaged using a separated amplifier to obtain

12bits at 1 MHz
MHz. ( possibly up to 14 bits at 3 MHz )
HIGH-
HIGH-RESOLUTION ADC [12/21]

* Error-Averaging Amplifier

A lif i
Amplifying 2C

C
2Vin - Vref + Δ
C

2C

2C
Averaging

C 2Vin - Vref + Δ - Δ
2Vin - Vref - Δ
C = 2Vin - Vref

2C

- Total input voltage change is (2Vin - Vref - Δ ) - (2Vin - Vref + Δ ) = -2Δ

HIGH-
HIGH-RESOLUTION ADC [13/21]

■ Advantage : - Can be done in fewer clock cycles than the ratio-independent

or reference-recycling methods

- Can be used with a correlated double sampling technique

■ Disadvantage : - Extra amplifier for error averaging

- Too Complex
HIGH-
HIGH-RESOLUTION ADC [14/21]

E. Digital-Domain Self-Calibration ADC

DIGITAL IDEAL IDEAL

DIGITAL
OUTPUT
OUTPUT

ANALOG ANALOG
INPUT INPUT

CODE
ERROR

COARSE
DIGITAL
OUTPUT
HIGH-
HIGH-RESOLUTION ADC [15/21]

- Feedthrough Measurement

VO = VOS
2NC 2C C 2C
Vref
1 0 0
INPUT = Dj

2NC 2C C 2C
Vref
1 0 0
VO = VFT
INPUT = Dj
HIGH-
HIGH-RESOLUTION ADC [16/21]

- Code-Error Measurement

VO = VOS
2NC 2C C 2C
Vref
1 0 0
INPUT = Dj

2NC 2C C 2C
Vref Vref
1 0 1
INPUT = Dj+1 ( = Dj+1 ) VO = -1/2 Vref + VFT + Vε(Dj+1)
HIGH-
HIGH-RESOLUTION ADC [17/21]

- Digital Calibration and Correction

2 HOLD DIGITAL
(N+1)
(N 1)
CALIBRATION
BITS 2N BITS
1 (N+1)-BIT (N+1)-BIT LOGIC
MDAC FLASH DIGITAL
CORRECTION
LOGIC
(N+1) BITS
3

CORRECTION

2N-1 N+1 N N-1 1 0

COARSE BITS

FINE BITS

CALIBRATION CODE ERRORS

2N-BIT
2N BIT OUTPUT
HIGH-
HIGH-RESOLUTION ADC [18/21]

Recycling
calibrated ADC
HIGH-
HIGH-RESOLUTION ADC [19/21]

Differential
Diff ti l
Capacitor-array MDAC
HIGH-
HIGH-RESOLUTION ADC [20/21]

Before calibration After calibration

HIGH-
HIGH-RESOLUTION ADC [21/21]

Beforecalibration
Before calibration Aftercalibration
After calibration
HIGH-
HIGH-SPEED ADC DESIGN EXAMPLE

A 12b 10MHz 250mW

DIGITALLY CALIBRATED STAND
STAND-ALONE
ALONE
CMOS A/D CONVERTER

[ISSCC 1996 Presented]

ELECTRONIC CAMERA FRONT
FRONT-
-END

BLOCK DIAGRAM
OF FRONT-END

DIGITAL VIDEO
DAC OUT1
CCD CDS AGC ADC CAMERA
SIGNAL VIDEO
PROCESSING DAC OUT1

CCD : Charge-Coupled Device

CDS : Correlated Double Sampling
AGC : Automatic Gain Control
ADC : Analog-to-Digital Converter
DAC : Digital-to-Analog Converter
DESIGN OF A/D CONVERTER

ADC BLOCK

DIGITAL DAC
CAMERA
AGC A/D CONVERTER
SIGNAL
PROCESSING DAC

* Design Issues :
- Speed, Resolution, Power Dissipation
- Chip Area
- Yield
- Cycle Time
- What Process (Bipolar, MOS)
- etc.
DESIGN EXAMPLE OF A/D CONVERTER

DESIGN
EXAMPLE

DIGITAL DAC
CAMERA
AGC A/D CONVERTER
SIGNAL
PROCESSING DAC

Example Target Specifications :

12-Bit,
12 Bit 10
10-MHz,
MH 250
250mW,
W and d more
0.8 um Full CMOS A/D Converter
(’96 ISSCC published)
A 12b 10MHz 250mW A/D CONVERTER
FLASH A/D CONVERTER SCHEMATIC

FLASH ADC
TOP SCHEMATIC
FLASH ADC TIMING

Q2 Q1 Q2 Q1

PREAMP SAMPLE REF AMPLIFY

PREAMP_LATCH PRECHARGE LATCH
F1_LATCH TRACK LATCH

ROM RESET ENCODING

Q1 Q1P

Q2 Q2P
AN EXAMPLE OF FLASH ADC SPEC

TECHNOLOGY 0.8 um DOUBLE-POLY DOUBLE-METAL CMOS

REFERENCE 2 Vp-p

RESOLUTION 4 BITS

ACCURACY 5 BITS ( 2/16 = 125 mV ) + SAFETY MARGIN

SPEED 100 ns / 2 / 2 = 25 ns ?

POWER, AREA 5V, << 0.5 mW, REQUIRED

ARCHITECTURE PREAMP + LATCH

TIMING Q1 AND Q2 (NONOVERLAPPTED)

TOLERANCE
WITH TEMP, SUPPLY, SIMULATE AND CHECK
AND MODEL PARAMETER
COMP1N
PRE-
PRE-AMP

gm5
DC gain =
gm1-gm2
1
f-3dB =
2π RTCT

RT = 1/(g
1/( m1-gm2)

CT = Cdb1 + Cgs1 + Cdb2

+ Cgs3 + 2Cgd2 + 2Cgd3
+ Cgd5 + Cdb5

P
Power = Vsupply * Ibias
COMP1P
F1_BIAS
F1_NAND
F1_LATCH
LATCH_1
F1_ROM
Comparator Operation Principle

제안된 비교기의 동작 원리
CML1

C1
• Q2 HIGH
- 기준 전압 샘플링
REFT
(REFT, REFC)
amp
a p latch
atc
REFC • Q1 HIGH
C2 - 입력 전압 샘플링
CML1 C
LATCH (INP INN)
(INP,
- 래치 입력단에 차이 전압 생성
(INP-INN)-(REFT-REFC)
C1
- 래치의 출력단 LN과 LP는 VDD로 충전
INP
amp latch • LATCH HIGH
INN - 래치의 정궤환 동작으로 래치 출력단에
C2 디지털 신호 출력
LATCH - 버퍼단을 통해 최종 디지털 신
신호 출력
PRE-
PRE-AMP OUTPUT (AC ANALYSIS)
WAVEFORM OF PRE-
PRE-AMP INPUT (1)
WAVEFORM OF PRE-
PRE-AMP INPUT (2)
WAVEFORM OF PRE-
PRE-AMP OUTPUT (1)
WAVEFORM OF PRE-
PRE-AMP OUTPUT (2)
WAVEFORM OF FLASH LATCH
WAVEFORM OF FLASH OUTPUT
FLOORPLANNING

ANALOG DIGITAL
FERENCE

W ARRAY

F _ LATCH
F _ NAND
REAMP

LATCH

ROM
PR
S.W
REF

L
■ LINE LOCATIONS AND WIDTHS
- POWER LINES
- CLOCK LINES
- INPUTS AND OUTPUTS
■ WHERE IS A BIAS BLOCK ?
LAYOUT PRINCIPLES

1 Good isolation of analog and digital circuit blocks

1.
2. Isolation of analog and digital power supplies
3. Minimized line crossings of analog and digital signals
4. Use of n-well (or p-well) for low substrate noise coupling
5. Good analog and digital pad grouping
p y
6. Employment of separate
p current mirrors and bias circuits
7. Many well and subst contacts required
8. Fully differential layout techniques
9 Minimization of proximity problems
9.
10. Isolation of clock generators from other blocks
11. Consideration of mismatch effects
12. Use of metal2 rather than metal1 for power lines
13. Multiple pads for inputs
14. At least two vias and contacts for high yield and reliability
15. Prevention of layers on well edges
16. Modular approach for easy verification of functional blocks
17 Don’t mix pmos and nmos transistors
17.
18. More…..
FLASH LAYOUT
CHIP PHOTO
MORE WORK TO DO

g Check design target specifications in details

g Consideration
C id i process variations
i i ffor d
design
i and
d llayout
- Safety margin, yield, application fields, etc.
- Fast, nominal, slow model parameters (+- 30%)
- Extra devices for minimum design and layout cost
- Multiple pads and test pins for isolated problems

g Add test circuits for worst-case conditions

g Set up performance evaluation kits in parallel with design

g More ... SHOULD BE FUNCTIONAL, FIRST !!!

High-Speed High-
High- High-Resolution
Low--Power CMOS ADCs
Low
August
g 2009

SEUNG--HOON LEE
SEUNG

D t off El
Dept. Electronic
t i Engineering
E i i
SOGANG UNIVERSITY,, KOREA
System-
System-on
on-
-a-Chip(SoC) Applications

군사분야 가전/정보분야 통신/SDR분야

의료/영상분야

기계/MEMS 및 자동차분야

컴퓨터/멀티미디어분야

기타 미래의 첨단 정보기술산업의 많은 분야
반도체 IC 없이 가능한 일은 ?
System R&D with Digital Convergence

Mobiles
Communication MP3, Cellular phone,
MP3 phone
ATM, CDMA PDA, Notebook PC

High Speed Low Power

Consumer Multimedia Fusion
+
IC Card
Card, Lab Top PC
PC, C
Connectivity
ti it Products
Electronic Money +
Mobility “(SoC)”
Low Cost Reliability

Graphics
DTV,, Digital
g Camera,,
Networking
DVD, CMOS Image WLAN
Contents

„ Recent Trend of ADC IP’s

->
> Hi
High
h Speed
S d and
d Low
L Power
P
-> High Resolution and Small Area
-> How to trade off various conflicts ?

„ Case1
C 1 - A Calibration-Free
C lib ti F 14b 70MS/s
70MS/ CMOS ADC

„ Case2 - A 10b 25MS/s 4.8mW

4 8mW 0.13um
0 13um CMOS ADC

„ Case3 - A Re
Re-Configurable
Configurable 10b, 10MS/s - 100MS/s,
0.5V - 1.2V, Low-Power, 0.13um CMOS ADC
Low-
Low-Power ADC (Circuit Sharing) [1]

VDD
Sampling C1 Amplifying C3
Bi+1*VREF
VRES(n-1) 1st stage 1st stage
C2 1 2nd
stage 2
VSS CC C4

VRES(n+1)
1 + 2

S1 ON
VIP+ VIP- (Phase 1) VIPC
s2 s2
VIPC VIPC VIP+ VIP-
s1 s1 VIN+ - VO+ VIN-
s2 - VO+ s2 - VO+
VINC VINC
s1 s1 S2 ON VINC
VIN VIN (Ph
(Phase 2)
+ -

 The 2nd stage opamp shared by opposite phase stages

 The 1st stage opamps merged with a single bias branch
[[1]] S. T. Ryu,
y B. S. Song,g and K. Bacrania, “A 10-bit 50-MS/s Pipelined
p ADC with opamp
p p current reuse,” IEEE J.
Solid-State Circuits, vol. 42, pp. 475-485, March 2007. [
Pow. (18mW), Area (1.43mm ), DNL/INL (0.2/0.4), SNDR (56.9dB) ]
2
Low-
Low-Power ADC (CBSC & ZCBC) [2]

* CBSC : Comparator-Based Switched-Capacitor

VO[n]
C1

C2 VX t
CL
VX IX VCM
VCM + VO - VX
VCM
VCM O t
Improved
* ZCBC : Zero Crossing Based Circuit
C1

C2
CL
VX ZCD IX
VCM + VO -
VCM
VCM

 Opamp replaced with a comparator(ZCD) and a current source

 Comparator(ZCD) detects virtual ground condition and turns off current source

[2] L. Brooks and H. S. Lee, “A zero-crossing-based 8b 200MS/s pipelined ADC,” in ISSCC Dig. Tech. Papers,
Feb. 2007, pp. 460-461. [ Pow. (8.5mW), Area (0.05mm2), DNL/INL (0.75/1.0) ]
Low-
Low-Power ADC (Switched Bias Power Reduction) [3]

VDD VDD
M4 M5
MP1 MP2 MP3 MP4 MP5 MP6
30%Ⅰ
reduced 2
M6 M7 BIAS1
IN IN OUT 70 : 30
BIAS2
Q1
M1 M2 + +
M8 M9 IREF
BIAS4
100%Ⅰ
reduced M10 M11 1
M3 MN1 MN2 MN3 MN4

VSS VSS
Amplifying
Current Reduction in Sampling Sequence Delay Cell

 Sampling - Currents reduced by 30% with BIAS1 & 2 and by 100% with BIAS4
 Holding - Currents resumed with switching sequence;
first BIAS4, then BIAS1 and BIAS2
- Timing delay needed by MP3 and MN3

[3] Y. J. Cho, et al., “A 10b 25MS/s 4.8mW 0.13um CMOS ADC for digital multimedia broadcasting
applications,” in Proc. CICC, Sept. 2006, pp. 497-500.
[ Pow. (4.8mW), Area (0.8mm2), DNL/INL (0.42/0.91), SNDR/SFDR (56dB/65dB) ]
Low-
Low-Power ADC (SAR ADC
ADC)) [4]

Ref.
1X X
ADC Dr

Φr((599.4KHz))
CN-1 C1 C0 C0 CN-1,d CN-4,d
ADC1 ADF1 dN-1 d1 d0
D1 D
SAR Logic
Φ1(60MHz) +VR
Vin
i
T/H 1X -VR
Vin Dynamic Threshold
Φ Comparator
(600MHz) ADC10 Vin n−1 Ci V
ADF10 =∑ (2di − 1) + OS + QN
Φ1 VR i=0 Ctot VR
Φ`
DLL Φ10(60MHz)
(60MHz) Φ10 Software (ADF : Adaptive Digital Filter)
(QN : Quantization Noise)

 Power-efficient SAR ADCs based time-interleaved architecture

 Calibration techniques required to solve the channel mismatch problem
between individual SAR ADCs

[4] W. Liu, “A 600MS/s 30mW 0.13um CMOS ADC Array Achieving Over 60dB SFDR with Adaptive Digital
Equalization,” in ISSCC Dig. Tech. Papers, Feb. 2009, pp. 82-83.
[ Pow. (30mW), Area (1.1mm2), DNL/INL (0.23/0.3), SNDR/SFDR (46.7dB/65.2dB) ]
Low-
Low-Power ADC (Asynchronous Binary-
Binary-Search ADC) [5]

Vin

Comp (6/8) Comp (3II7/8)

OR
Comp (4/8)

Comp
p (2/8)
( ) Comp
p (1II5/8)
( )
Vclk

OR

if Vin > 4 5&7 Switching

S i hi
if Vin > 4 5&7 Network
4
Reference voltages

 Clock signal only applied to the first comparator

 Output signal of (N-1)th comparator used the trigger signal of Nth comparator
 Only one comparator is activated at any moment of the comparison phase

[5] Y. Z. Lin, et al., “A 5b 800MS/s 2mW Asynchronous Binary-Search ADC in 65nm CMOS,” in ISSCC Dig.
Tech. Papers, Feb. 2009, pp. 80-81.
[ Pow. (2mW), Area (0.02mm2), DNL/INL (0.56/0.62), SNDR/SFDR (26.9dB/35.9dB) ]
Small-
Small-Area ADC (Circuit Sharing) [6]

Q2 AMP1 Q1 Q2 AMP2 Q1

3-Bit 3-Bit 3-Bit

Vin SHA MDAC1 MDAC2 MDAC3

3-Bit 3-Bit 3-Bit 4-Bit

REGISTER

REGISTER
SHARED

SHARED
LADDER

LADDER
FLASH FLASH FLASH FLASH
ADC ADC ADC ADC
(F1) R (F2) (F3) (F4)

R
D

D
R

R
3bits 3bits 3bits 4bits
Q1
Q2 Digital Correction Logic 10bits

 SHA shares AMP1 with the 1st stage MDAC1

 The 2nd stage MDAC2 shares AMP2 with the 3rd stage MDAC3
 Flash ADCs share the resistor ladder work on opposite clock phase
[6] Y. D. Jeon, et al., “A 5mW 0.26mm2 10bit 20MS/s pipelined CMOS ADC with multi-stage
g amplifier sharing g
technique,” in Proc. ESSCIRC, Sept. 2006, pp. 544-547. [ Pow. (5mW), Area (0.26mm2), DNL/INL (0.8/1.7),
SNDR/SFDR (56dB/69dB) ]
Small-
Small-Area ADC (Cyclic Architecture) [7]

AIN From T&H

Analog 2.5-bit 2.5-bit
MUX MDAC1 MDAC2

S&H MX2
+
∑
Reference -
Generator
2.5
2 5-bit
bit 2.5-bit
2 5-bit
FLASH FLASH 1.5b 1.5b
MUX ADC1 ADC2 ADC DAC
STC
Control 2.5 bit 2.5 bit

Clock Digital EOC 1b

CKIN To Digital Error
Generator Correction Logic DOUT ADC
16 bit Correction

 The minimum function blocks recycled to acquire pipeline

performance with small size and low
low-power
power consumption

[[7]] H. C. Choi, et al., “A calibration-free 3V 16b 500kS/s 6mW 0.5mm2 ADC with 0.13um CMOS,” in Symp.
y p
VLSI Circuits Dig. Tech. Papers, June 2004, pp. 76-77.
[ Pow. (6mW), Area (0.5mm2), DNL/INL (0.9/6.1), SNDR (77.4dB) ]
High Resolution ADC (3D Fully Symmetric Layout) [8]

MET4
VIA3
MET3
VIA2
MET2
VIA1
MET1

: MIM Capacitor
C Top Plate
: Stacked metals of M1, 2, 4
: Stacked metals of M1, 3, 4
: Stacked metals from M1 to M4

„ Only MDAC capacitors isolated

„ High-matching capacitors insensitive to neighboring signals
[8] Y. J. Cho, et al., “A calibration-free 14b 70MS/s 3.3mm2 235mW 0.13um CMOS pipeline ADC with high-
g
matching 3-D symmetric capacitors,” in Proc. CICC, Sept. 2006, pp. 485-488.
[ Pow. (235mW), Area (3.3mm2), DNL/INL (0.65/1.8), SNDR/SFDR (65.7dB/80.6dB) ]
High Resolution ADC (Digital Calibration) [9]

((1)) Background
g Calibration

Vi ra Back-end ADC

1/8

ADC DAC
raes Do = ((Vi+Q
QN+(1/8)P
( ) N))raes
DO -(QN+(1/8)PN)ra+ON

PN
e = (1/8)(ra
(1/8)( es-ra))
Digital Domain e ra = raes-8e

 Binary pseudorandom noise sequence injected at the input of the sub-ADC

 ADC digital output correlated with the same pseudorandom sequence
to get the radix error
 Background calibration technique can continuously monitor the transfer
f
characteristics and correct the digital output codes accordingly
[[9]] J. Li, et al., “A 0.9V 12-mW 5-MSPS algorithmic
g ADC with 77-dB SFDR,” IEEE J. Solid-State Circuits,
vol. 40, No. 4, pp. 960-969, April 2005. [
Pow. (12mW), Area (1.4mm2), DNL/INL (0.6/1.4), SNDR/SFDR (50dB/77dB) ]
High Resolution ADC (Digital Calibration) [10]

((2)) Foreground
g Calibration
Acc & Avg
VGND
T/H Sub-ADCi Z-1 N 1/N bi

g
*Offset error foreground calibration ctl
Correction

T/H Sub-ADCi I.I Acc &Avg

Vref_cal

LMS
bi
Gain error foreground calibration
*Gain ei IViI
ai Z-1 u
IVOI

 Foreground (power-up) calibration performed to estimate initial values

for the gain/offset by configuring the circuit
[10] C. C. Hsu, et al., “An 11b 800MS/s time-interleaved ADC with digital background calibration,” in ISSCC Dig.
Tech. Papers, Feb. 2007, pp. 464-465. [ Pow. (350mW), Area (1.4mm2), DNL/INL (0.5/1.6), SNDR (58dB) ]
High Resolution ADC (Analog Calibration) [11]

Calibration Engine with

Permutation Generator and Spread Detector

S/H St
Stage 1 St
Stage 2 St
Stage 3 B k E d ADC
Back-End
3 3 3 7
Digital
Digital Error Correction Logic
Output
p

C4
Permutation
Address C3
2 x 32 C2
C1

ADC Decoder Select best matched

array by permutation
3b

 Each Unit DAC capacitor break into smaller element

 DAC capacitors reconstructed by grouping for the cancellation of error
[11] S. Ray
y and B. S. Song,
g “A 13b linear 40MS/s pipelined ADC with self-configured
g capacitor matching,”
g in
ISSCC Dig. Tech. Papers, Feb. 2006, pp.228-229.
[ Pow. (268mW), Area (3.6mm2), DNL/INL (0.4/3.0), SNDR/SFDR (67dB/70dB) ]
High-
High-Speed ADC (Full Flash ADC) [12]

Ref Ladder
Ref. Preamp Comparator NAND ROM Latch

Digitall Output
coder
Enc
Vin_plus Vin_min clk
Analog Input
 High speed, simplicity, and parallelism
 The number of comparators increases exponentially with the resolution
 Resolution limited less than or equal to 6 bits
[12] K. Uyttenhove
y and M. S. J. Steyaert,
y “A 1.8-V 6-bit 1.3-GHz flash ADC in 0.25-um CMOS,” IEEE
J. Solid-State Circuits, vol. 38, no. 7, pp. 1115-1122, July 2003.
[ Pow. (600mW), Area (0.12mm2), DNL/INL (0.42/0.8), SNDR/SFDR (30dB/41dB) ]
High-
High-Speed ADC (Multi Channel) [13]

f s/ 2 fs

Channel 1

Flash Digital
1ststage 2ndstage 3rdstage
S/H ADC
(3bit) (3bit) (3bit) (3bit) Logic
T1~ D1~D10

ver
T10

Output Driv
Vin

MUX
Channel 2

O
DB1~DB10
Flash Digital
1ststage 2ndstage 3rdstage
S/H ADC
(3bit) (3bit) (3bit) (3bit) Logic

 Operating speed enhanced with acceptable power consumption

 Channel mismatch of parallel ADCs demands complex and bulky calibration
circuits for high resolution

[13] S. C. Lee, et al., “A 10-bit 400-MS/s 160-mW 0.13-um CMOS dual-channel pipeline ADC without channel
mismatch calibration,” IEEE J. Solid-State Circuits, vol. 41. no. 7, pp. 1596-1605, July, 2006.
[ Pow. (160mW), Area (4.2mm2), DNL/INL (0.4/0.3), SNDR (55.9dB) ]
Current Status of ADC R&D

[’00]
20 JSSC
[’03] [’05][’08] [’03] [’05] [’09]
ISSCC
16
[’04] [’08] [’06] [’07] [’07] CICC
[’04] VLSI Symp.
[’06] [’03] [’04] [’07] [’06] [’06] [’06] [’06] [’06] [’07]
14 AP-ASIC
[’04] [’07] [’01] [’04] [’03] [’08] [’09]
[’04] [’00] [’00] [’08] APCCAS
bit]

[’08]
SGU IC Lab.
Lab
UTION [b

[’08] [’07]
[’06] [’06] [’00][’96] [’07][’08] [’09][’03] [’04] [’09] [’06] [’05] [’09]
12
[’03] [’09] [’96][’08] [’09] [’04] [’07] [’08] [’08] [’07] [’06]

[’08]
09] [[’07]
07][[’09] 07][[’09]
07][[’07]
09][[’07] 09] [[’02]
02] [[’01]
01] [[’04]
04] [[’08]
08] [[’06]
06]
RESOLU

[[’08]
08] [[’08]
08] 06] [[’07]
[[’06] 07] [[’05]
05][[’09] [[’04]
04] [[’07]
07] [[’09]
09] [[’07]
07]
10
[’05] [’03] [’07] [’06] [’07] [’09] [’09] [’04] [’07] [’08] [’03] [’05] [’03] [’07][’07] [’06] [’09]
[’09]

[’08]
[’07] [’07] [’01] [’00] [’04] [’04] [’01] [’02][’05] [’07] [[’04]] [[’02]]
8
[’07] [’00] [’05] [’03] [’04] [’04]
[’03] [’02] [’07] [’09]

[’03] [’09] [’08] [’02] [’02] [’01] [’06] [’03] [’03] [’09] [’08]
6
[’04] [’06] [’09][’08] [’09]
[’08] [’08] [’06] [’07]

[’08] [’09] [’03] [’03][’08] [’06] [’07]

4

0.25 1 50 100 150 200 500 1000 2000 5000

SPEED [MSample/s]
 A Calibration-
Calibration-Free 14b 70MS/s
0.13um CMOS Pipeline ADC
with High-
High-Matching 3D Symmetric C’s

Sept. 2006 (CICC)

SEUNG-HOON LEE
INTEGRATED CIRCUIT DESIGN LAB.
SOGANG UNIVERSITY, SEOUL, KOREA
Contents

„ Introduction

„ Proposed 14b 70MS/s 3-Step ADC

„ Circuit Design

„ Prototype ADC Implementation

„ Performance Measurements

„ Conclusion
C
Introduction (I)

„ Required ADC specs for WLAN and high-definition

display applications :
- Resolution : 14b, Sampling rate : 70MS/s

- Low-power
L consumption
ti and
dSSmall
ll chip
hi area in
i CMOS

„ Conventional
C ti l high-resolution
hi h l ti ADCs
ADC :

- Mostly complicated calibration techniques required to obtain

high resolution at high speed

- High-speed high-resolution SHA difficult to be implemented on chip

- ADC static and dynamic accuracy limited by cap mismatch

Introduction (II)

„ Proposed 14b 70MS/s 0.13um CMOS ADC :

- 3-D fully symmetric layout for 14b capacitor matching accuracy
in MDACs without any calibration scheme

- Trans-conductance
Trans conductance controlled SHA with 2-Stage
2 Stage amp and
gate-bootstrapped SWs for high sampling accuracy

- 3-stage
3 t pipeline
i li architecture
hit t to
t optimize
ti i power and
d chip
hi area
at 14b and 70MS/s

- O
Open-loop
l offset
ff t cancellation
ll ti and d interpolation
i t l ti ini 6b flash
fl h ADC
to improve accuracy with small chip area

- O
On-chip
hi currentt and
d voltage
lt references
f using
i off-chip
ff hi bypass
b C’s
C’
to reduce switching noise
Proposed 3
3-
-stage Pipeline ADC

AIN SHA MDAC1 MDAC2

I/V REFERENCE

FLASH
H

FLASH
FLASH
ADC1

ADC3
ADC2
WITH OFF-CHIP 5-b 5-b
CAP FILTERS

TIMING CIRCUIT 5-b 5-b 6-b

DIGITAL CORRECTION LOGIC

Q1P
Q1 14 b
14-b
Q2P
Q2 OPT. DECIMATOR ( 1/1, 1/2, 1/4 fs ) 14-b
DOUT
Sample-
Sample-and-
and-Hold Amplifier (SHA)

Q1 Q1B

MP3 OUT+
MN3
GT Q2PB Q2
GATE- C3
BOOTSTRAPPING BIAS T1
C1 MG1 MS1
IN+ Q1B
MN1 AT ACC Q2PB
AMP1 MP1 MP2 AMP2
MN2 AC ACT
IN- MT
C2 MG2 MS2
GATE- BIAS T2 C4
BOOTSTRAPPING GC
Q2PB Q2
MN4
Q1P MP4
Q1 OUT
OUT-
Q2 : SAMPLING PHASE
Q2 Q1 : HOLDING PHASE Q1 Q1B

„ 14b SHA with a DC gain of 95dB, f-3dB of 246MHz, and φPM of 74°

„ Gate-bootstrapped sampling switches for low input distortion with 4pF

sampling capacitors
Bootstrapping Circuit

VDD
Q2PB
M13
M1 M2 M3
M8
VSS
VDD M11 M12

M5 Sampling SW & SHA

C1 C2 C3 Q2
M7 OUT

M6 G (VDD+VIN)
Q2 Q2B M9 VDD
Q2B Q2 IN
Cs
S (VIN) D
Q2B M4 M10
Q2B AMP
VSS

„ VGS (sampling switch) = VOUT - VIN = VDD = constant (on Q2)

„ PMOS transistor M10 added for higher linearity

3D Symmetric C Layout of MDAC (V1)

MET4
VIA3
MET3
VIA2
MET2
VIA1
MET1

: MIM Capacitor Top Plate

: Stacked metals of MET1, 2, 4
: Stacked metals of MET1, 3, 4
: Stacked metals from MET1
to MET4

„ MDAC capacitor mismatch critical to ADC non-linearity

„ Both MDAC capacitors and signal lines isolated

3D Symmetric C Layout of MDAC (V2)

MET4
VIA3
MET3
VIA2
MET2
VIA1
MET1

: MIM Capacitor Top Plate

: Stacked metals of MET1, 2, 4
: Stacked metals of MET1, 3, 4
: Stacked metals from MET1
to MET4

„ Only MDAC capacitors isolated

„ High-matching
Hi h t hi capacitors
it insensitive
i iti tot neighboring
i hb i signals
i l
FLASH3 AMPS : Open
Open-
-Loop Offset Sampling

0.46
75%
BIAS

ge[ V ]
Q2PB
Cos1 = 1.6mV
TN1 TP2
TP1

Voltag
IN+
PREAMP1 PREAMP2 Q1
IN- TN1
TP1 TN2
Cos2
Q2PB
~ 31.25mV )
( 1LSB / 6b =
BIAS
0.12
40 43.5 45.25 47
Time [ ns ]

„ Q1 Phase : offset canceling and amplifying

„ Q2 Phase : offset sampling

Proposed On
On-
-Chip I/V References

ON- CHIP VDD VDD OFF- CHIP

I/V REFERENCES EXTRFB FILTERS
MPS
( Required )
IVCN
T1

OP
REFTO
AMPT MPB
CB1
IREF & REFT
Cc1 Rc1
VREF LEVEL
SHIFTER
REFC Cc2 Rc2

REFBOT
T
CB2
AMPC` MNB
EXTRF EXTRFB T2

MNS
EXTRF
Optional Ext. Voltage References VSS VSS
Available with “EXTRF” High
Simulated Voltage Driver Outputs

0.57 -0.43

off-chip 0.1uF C off-chip 0.1uF C

TOP [ V ]

T/2 = 7.14ns
7 14

BOT [ V ]
T/2 = 7.14ns

+ 0.06mV + 0.06mV

0.50 -0.50

REFB
REFT

- 0.06mV - 0.06mV
- 0.06mV

Settling time = 2.72ns Settling time = 2.27ns

38% of T/2 32% of T/2

Ideal = GND + 0.5 Ideal = GND - 0.5

0 43
0.43 0 57
-0.57
98 100 102 98 100 102
Time [ ns ] Time [ ns ]
Prototype ADC Chip Photo

ASH1

ASH2

FLASH3
„ Designed and laid out with

DCL
a 0.13um
0 13 1P7M CMOS :

D
FLA

FLA
( Only 4 metals employed )
CLK

„ Occupied die area : 3.3mm2

IVREF ( = 1.65mm × 2.01mm )

„ Decoupling capacitors ( )
CML

SHA MDAC1 MDAC2

laid out in each functional block
to reduce coupling noise
Evaluation Board

Digital Power Latch Power

„ Design issues :
Voltage
g
Regulator - High speed digital latch

Digita
at outputs
Crystal Digital
DUT

al Outputts
Oscillator L t h
Latch - Passive filters at inputs
Analog
Input - Crystal Oscillator with a
ji
jitter off 1ps
1 level
l l

- Voltage regulators with

low glitch

Analog Power
Measured DNL & INL of ADC (V1)

1
DNL [ LSB/14b ]

-1
0 CODE 16383

10
b]
LSB/14b

0
INL [ L

-10
0 CODE 16383
Measured DNL & INL of ADC (V2)

1
DNL [ LSB/14b ]

-1
0 CODE 16383

2
b]
LSB/14b

0
INL [ L

-2
0 CODE 16383
Measured FFT Plot of ADC (V2)

0
Latch
fin = 1MHz fs
fs = 70MHz DUT
(16384 FFT) (fs) ½fs Outputs

-50 ¼fs
dB ]

Harmonic distortions closely related

[d

to the signal generator performance

-100
100

-150
0 17.5
F
Frequency [ MHz
MH ]
Measured SFDR & SNDR vs. Sampling Freq.

90

80 SFDR(V2)

SFDR(V1)
dB ]

70
[d

SNDR(V2)
SNDR(V1)
60
f in = 1MHz

0
0 20 40 60 80
Sampling
p g Frequency
q y [ MHz ]
Measured SFDR & SNDR vs. Input Freq.

80

SFDR(V2)

70
SFDR(V1)
dB ]
[d

SNDR(V2)
60 SNDR(V1)

f s = 70MHz

0
1 10 20 30 40
Input Frequency [ MHz ]
Measured ADC Performance

VERSION1* VERSION2*
Resolution 14bits
Max. Conversion 70MS/s
Process 0.13um CMOS ( Lmin = 0.35um for 2.5V systems
y )
Input Range 2.0Vp-p
SNDR (at fin = 1MHz) 63.4dB 65.7dB
SFDR (at fin = 1MHz) 72.2dB 80.6dB
DNL - 0.66LSB / + 0.77LSB - 0.60LSB / + 0.65LSB
INL - 4.62LSB / + 9.82LSB - 0.98LSB / + 1.80LSB
ADC Core Power 235mW at 70MS/s and 2.5V
Active Die Area 3.3mm2 (= 1.65mm × 2.01mm)

* VERSION1 : MDACs with both capacitors and signal lines isolated

* VERSION2 : MDACs with only capacitors isolated
Power vs. Speed of 14b to 16b ADCs

1000 CICC03-16b
ISSCC00-14b
Consumption [ mW ]

ISSCC04-15b
SSCC0 5b
JSSC05-15b
ISCAS01-15b ISSCC04-14b ISSCC01-14b

JSSC02-14b
ISSCC04-15b
VLSI96-14b
ESSCIRC05-14b This Work
ISCAS00 14b
ISCAS00-14b ((= 3.36mW/MHz)
Power C

ISSCC04-14b
100 JSSC04-14b CALIBRATION-FREE ADC
CALIBRATED ADC
P

10 100
Sampling Rate [ MHz ]
Comparison to Previous 14b ADCs

Bits MS/s mW mm2 DNL / INL Calibration

Proposed ADC 14 70 235 3.3 0.65 / 1.80 X

[[1]] ISCAS00 14 10 118 2.4 0.73 / 1.55 X

[2] JSSC04 14 12 98 15.1 0.47 / 0.54 X

[3] ISSCC00 14 20 720 10.8 0.28 / 1.06 X

[4] ISSCC01 14 75 340 7.8 0.60 / 2.00 X

[5] JSSC02 14 10 220 12.5 0.60 / 2.50 O

[6] ESSCIRC05 14 40 220 65

6.5 0 25 / 1
0.25 1.50
50 O

[7] ISSCC04 14 50 350 16.0 0.50 / 1.00 O

A 10b 25MS/s 4
4.8mW
8mW 00.13um
13um CMOS
ADC
for DMB Application

Sept. 2006 (CICC published)

SEUNG-HOON LEE
INTEGRATED CIRCUIT DESIGN LAB.
SOGANG UNIVERSITY,
UNIVERSITY SEOUL,
SEOUL KOREA
Contents

„ Introduction

„ Proposed 10b 25MS/s CMOS ADC

„ Circuit Design

„ Prototype ADC Implementation

„ Performance Measurements

„ Conclusion
C l i
Introduction (I)

„ Required ADC Spec for DMB Applications :

- Resolution
R l ti : 10b
10b, Supply
S l voltage
lt :1
1.2V,
2V f sample
l : 25MS/
25MS/s

- Low-power consumption and small chip area in CMOS

„ Limitations of Conventional Pipeline ADCs :

- Speed, power, and chip area limited by inter-stage amps

- Low power difficult due to required analog circuits

- ADC static and dynamic accuracy affected by C mismatch

- Low-noise refs difficult to be implemented on a single chip

Introduction (II)

„ System Solutions for Low Power :

- 2
2-stage
t pipeline
i li architecture
hit t to
t optimize
ti i power and
d chip
hi area
at 10b and 25MS/s

- Switched-bias power reduction techniques in analog circuits

to obtain ultra low power

- Down-sampling clock mode to select 10MS/s depending on

q
other required applications
pp
Introduction (III)

„ Circuit Solutions for Improved Performance :

- 3
3-D
D ffully
ll ssymmetric
mmetric la
layouts
o ts in MDAC to achie
achieve
e high static
and dynamic accuracy

- On-chip I/V refs with optional off-chip bypass C’s and voltage
refs to reduce transient glitch

- Merged capacitor switching and on-chip MOS capacitors to

minimize MDAC noise
Proposed 2
2-
-step Pipeline ADC

AIN SHA MDAC

DNCK PDOWN PDOWN

I/V References
With Optional Off-chip FLASH FLASH
Cap Filters 5-b
ADC1 ADC2

Timing Generator
PDOWN PDOWN
5-b 6-b
Q1P
Q1
Digital Correction Logic 10-b
Q2P DOUT
Q2

„ PDOWN : Power Down Mode

„ DNCK : 25MS/s and 10MS/s Sampling Clock Selection`

Sample-
Sample-and-
and-Hold Amplifier (SHA)

Q1 Q1B

MP3
Q2 Q2B MN3 OUT+
Q2PB Q1P
Q
BIAS
MP1 C1 MG1
Q1
IN+
MN1 AT ACC Q1B
Q
AMP
MN2 AC ACT Q2
IN- MT
MP2 C2 MG2
BIAS
Q2 : SAMPLING PHASE
Q2PB Q1 : HOLDING PHASE
MN4 OUT-
Q2 Q2B
MP4

Q1 Q1B
Switched-
Switched-Bias Power Reduction for SHA

<AMP = 68% of SHA power> <BIAS = 32% of SHA power>

VDD
M4 M5 VDD
MP1 MP2 MP3 MP4 MP5 MP6
30%Ⅰ
reduced 2
M6 M7 BIAS1
IN IN OUT 70 : 30
BIAS2
Q
+ + 1
M1 M2 M8 M9 IREF
BIAS4
100%Ⅰ
reduced
M10 M11 1
M3 MN1 MN2 MN3 MN4
VSS Amplifying
VSS
Current Reduction in Sampling Sequence Delay Cell

„ Sampling - Currents reduced by 30% with BIAS1 & 2 and by 100% with BIAS4

g
„ Holding - Currents resumed with switching
g sequence;
q ;
first BIAS4, then BIAS1 and BIAS2
- Timing delay needed by MP3 and MN3
„ Total (= AMP + BIAS) power consumption reduced by 10%
Switched-
Switched-Bias Power Reduction for MDAC

<AMP = 96% of MDAC power> <BIAS = 4% of MDAC power>

VDD
M4 M5 M12 M13 VDD
2 MP1 MP2 MP3 MP4 MP5 MP6
20%Ⅰ
reduced OUT BIAS1
+ BIAS2 80 : 20
M6 M7
IN IN
AMP1 AMP2 Q2
+ M14 M15 IREF
M1 M2 M8 M9
BIAS4
100%Ⅰ
reduced
M10 M11 M16 1
M3 MN1 MN2 MN3 MN4
VSS
Amplifying VSS
Current Reduction in Sampling
p g Sequence
q Delay
y Cell

„ Sampling - Currents reduced by 20% with BIAS1 & 2 and by 100% with BIAS4

„ Amplifying - Currents resumed with switching sequence;

first BIAS4, then BIAS1 and BIAS2
- Timing delay needed by MP3 and MN3
„ Total (= AMP + BIAS) power consumption reduced by 10%
Switched-
Switched-Bias Power Reduction for FLASH

<All PREAMPS = 45% <BIAS + DIGITAL = 55%

of FLASH ADC power> of FLASH ADC power>
VDD
M1 M2 M3 M4 VDD
MP1 MP2 MP3

OUT 75 : 25
+ CK
IN IN
AMP 75%Ⅰ IREF
+ reduced
M5 M6

M7 M8 BIAS1 MN1

VSS
VSS

„ Sampling - Currents reduced by 75% with BIAS1

„ Amplifying - Currents resumed with BIAS1 fully turned on

„ Total (= PREAMPS+BIAS+DIGITAL) power reduced by 17%

Merged Capacitor Switching (CICC’
(CICC’02)

T1
VOUT Conventional 5b
AMP
MDAC
C1 C2 C3 C4 C5 C6 C29 C30 C31 C32
+VREF +VREF +VREF -VREF -VREF -VREF -VREF -VREF
1 1 1 0 0 0 0 0

+VREF GND -VREF -VREF F/B

T1
VOUT Proposed
AMP
5b MDAC
C1' C2' C3' C15' C16'
+VREF GND -VREF -VREF

„ Reduced
R d d number
b off capacitors
it by
b 50% :

- Increases operating speed of amplifiers with less power

- Improves
I C matching
t hi accuracy and
d noise
i performance
f
3-D Fully Symmetric MDAC Cap’
Cap’s

MET7
VIA6
MET6
VIA5
MET5
VIA4
MET4
VIA3
MET3
VIA2
MET2
VIA1
MET1

: MIM capacitor top metal

: MIM capacitor bottom metal
: Stacked metals from MET1 to MET6
: Stacked metals from MET1 to MET7

„ Only MDAC capacitors isolated

„ MDAC capacitors insensitive to neighboring signals for high matching

accuracy
Proposed On
On-
-Chip I/V References

IREF VREF LEVEL SHIFTER VREF DRIVER

VDD VDD VDD VDD
Down-Sampling EXTRFB EXTRFB
Clock Selection
DNCK
MRS MPS
VREFIN
POFF TR1 T1
IVCN
IREF AMP MR1 AMP MPB
REFT
C 1R
Cc1 Rc1
1 REFTOP
AMP_BIAS C1
R1
BIAS TR2
Cc2 Rc2 REFBOT
R2
REFC
EXTRFB EXTRFC AMP MNB
EXTRF T2
IR3 R3 MNS
EXTRFC
„ External reference optional
VSS VSS VSS
Prototype ADC Chip Photo

DCL
SH1

SH2
„ Designed and laid out with
FLAS

FLAS
a 0.13um 1P8M TSMC CMOS :

CLK
p
„ Occupied die area : 0.80mm2
(= 0.67mm × 1.18mm)

„ Decoupling capacitors
IVREF (PMOS : , NMOS : ) laid out
separately in each functional block
MDAC t reduce
to d coupling
li noise
i
CML
L

SHA
Evaluation Board

Digital Power Latch Power

„ Design issues :

uts
Digitall Outpu
Digital - Single-ended and
DUT Latch differential inputs
available
- High-speed digital
latch at outputs
p

Analog
Input - Passive filters at
analog inputs

Analog Power
Measured DNL & INL

b]
DNL [ LSB/10b 1.0

-1.0
0 CODE 1023

1.0
SB/10b ]

0
INL [ LS

-1.0
0 CODE 1023
Measured FFT Plot

0
fin = 1MHz
fi 1MH
fs = 25MHz (1024 FFT)

- 40
B]
[ dB

- 80

- 120
0 12.5
Frequency
q y [ MHz ]
Measured SFDR & SNDR Performance

80

60
B]

40
[ dB

SFDR
20
fin = 1MHz SNDR

0
0 10 20 25 30 40

Sampling Frequency [ MHz ]

Measured SFDR & SNDR Performance

80

60

40
B]
[ dB

SFDR
20
fs = 25MHz SNDR

0
0 10 20 30 40 50 60 70 80

Input Frequency [ MHz ]

Measured ADC Performance

NOMINAL MODE DOWN-CLOCK MODE

Resolution 10bits
Max. Conversion 25MSample/s 10MSample/s
Process 0.13um CMOS ( with MIM Capacitors )
Input Range 1.0Vpp
SNDR 56dB (at fin = 1MHz)
SFDR 65dB (at fin = 1MHz)
DNL - 0.42LSB / + 0.41LSB
INL - 0.89LSB / + 0.91LSB
ADC Core Power 4.8mW @ 1.2V 2.4mW @ 1.2V
Active Die Area 0.8mm2 (= 0.67mm × 1.18mm)
Power vs. Speed Comparison

100
: 1.5b/stage ISCAS01
: 2.5b/stage ISSCC03 CICC03
ESSCIRC05
: 3b-3b-3b-4b
mption [[mW]

ISCAS00 ESSCIRC05
: 4b-3b-3b-3b ISSCC05
: 2b-3b-3b-3b-3b
2b 3b 3b 3b 3b ISSCC04
VLSI 04
: 3b-3b-3b-3b-2b
JSSC03
ISSCC06
Consum

ISSCC02
ISSCC06
ESSCIRC02
Power C

This Work
ISSCC05 (5b--6b p
((5b pipeline
p : 0.19mW/MHz))
P

1
2 Speed
p [MHz]
[ ] 100 200
 A Re-
Re-configurable 0
0.5V
5V to 1
1.2V,
2V
10MS/s to 100MS/s, Low-
Low-Power
10b 0.13um CMOS Pipeline ADC

Sept. 2007 (CICC published)

SEUNG-HOON LEE
INTEGRATED CIRCUIT DESIGN LAB.
SOGANG UNIVERSITY,
UNIVERSITY SEOUL,
SEOUL KOREA
Contents

„ Introduction

„ Proposed ADC Architecture

„ Circuit Design

„ Prototype ADC Implementation

„ Performance Measurements

„ Conclusion
C l i
Introduction (I)

„ Required ADC specs for WLAN and Image Signal

Processing :
- Resolution : 10b, Supply voltage : 0.5V~1.2V

- Sampling
p g rate : 10MS/s~100MS/s
- Low-power consumption and small chip area for SoC

„ Conventional
C pipeline ADCs
C :
- Speed, power, and chip area limited by low supply voltage
- Input accuracy limited by R and C of input switches at low supply
voltages
- ADC static and dynamic accuracy affected by C mismatch
- Low-noise refs difficult to be implemented on a single chip
Introduction (II)

„ Proposed re-configurable 10b CMOS ADC :

-2
2-step
step pipeline arch.
arch to optimize power and chip area at
10b and 10MS/s to 100MS/s

- Low-voltage amp with high signal swing and switched-bias

power reduction scheme

- SHA with
ith gate-bootstrapped
t b t t d input
i t sampling
li switches
it h att
0.5V to 1.2V supply

- All directionally-isolated symmetric capacitor layout in

MDAC for high linearity

- On-chip full CMOS I/V references for wideband operation

at variable supply voltages
Proposed 2
2-
-step ADC Architecture

AIN SHA MDAC

I/V REFERENCE
WITH OPTIONAL OFF- FLASH FLASH
CHIP C FILTERS 5-b
ADC1 ADC2

TIMING GENERATOR
5-b 6-b
Q1P
Q1
Q2P DIGITAL CORRECTION LOGIC 10-b
10 b
Q2 & DECIMATOR DOUT
Sample-
Sample-and-
and-Hold Amplifier (SHA)

Q1 Q1B

MP3 OUT+
MN3
GT Q2PB Q2
GATE- C3
T1
BOOTSTRAPPING BIAS
C1 MG1 MS1
IN+
MN1 AT ACC Q2PB Q1B
AMP1 MP1 MP2 AMP2
MN2 AC ACT
IN- MT
C2 MG2 MS2

GATE- BIAS T2 C4
BOOTSTRAPPING GC Q2PB Q2
MN4
Q1P MP4
Q1 OUT-
Q2 : SAMPLING PHASE
Q2 Q1 : HOLDING PHASE Q1 Q1B

„ 10b SHA based on a 2-stage low-voltage amp with 69° φPM

„ Gate-bootstrapped sampling SWs for 10b accuracy at 0.5V to 1.2V supply

All Directionally-
Directionally-isolated MDAC Cs

MET4
VIA3
MET3
VIA2
MET2
VIA1
MET1

: MIM Capacitor Top Plate

: Stacked Metals of MET1, 3, 4
: Stacked Metals of MET1, 2, 4

z
: Stacked Metals from MET1
to MET4

„ MDAC capacitor mismatch critical to ADC non-linearity

„ Both MDAC capacitors and signal lines isolated

Switched-
Switched-Bias Power Reduction for FLASH

M1 M2 M3 M4 M9 M10 M11 M12 VDD VDD

MP1 MP2 MP3

BIAS OUT 100%Ⅰ

reduced CK
+
Q1PB MS11
IN IN
+ XC3
M5 M6 M14 IREF
XC4 M13
M7 M8 M15 M16
Q1PB MS12
MN1 MN2
BIAS1 BIAS BIAS2

VSS VSS

„ Sampling - Currents reduced by 100% with BIAS2

- Offset sampling with BIAS1
„ Amplifying - Currents resumed with BIAS2 fully turned on

„ Total (=PREAMPS+BIAS+DIGITAL) power reduced by 20%

Proposed On
On-
-Chip I/V References

IREF VREF LEVEL SHIFTER VREF DRIVER ON-CHIP FILTER

POFF VDD VDD VDD VDD

EXTRFB EXTRFB Rf2 Cf2

IVCN
MRS MPS
VREFIN
IREF TR1 T1
AMPR MR1 AMPT MPB
Rf1 Cf1
REFT

AMP_BIAS Cc1 Rc1

C1
R1
BIAS TR2
Cc2 Rc2
R2

EXTRF EXTRFB EXTRFC AMPC MNB

REFC REFTOP
T2
IR3 R3 TO on-
on-chip
MNS
ADC
EXTRFC
REFBOT
VSS VSS VSS

„ Optional external voltage reference employed

Prototype ADC Chip Photo

LK
CL
DCL

ASH2
ASH1
„ Implemented with a 0.13um
1P6M Samsung CMOS :

FLA
FLA „ Occupied die area : 0.98mm2
( = 0.82mm × 1.20mm )

IVREF „ Decoupling
p g capacitors
p
( PMOS : , NMOS : )
CML

laid out separately in each

SHA MDAC functional block to reduce
coupling noise
Evaluation Board

Digital Power

„ PCB design issues :

Outputs
s
Analog
Digital - Single-ended and differential
Input
DUT Latch inputs available

Digital O
- Passive filters at inputs

D
- High-speed digital latch at
outputs

Analog Power Digital Latch Power

Measured DNL & INL of ADC

0b ]
DNL [ LSB/10 1.0

-1.0
0 CODE 1023

1.0
b]
LSB/10b

0
INL [ L

-1.0
0 CODE 1023
Measured FFT Plot of ADC

0
fin = 1MH
fi 1MHz
fs = 70MHz (1024 FFT)

- 40
[ dB ]

- 80

- 120
0 35
Frequency [ MHz ]
Measured SFDR & SNDR vs. Sampling Freq.

80

60
B]

40
[ dB

fin = 1MHz @ 0.8V SFDR

20
SNDR

0
0 10 20 30 40 50 60 70 80

Sampling Frequency [ MHz ]

Measured SFDR & SNDR vs. Input Freq.

80

60
B]

40
[ dB

fs = 60MHz @ 0.8V SFDR

20
SNDR

1 10 20 30

Input Frequency [ MHz ]

Measured ADC Performance

Resolution 10bits

Process Samsung 0.13um CMOS ( MIM Cap. )

Input
p Range
g / On-Chip
p REF 0.8Vpp ((Fixed,, Off-Chip
p Ref Optional)
p )

Power Supply 0.5V (Min.) 0.8V (Typ.) 1.2V (Max.)

Max. Conversion Rate 10MS/s 60MS/s 100MS/s
SNDR 52.9dB 56.0dB 53.3dB
SFDR 64 9dB
64.9dB 69 6dB
69.6dB 70 2dB
70.2dB
ADC Power 3.0mW 19.2mW 45.6mW
DNL INL
DNL, 0 35LSB / 0
0.35LSB 0.49LSB
49LSB

Active Die Area 0.98mm2 ( = 0.82mm × 1.20mm )

Comparison to Previous 10b ADCs

Supply Speed Power Area DNL / INL

[V] [ MS/s ] [ mW ] [ mm2 ] [ LSB ]

This Work 0.5~1.0 10~100 3~45.6 0.98 0.35 / 0.49

[1] ISSCC07 0.8 80 6.5 0.64 0.80 / 1.00

[2] ISSCC07 10
1.0 30 47
4.7 0 32
0.32 0 47 / 0
0.47 0.80
80

[3] VLSI06 1.0 100 30.0 4.03 0.50 / 0.80

[4] CICC05 1.0 100 40.0 0.52 0.38 / 0.96

[5] ISSCC07 1.0 160 84.0 0.42 -/-

[6] ISSCC07 1.0 205 111 1.00 0.50 / 0.50

An 11
11bb 70MHz 1.2mm2 49mW 0.18um CMOS ADC
with
ith On-
On
O -Chip
Chi Current/Voltage
C t/V lt References
R f
[REF: 28th European Solid
Solid-State
State Circuits Conference
(ESSCIRC), Florence, Italy, pp. 463-466, Sept. 2002]

SEUNG HOON LEE

SEUNG-HOON

INTEGRATED CIRCUIT DESIGN LAB.

SOGANG UNIVERSITY,, SEOUL,, KOREA
Contents

„ INTRODUCTION

„ LIMITATIONS & SOLUTIONS IN PROTOTYPE ADC

„ PROPOSED ADC ARCHITECTURE

„ CIRCUIT IMPLEMENTATION

„ MEASUREMENT RESULTS

„ CONCLUSION
INTRODUCTION

„ High-performance ADCs for high-speed communication system

applications commonly adopt pipelined architecture considering
speed,
d power consumption,
ti and
d chip
hi area :

- Sampling rate : 50MHz - 200MHz

- Resolution : 10b - 14b
- Low power consumption and small chip area

„ Required ADC spec for this VDSL application :

- Process : 0
0.18um
18um CMOS
- Sampling rate : 70MHz (max.), 60MHz (typ.)
- Resolution : 11b
- SFDR : 70dB + at 12MHz fin
- Input range : 1Vpp
- Power
P consumption
i : 49mW
49 W at 70MS/s
0MS/
LIMITATIONS & SOLUTIONS IN PROTOTYPE ADC

„ System limitations :

- Minimized number of externally connected I/O pins

- On-chip current/voltage reference circuit required

- Low power consumption and small chip area

„ Proposed ADC solutions :

- Multi-step pipelined architecture for performance trade-off

- I/O pins only for power supplies and bypass capacitors

- On-chip current/voltage references for high-speed driving capability

of on
on-chip
chip R&C loads

- Merged-Capacitor Switching(MCS) technique for high sampling rate

and high resolution
PROPOSED ADC ARCHITECTURE

4-BIT 4-BIT
INPUTS SHA MDAC1 POWERS
MDAC2

4-BIT 4-BIT 5-BIT

I/V FLASH FLASH FLASH
REFERENCE ADC
REFS ADC ADC
CIRCUIT ( F1 ) ( F2 ) ( F3 )

FOR TESTING &

4 BITS 4 BITS 5 BITS OUTPUTS
COMPARISON
11 BITS

DIGITAL CORRECTION LOGIC

„ Multiplying DAC uses MCS technique for reduced parasitics :

„ Proposed current/voltage reference implemented with CMOS :
- generates digitally-controlled differential voltage reference
- employs on
on-chip
chip CMOS buffers to drive heavy internal R&C loads
SAMPLE-
SAMPLE-AND-
AND-HOLD AMPLIFIER (SHA)
4b MULTIPLYING D/A CONVERTER (MDAC)

Bottom plate parasitic = 10%

MCS TECHINIQUE [S. Yoo et al., CICC2002]

T1
VOUT
AMP Conventional
4b MDAC
C1 C2 C3 C4 C5 C6 C13 C14 C15 C16
+VREF +VREF +VREF -VREF -VREF -VREF -VREF -VREF
1 1 1 0 0 0 0 0

+VREF GND -VREF -VREF F/B

T1
VOUT
AMP Proposed
4b MDAC
C1' C2' C3' C7' C8'

+VREF GND -VREF -VREF

„ Reduced number of unit capacitors by 50% :

- Increases operating speed of amplifiers with less power on same sized unit C
- Improves
I C matching
t hi accuracy with
ith same power & Ctotal on double
d bl sized
i d unit
it C
4b MDAC IMPLEMENTATION WITH MCS TECHNIQUE

- VREF
+ VREF

VINT
„ Key enhancements :
Decoder C1' C2' C3' C7' C8'
- Only 8 unit Cs required
instead of 16 unit Cs
AMP OUT
- CFCS available
4b ADC - “- VREF” for differential
C1'' C2'' C3'' C7'' C8''
GND instead of floating
VINC reset

+ VREF
- VREF
CONVENTIONAL VOLTAGE REFERENCES

On Chip Off Chip

REFTOP(( to ADC ) „ CASE 1 [ISSCC 2000] :
VREF
5 ~ 8nH – On-chip wideband preamps
Internally
generated 20x 20x Gm – Off-chip 0.1uF capacitor
01 F
0.1uF
GND – Large power consumption
5 ~ 8nH
REFBOT( to ADC )

DAC On Chip Off Chip „ CASE 2 [Symp. on VLSI 1999] :

– 0.5nF on-chip decoupling
VREF capacitor
5 ~ 8nH

5 ~ 8nH – Off-chip
Off hi 0.1uF
0 1 F capacitor
it
0.1uF
0.5nF
– Large active chip area
PROPOSED CURRENT/VOLTAGE REFERENCES

Current reference Digital

with a negative T.C. calibration
REFERENCE
CURRENT
Current reference
with a positive T.C. Reference
voltage Based on
generator g
digital calibration
for accurate outputs

On-chip voltage drivers

Reference voltage level shifter for high speed operation

REFERENCE
Reference voltage driver VOLTAGES
CIRCUIT IMPLEMENTATION

CURRENT REFERENCE VOLTAGE REFERENCE

REFERENCE LEVEL SHIFTER VOLTAGE DRIVER

IVCON VDD IVCONZRB VDD VDD

MPS
VREFIN MPB
T1
IREF TR1
MR1 AMPT 0.01~0.1uF
AMPR
T3
REFT

AMP_BIAS C1 Cc1 Rc1

R1 Ext.
BIAS 5~8nH REF
REFC
Cc2 Rc2
R2
TR2 T4
AMPC 0.01~0.1uF
IR3 T2
R3 MNB
IVCONZR
1 IVCONZRB IVCONZR MNS
S

IVCONZR
VSS VSS VSS OPTIONAL
On-Chip TO 11b CMOS ADC CORE REF
PROPOSED CURRENT REFERENCE

CURRENT REFERENCE CURRENT CURRENT REFERENCE DIGITALLY CALIBRATED VOLTAGE

WITH A NEGATIVE T.C. ADDER WITH A POSITIVE T.C. CURRENT OUTPUT

VDD

MP1 MP6 N
Rd1
MP9 MP10 MP16
Ra MP17 MP18
T1 MP3
T3
MN11 MN17
ISUM T8
MP2 Rd2 N
T12
MP7 MP8
MP4
T2 T4
T7 CONTROL SIGNALS
MP5

INEGG IPOS VREF

IOUT
T6
T9 T10 T11
T5

MN1 MN2 MN3 MN4 MN5 MN6 MN7 MN8 MN9 MN10 MN18 MN19 MN20

VSS
CONVENTIONAL vs. PROPOSED REFERENCES

Architecture Descriptions
Current - Extra analog pins
- Analog calibration
ntional

Reference [1] - External noise coupling

- Wideband on-chip preamps
- Large power consumption
Conven

Voltage
V lt - External 0.1uF capacitors
Reference
[2][3] - 0.5nF on-chip decoupling cap.
- Large active chip area
- External 0
0.1uF
1uF capacitors

Current - Minimized analog pins

osed

- Digital calibration
Reference - Reduced noise coupling
Propo

Voltage - Internal reference drivers - Low power consumption

Reference - Optional Ext. 0.1uF capacitors - Small active chip area

[1] S. Lee et al., IEICE Trans. Electron. Vol. E82-C, pp. 1562-1566, Aug. 1999
[2] L. Singer et al., ISSCC Dig. Tech. Papers, Feb. 2000, pp. 38-39
[3] K. Khanoyan et al., Symp. VLSI Circuits Dig. Tech. Papers, Jun. 1999, pp. 73-76
PROTOTYPE ADC CHIP PHOTO

„ Fabricated with a 0.18um

ADC single-poly quad-metal
CMOS process :

„ Active die area : 1.2mm2

( = 1.0mm × 1.2mm )
PROTOTYPE ADC EVALUATION BOARD

ower
put
nalog Inp
nalog Po

„ Design Features :
- Optional
p off-chip
p reference
An
An

- DUT without socket

- Differential inputs

- High speed digital latch

al Powerr

at outputs

- Passive filters at inputs

Digita

Digital
g Outputs
p Digital
g Latch Power
MEASURED DNL & INL

1.5
L [LSB/11b]

0
DNL

-1.5
0 CODE 2047

1.5
b]
INL [LSB/11b

-1.5
0 CODE 2047
MEASURED FFT

fin = 20MHz, fs = 70MHz (2048 FFT)

-30
B]
[dB

-60

-90

-120
0 Frequency [MHz] 35
MEASURED SFDR & SNDR vs. fs

90
SFDR

70

SNDR
[dB]

50

30

@ fin = 3MHz
10
10 30 50 70
fs [MHz]
MEASURED SFDR & SNDR vs. fin

90

SFDR
70
[dB]

50 SNDR

30

10 @ fs = 60MHz

3 10 15 30
fin [[MHz]]
MEASURED REFERENCE VOLTAGES

0.6
0.60

„ Diff. Vout vs. Temp.

F. Vout [ V ]

0.55

0.5 - Min. Voltage = 504mV

0.50
- Max. Voltage
g = 507mV
DIFF

0.45
- T.C. = 48ppm / °C
0.4
0.40
-25 0 25 50 75 100
-25 0 25 50 75 100
Temperature [ °C ]
0.6
0.60

„ Diff. Vout vs. Supply

DIIFF. Vout [ V ]

0.55

0.5
0.50 - Min. Voltage = 498mV
- Max. Voltage = 503mV
0.45
- V.C. = 2.59% / V
0.4
0.40
1.6
1.6 1.7
1.7 1.8
1.8 1.9
1.9 2.0
2.0

Supply Voltage [ V ]
MEASURED ADC PERFORMANCE

Resolution 11 bits
Max. Conversion Rate 70MSample/s
Process 0.18um CMOS
Input Range 1Vp
1Vp--p

SNDR (at 70MS/s) 60.2dB at 3MHz fin, 56.5dB at 20MHz fin

SFDR (at 70MS/s) 72.3dB at 3MHz fin, 68.9dB at 20MHz fin

DNL ± 0.63LSB

INL ± 1.21LSB

ADC Power 49mW at 1.8V

Die Area 1.2mm2 ( = 1.0 × 1.2mm2 )

Differential Temperature Coeff. 48ppm/℃

48ppm/℃
Reference Voltages Supply Voltage Coeff. 2.59%/V
HIGH-SPEED CMOS COMPARATORS
AS A DESIGN EXAMPLE

SEUNG-HOON LEE
ELECTRONIC ENGINEERING
SOGANG UNIVERSITY
COMPARATORS

A. DEFINITION

VDD Vo

+
+
Vi VO Vi
VOS
- -

TRANSFER FUNCTION
VSS
“1 BIT A/D CONVERTER”

Vi Vo

A
1mV

t t

WAVEFORMS
IN A REAL CIRCUIT
COMPARATORS

B. COMPARISON BETWEEN OP AMPS AND COMPARATORS

GAIN IN dB GAIN IN dB

B.W.

ω ω

Φ ① UNCOMPENSATED
② OPEN-LOOP OPERATION
-135º
135 ③ WIDER BANDWIDTH (B.W.)
(B W )
→ FASTER

OP AMP (→
( COMPENSATED)
COMPARATORS

C. REQUIREMENTS OF COMPARATORS

(1) HIGH DIFFERENTIAL GAIN

(2) LOW OFFSET VOLTAGE

(3) HIGH COMMON MODE REJECTION

POWER SUPPLY REJECTION

(4) HIGH BANDWIDTH

FOR HIGH-SPEED OPEN-LOOP RESPONSE

((5)) LOW POWER CONSUMPTION,, SMALL AREA

(6) LOW INPUT CAPACITANCE

(7) LOW NOISE OPERATION

NON-
NON-SAMPLING AND SAMPLING COMPARATORS

A. NON-SAMPLING COMPARATORS

Vi VO

Vi LATCH VO

STROBE

“1”
1 “0”
0

DON’T CARE
NON-
NON-SAMPLING AND SAMPLING COMPARATORS

B. SAMPLING COMPARATORS

Φ1
Φ1

Vi LATCH VO

Φ2 STROBE

① PROS ; OFFSET CAN BE CANCELLED

② CONS ; NEED CLOCKS AND COMPLICATED

③ A GOOD SOLUTION FOR HIGH-SPEED OPERATION

(~10 MHz ~1 GHz LEVEL)
AMPLIFIER ARCHITECTURE OF COMPARATORS

A. SINGLE-STAGE WITH HIGH GAIN ( OP-AMP STYLE )

VDD

Vi

Vo

Vbias
VSS
LOW POWER, BUT SLOW

(EX) ×1000
AMPLIFIER ARCHITECTURE OF COMPARATORS

B. MULTI-STAGE WITH AUTO-ZEROED ARCHITECTURES

×10 ×10 ×10

MEDIUM POWER, BUT FASTER

C. OPTIMIZATION OF POWER AND STAGES

Vo

t
POSITIVE FEEDBACK LATCH CIRCUITS

A. COMPARATOR LATCH
STROBE

COLUMN COLUMN
R Φ1 R
ROW ROW
ΔV
~ 100 mV

0 01 pF
0.01 0 01 pF
0.01

Φ2
CCOLUMN
0.5 ∼ 1 pF

Vo GAIN=1

TWO-STABLE POINTS
(Bi STABLE)

Vi
POSITIVE FEEDBACK LATCH CIRCUITS

B. OPERATION

5 V (“1”)
(1)

① DYNAMIC ERRORS
V1, V2 → MINIMUM LATCH INPUT VOLTAGES
~ 100 mV
V ERRORS
TO GET RIGHT ANSWERS !!

0 V ((“0”))
Φ1 on Φ2 on

② CALCULATE REGENERATION TIME

R R IN THE LATCH CIRCUITS
V1((0)) V2((0))
WHAT IS
S THE EQUATION
Q O OF
O (V
( 2(t)
( ) - V1(t))
( )) ?
C M1 M2 C
gm1 gm2
POSITIVE FEEDBACK LATCH CIRCUITS

C. VARIATIONS OF LATCH CIRCUITS

gm2 > gm1

① ②

VDD Φ LATCH
Φ Φ

gm1 gm1 gm2 gm2

S
SELF - BIASED
S
OFFSET AND FEEDTHROUGH (F.T.) CANCELLATION

A. ORIGIN

RANDOM
① VOS → BY DEVICE MISMATCH
SYSTEMATIC
② F.T. ERRORS FROM SWITCHES
Φ Φ
Cov VTH

VCK-
COL
VI C Δ VF.T. = (VTH - VCK-)
C
FOR SLOW TRANSITION CLOCKS

Φ
VCK+

VCK-
1/2Q 1/2Q Q = COXWL
VI C
1 Q IS MOVED TO C FOR FAST
2
TRANSITION CLOCKS
OFFSET AND FEEDTHROUGH (F.T.) CANCELLATION

B. Vos CANCELLATION

① USE CLOSED-LOOP OFFSET CANCELLATION WITH

SAMPLING CAPACITORS
Φ1
Φ1
Vos
VO
A
Φ2
VIN
(UNITY-GAIN STABLE !)

Vos Vos Vos

VO Vin VO
A A
((=VOS ) AVIN

(a) Φ1 ((b)) Φ2
SIMPLE, BUT F.T. ERRORS ARE NOT CANCELLED
OFFSET AND FEEDTHROUGH (F.T.) CANCELLATION

② OPEN-LOOP OFFSET CANCELLATION

Vos A1Vos

A1 A2

SLOW
((UNITY-GAIN STABLE REQUIRED))
OFFSET AND FEEDTHROUGH (F.T.) CANCELLATION

C. Vos AND F.T. SIMULTANEOUS CANCELLATION

(CORRELATED DOUBLE SAMPLING : CDS)

Φ1 Φ2 Φ3

Φ4
V1 A1 A2 A3
Φ4

Φ1 Φ2 Φ3
Φ1

Φ2 Vos1 SAMPLE

Φ3 Vos2 SAMPLE & VFT1 SAMPLE

Φ4 Vos2 SAMPLE & Ai VFT1 + VF2 SAMPLE

AMPLIFY
F.T. ERROR CORRECTION
OFFSET AND FEEDTHROUGH (F.T.) CANCELLATION

① BOTH OF Vos AND VF.T. CANCELLED

② 1/f NOISE REDUCED, BUT

③ WIDE-BAND kT/C NOISE DOUBLED

④ AMPLIFIERS CAN BE SATURATED DEPENDING ON
MAGNITUDES OF A1, A2, A3

⑤ OPEN-LOOP Vos SAMPLING CAN BE USED TO AVOID

UNITY-GAIN STABLE OPERATIONS OF OP AMPS
OFFSET AND FEEDTHROUGH (F.T.) CANCELLATION

D. AUXILIARY INPUT OFFSET & F.T. ERROR CANCELLATION

Φ1

Φ3 Vos1
A1

Vos2
A2
COFF COFF

Φ2
Φ1

Φ2 VOS AND VF.T.

SAMPLING IN COFF

Φ3
OFFSET AND FEEDTHROUGH (F.T.) CANCELLATION

A1VOS1 + A2VOS2
VOS(input-referred) =
A1(1+A2) PROVE IT !!

A1 A2

E. DESIGN TECHNIQUES FOR HIGH PERFORMANCE

(1) USE FULLY DIFFERENTIAL ARCHITECTURE

(2) USE AS MINIMUM STAGES AS POSSIBLE
WITH HIGH-SPEED
HIGH SPEED LATCH FOR
- GOOD CMRR, PSRR
- LOW TRANSIENT NOISE COUPLING FROM SUBSTRATE
- FIRST-ORDER CHARGE F.T. CANCELLATION