DIGITAL LOGIC AND

COMPUTER ORGANIZATION
Lecture 17: Pipelined Microprocessor (P1)
ELEC3010
ACKNOWLEGEMENT

I would like to express my special thanks to Professor Zhiru Zhang

School of Electrical and Computer Engineering, Cornell University
and Prof. Rudy Lauwereins, KU Leuven for sharing their teaching
materials.

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COVERED IN THIS COURSE
❑ Binary numbers and logic gates
❑ Boolean algebra and combinational logic
❑ Sequential logic and state machines
❑ Binary arithmetic
Digital logic
❑ Memories

❑ Instruction set architecture

❑ Processor organization Computer
❑ Caches and virtual memory
❑ Input/output Organization
❑ Advanced topics
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PROGRAMMABLE SINGLE-CYCLE PROCESSOR

❑ Instruction RAM holds the program to be run

▪ Here, each instruction is 16 bits (2 bytes)
❑ Decoder derives control word from the instruction
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 FORMING THE BRANCH TARGET ADDRESS

❑ A memory address points to a byte location (byte

addressable)
❑ If instructions are 2 bytes wide
▪ Instructions are located at even locations (0, 2, 4, ...)
▪ The PC must be incremented by 2 (PC+2)
▪ If we use the offset to refer to the number
of instructions not bytes) to jump, we will have larger jump distance
=> we must append a 0 to LSB
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 LITTLE ENDIAN VS. BIG ENDIAN
❑ Value = 0x1234 (2 bytes)

Memory Memory
Address Address

X+3 X+3
X+2 X+2
X+1 12 X+1 34

X 34 X 12

Little endian Big endian

(Lower byte at lower address) (Lower byte at higher address)

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 INSTRUCTION SET ARCHITECTURE (ISA)

❑ The ISA describes a set of instructions supported by a family of

machines
❑ The ISA specification informs hardware & software (compiler and
operating system) developers about
▪ Instruction formats
▪ Operation of each instruction
▪ Ways to form memory addresses
▪ Data formats
▪ Lots of other
❑ Examples: x86, ARM, MIPS, POWER, SPARC, RISC-V

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 STEPS IN INSTRUCTION EXECUTION

❑ Instruction Fetch (IF)

▪ Fetch instruction; Update PC ❑ Clock period is
❑ Instruction Decode (ID) limited by the
▪ Decode instruction; Read register file
longest path
❑ Execute (EX) ▪ Suppose each step
▪ Perform ALU operation takes 1ns, clock
❑ Memory (MEM) period is 5ns
▪ Perform memory operation
❑ Write Back (WB)
▪ Put result into register file

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MOTIVATION EXAMPLE

https://www.youtube.com/watch?v=DfGs2Y5WJ14
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PIPELINING: OVERLAPPED INSTRUCTIONS

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CAN YOU DO IT?

Assumptions: IF: 4ns; ID:3ns; EX: 6 ns; MEM:4 ns; WB: 3ns

What is the maximum clock frequency at which the processor can run?
How many clock cycles are needed to process one instruction?
How many instructions per second can the processor process?

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 CAN YOU DO IT?
❑Multi-cycle processor without pipelining

Assumptions: IF: 4ns; ID:3ns; EX: 6 ns; MEM:4 ns; WB: 3ns

What is the maximum clock frequency at which the processor can run?
How many clock cycles are needed to process one instruction?
How many instructions per second can the processor process?

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 CAN YOU DO IT?
❑Multi-cycle processor with pipelining

Assumptions: IF: 4ns; ID:3ns; EX: 6 ns; MEM:4 ns; WB: 3ns

What is the maximum clock frequency at which the processor can run?
How many clock cycles are needed to process one instruction?
How many instructions per second can the processor process?

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 PIPELINING: PERFORMANCE

❑ Faster clock frequency than single cycle processor

❑ Each instruction takes 5 cycles
❑ Average number of cycles per instruction (CPI)

❑ ~1 instruction completed every cycle (ideally)

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PIPELINING: BASIC IDEA
Registers

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PIPELINED MICROPROCESSOR

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INSTRUCTION FETCH STAGE (IF)

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INSTRUCTION DECODE STAGE (ID)

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EXECUTE STAGE (EX)

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MEMORY STAGE (MEM)

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WRITEBACK STAGE (WB)

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WRITEBACK STAGE (WB)

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ABSTRACT REPRESENTATION OF
PIPELINED PROCESSOR

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EXAMPLE INSTRUCTION SEQUENCE

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EXAMPLE INSTRUCTION SEQUENCE

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EXAMPLE INSTRUCTION SEQUENCE

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EXAMPLE INSTRUCTION SEQUENCE

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EXAMPLE INSTRUCTION SEQUENCE

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EXAMPLE INSTRUCTION SEQUENCE

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EXAMPLE INSTRUCTION SEQUENCE

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EXAMPLE INSTRUCTION SEQUENCE

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EXAMPLE INSTRUCTION SEQUENCE

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WHAT ABOUT THIS SEQUENCE?

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 DATA HAZARD
❑ Occurs when a register is read before the write back of a value to
that register

❑ What should happen

▪ The 1st instruction calculates a new value for R1
▪ The 2nd, 3rd, and 4th instructions use this new value
❑ What actually happens
▪ The 2nd, 3rd, and 4th instructions read the old value of R1
▪ The first instruction then writes the new value into R1
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SOLUTION 1: SW (COMPILER) INSERTS NOPS

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SOLUTION 2: HW STALLS THE PIPELINE

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 EXAMPLE: DATA HAZARDS
❑ Identify all data hazards in the following instruction
sequences by circling each source register that is read
before the updated value is written back

ADD R1, R2, R3

NOP
ADDI R3, R1, 1
SUB R3, R1, R2
OR R4, R3, R1

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 BEFORE NEXT CLASS

• Textbook: 7.5.3-7.5.5
• Next time:
More Pipelined Microprocessor

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