CECS 301 Computer Logic Design II © 2014 R. W.

Allison

Fall 2014 CECS 301 – 16‐bit RISC Processor

I. Application You are to complete the design of an 16-bit “Reduced Instruction Set Computing” (RISC)
processor that will fetch and execute a simple set of 16-bit machine instructions.

II. Instruction Set Architecture -- The 16 opcodes for 16-bit RISC Processor will be encoded in bits IR[15:9]
of the instruction register. IR[8:6] will have the binary code for the destination register. IR[5:3] and IR[2:0]
will have the binary codes for the source registers.
A. Memory Structure
1. 256x16 address space
2. Each memory location holds one 16-bit word.
B. Processor Register Set (available to user)
1. Eight 16-bit integer registers (R0, R1, R2, R3, R4, R5, R6 and R7).
2. 16-bit Program Counter (PC).
3. Flags Register (N, Z, C)
C. Data Types -- 16-bit single word signed integer (i.e. -32768 to +32767)
D. Addressing Modes
1. Immediate (16-bit integer, in a “trailing word”)
2. Register
3. Register indirect (load, store and jmp)
4. PC relative (je, jne and jc)
E. Instruction Opcodes/Formatting

Instructions Opcodes Instructions Opcodes

Name Opcodes Name Opcodes

add 111_0000 load 111_1000

double‐source
sub 111_0001 operands store 111_1001 load/store,
halt
cmp 111_0010 loadi 111_1010
halt 111_1011
mov 111_0011
shl 111_0100 je 111_1100
single-source
shr 111_0101 operands
jne 111_1101 jumps
inc 111_0110 jc 111_1110
dec 111_0111 jmp 111_1111

The basic format for the instructions is shown below:

15 9 8 6 5 3 2 0

opcode dest_reg src1_reg src2_reg

301 RISC Specifications – Page 1

CECS 301 Computer Logic Design II © 2014 R. W. Allison

E. Instruction Opcodes/Formatting (cont.)

1. Double‐source op’s: all these instructions are register based. No memory accesses are allowed.
15 9 8 6 5 3 2 0

opcode dest_reg src1_reg src2_reg

Triple operand operations (i.e. add / sub / cmp) are to be performed as:
dest_reg  src1_reg operation src2_reg
Example: sub r4, r2, r3 ; {N,Z,C, r4}  r2 ‐ r3 [Binary code: 1110001_100_010_011]
cmp r6, r7 ; {N,Z,C}  r6 ‐ r7 [Binary code: 1110010_000_110_111]

2. Single‐source op’s: all single-operand (i.e. single source operand) instructions are register based.
No memory accesses are allowed.
All single source operand operations (i.e. mov / shl / shr/ inc/ dec) are to be performed as:
dest_reg  operation src2_reg
Examples: dec r4 ; {N,Z,C, r4}  r4 – 1 [Binary code: 1110111_100_000_100]
shl r5, r1 ; {N,Z,C, r5}  r1 << 1 [Binary code: 1110100_101_000_001]
mov r6, r7 ; r6  r7 [Binary code: 1110011_110_000_111]

3. Load, Store, Halt format:

 For Load, the 16-bit word in a memory location (pointed at by register (R0..R7) specified by the
“src2_reg” field) is transferred into the register specified by the “dest_reg” field.
 For Store, the 16-bit register specified by the “src2_reg” field is transferred to a memory
location (pointed at by register (R0..R7) specified by the “dest_reg” field).
 For Load immediate, the 16-bit immediate value (located in the trailing word) is transferred into
the register specified by the “dest_reg” field. This is the only “32-bit instruction.”
 For Halt, the RISC processor will stop fetching instructions, going to a state that waits for reset.

4. Conditional jumps (relative), Jump (register indirect): the result of a “jump” type instruction is
to change the PC (if applicable). The “effective address” of the “conditional jump” instructions is
calculated by adding the 16-bit “sign-extension” of a 8-bit signed offset to the Program Counter.
15 9 8 7 0

opcode 0 8-bit signed offset

Example: jne -5 {if Z = 0, PC  PC + 1111111111111011} [Binary code: 1111101_0_11111011]

The “effective address” of the “unconditional” jump instruction is the contents of the src2_reg.
15 9 8 6 5 3 2 0

opcode src2_reg

Example: jmp r6 {PC  r6} [Binary code: 1111111_000_000_110]

F. Reset
In response to an external reset input, your processor should do the following:
(1) PC  00h (2) Flags (N,Z,C)  0002 (3) Goto the “fetch state”
301 RISC Specifications – Page 2