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ovan-2O23)

Digital Systems

ScSITespondi
TICYn)ng SEI-303
RGPV BE. IISemester, Examination, Dee. 2012
DIGITALCIRCUIT AND SYSTEM
...(v)
c capacity Vote (i) Attempt one question from cach Unit.
e R> C. (ii) All questions carry equal marks.
which can Unit-1
L (a) Convert the following codes as directed
() (785.B2)16 =()o (ü) (1011011.1101),-Os
Eb and (ü) (110101.101101), =)gray (iv) (751.231), (O6
No (See Unit-, Page 29, Prob.21)
movement (b) Minimize the following function using Quine and McCluskey method.
the other F(a, b, c, d) = E(0, 2, 7, 9, 10, 14) + E, (1, 8)
as trading Or
. (a) Minimize the following function using Boolean algebra
f, = ABCD+ BC +AD +C(A + BDC
f; = (BCD + A) B + (AC + BC) D.
(See Uait-, Page 44, Prob.27)
(b) Minimize the following function using Karnaugh map method.
F(a, b, c, d) = E(1, 3, 7, 10, 12, 14) + E (0, 9)
(See Unit-I, Page 60, Prob.42)
Unit-II
3, (a) Design a full adder using minimum logic gates and also discuss the
working of parallel adder. (See Unit-II, Page 81, Q.19)
(b) Discuss the working of look ahead carry generator.
(See Unit-II, Page 83, Q.22)
Or
a full subtractor using minimum logic gates. Also design the
. (a) Design (See Unit-II, Page 78, Q.15)
circuit using all NAND gates. gates. (See Unit-II, Page 8s, O.24)
logc
(b) Design a BCD adder using Unit-III
circuit diagram cxplain the working of astable
S. (a) With the help of (See Unit-IV, Page 206, ).38)
multivibrator.
CMOS logic and explain its workino
using
(b) Design a NAND gate (See Unit-IV, Page 232, Q.64)

ofR.GPV, itis not included in syllabus


to new
revised syllabus
according
1
Note :
Now, 10. 9, 8.
7.
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6.
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ding RGPV (b) (a) (b) (a) (b) (a)
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DIGITALCIRCUITAND SYSTEM counter gray counter I1, TTL
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Examination,
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Schmit
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ory maximum Astable
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Page Page Page Page Page Systems
Digital
SYSTEM ? Page Page Page Page Karmaugh56,
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the uses 133, 209, 200, 206, 84, Prob.34)
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