Sir Syed CASE Institute of Technology, Islamabad

EE2401 Digital Logic Design

Lab No. 7

Name of Student: Roll No. :

Date of Experiment: Report submitted on:

Marks obtained: Instructor’s Signature:

Instructor: Engr Safdar Munir

 Designing of Half Adder & Full Adder
1. Objectives
Having completed this experiment you would have learnt

1. How to construct the basic binary adder, i.e. Half-Adder circuit using basic logic gates
2. How to use to Half-Adders to construct a Full-Adder circuit
3. How to use multiple Full-Adders to implement n-bit adder circuit

2. Basic Information

2.1 Binary Addition

To build a binary adder of any size it is sufficient to build a unit, which can add two single bits.
Such a circuit is not very complex as there are only three calculations that needs to be performed,
i.e.
0+0=0
0+1=1
1 + 1 = 10

In the third case we encounter a slight complication: A single bit of output does not suffice to
represent the sum of 1 and 1, and we must "carry" a 1 to the next place. A 1-bit adder, therefore,
must accept two bits of input (the bits to be added) and generate two bits of output. These two
bits can be designated the SUM bit and the CARRY OUT bit.

2.2 Half Adder Circuit

Half Adder is a combinational logic circuit that generates the sum of two single-bit binary
numbers. The logic circuit has two inputs A & B and two outputs i.e. Sum & Carry abbreviated
as SHA & CHA respectively, whose relationship does Table 2.1 describe. The functionality of this
truth table can be described by the following two Boolean equations for Sum and Carry,

SHA = xy + x y
CHA = x y
INPUTS OUTPUTS
A B SHA CHA
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
Table 2.1
The implementation of these Boolean functions is shown in Fig 2.1. This Half-Adder circuit,
though very basic and simple, is the first stage in the design of any n-bit adder circuit. Fig 2.2
shows the block diagram of a 3-bit adder circuit where x2x1x0 represents one 3-bit number and
y2y1y0 represents the other 3-bit number. There are two outputs of this adder, i.e. a 3-bit sum
z2z1z0 and a carry bit Cout.

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 Fig 2.1

Fig 2.2
2.3 Full Adder Circuit

As can be seen from the operation of Half-Adder, even the addition of two single-bit numbers
may generate a carry. This implies that the circuit, which is going to perform addition on the next
higher bits, must take into account the carry from the previous stage. Thus in order to built n-bit
adders, we require a modification in the Half-Adder circuit that can accept three inputs rather
than two, i.e. two bits to be added and the carry from the previous stage. Such a circuit is called a
Full-Adder. Table 2.2 shows the truth table of a Full-Adder. In this table, x and y represent the
two bits to be added and z is the carry from the previous stage. The Boolean expressions for the
two outputs, after algebraic simplification, are given below.
SFA = X  YZ
CFA = ( XY )Z + XY

Inputs Outputs
X Y Z SFA CFA
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
Table 2.2
Fig 2.3 shows an implementation of these Boolean functions. Especially note that how two Half-
Adders are used to implement a Full-Adder.

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 Fig 2.3
2.4 N-bit Adder

With the ability to design a full-adder, now one can construct adder circuits for adding two
numbers of any sizes, e.g. 4-bit adder (which adds two 4-bit numbers), 8-bit adder and so on.
Fig 2.4 shows the block diagram of a 3-bit adder. Specifically, the figure shows first two stages
of the design, i.e. a half-adder to add the least significant bits, cascaded to a full-adder for the
addition of next significant bits. This part of the circuit is shown fully expanded in Fig 2.5 where
this cascaded relationship can be seen more clearly at the gate level.

Thus by cascading required number of full-adders with a half-adder for least significant bits, it is
quite straightforward to construct adder for any number of bits.

Fig 2.4

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 Fig 2.5

3. Experimental Work
This experiment consists of three parts. In the first part, you will use basic gates to implement a
half-adder circuit. In the next part, you will construct a full-adder by combining two half-adders.
Finally in the third part of this experiment, you will cascade a half-adder with a full-adder to
implement a 2-bit adder circuit.

Material required
a) Logic Trainer
b) Multimeter
c) Logic ICs

74LS08 (AND Gate)

7LLS32 (OR Gate)
74LS86 (XOR Gate)

d) Connecting wires, etc.

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 Fig 3.1
3.2 Procedure

1. Connect the Logic Trainer to 220V AC power supply.

2. Turn On the trainer and verify its DC voltage, it should be +5 volts exactly.
3. Install the IC 7408 & 7486 on the trainer’s breadboard.
4. Connect the +VCC (pin # 14) and Ground (pin # 7) pins of the IC to +5V and Ground
supply of the trainer board.
5. Make the appropriate circuit connections as shown in Fig 2.1 for a Half-Adder. Use the
trainer’s logic switches to provide “0” and “1” at the input and use the trainer’s LEDs to
display the outputs. Note that there are more than one gates in each IC chip, so you can
use any one of these gates to make your connections for the pin numbers corresponding
to each gate in that particular chip
6. Apply inputs to the circuit and record corresponding values of outputs in Table 3.1.
7. Now without disconnecting the previous circuit, make another half-adder circuit and
connect the two half adders to implement the functionality of a full-adder as shown in Fig
2.3. Record your observations in Table 3.2.
8. Again without disconnecting the full-adder circuit, make another half-adder circuit and
connect it with the previous full-adder to implement a 2-bit adder. Test this 2-bit adder
for the combination of input numbers listed in Table 3.3 and record your results in the
truth table.

3.3 Experimental Results

Inputs Outputs
SHA = x y + x y CHA = x y
X Y Actual Observed Actual Observed
0 0
0 1
1 0
1 1
Table 3.1
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 Inputs Outputs
SFA CFA
X y z Actual Observed Actual Observed
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Table 3.2

Inputs Outputs

X1 X0 Y1 Y0 Z1 Z0 Cout

1 1 1 0
1 1 1 1
0 1 0 1
0 1 1 1
Table 3.3

4. In case of Trouble
 Check the power supply for correct voltage.
 Check the Vcc (pin # 14) and Ground (pin # 7) connections of the IC under test.
 Check all the wire connections and remove any possible breaks.
 Check the IC under test for its proper working according to its truth table. To do this use
Multimeter to measure voltage levels at the inputs and outputs of each gate in that chip.

Digital Logic Design Lab (EE-2401) 7

 Lab 7 Evaluation Sheet

Name: Roll No:

Neat Wiring (3)

Task Completion (6)

Trouble Shooting (3)

Understanding (12)

Teamwork (6)

Total: /30

Digital Logic Design Lab (EE-2401) 8