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-- Nombre: Juan carlos tejada M

-- Documento: 10767388

-- Fecha: 19022023

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library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity Simulacion is

--

end Simulacion;

architecture Behavioral of Simulacion is

component Compuerta_AND

port ( A : in STD_LOGIC;

B : in STD_LOGIC;

outC : in STD_LOGIC

);

end component;

-- Señales de las entradas

signal A,B: STD_LOGIC:= '0';

-- Señales de salidas

signal C : STD_LOGIC;
begin

UO: Compuerta_AND Port map (

A => entrada1,

B => entrada2,

outC=> salida1

);

process begin

--- Estímulos de la simulación wait for 100 ns;

wait for 100 ns;

A <= '0';

B <= '0';

wait for 100 ns;

A <= '0';

B <= '1';

wait for 100 ns;

A <= '1';

B <= '0';

wait for 100 ns;

A <= '1';

B <= '1';

wait;

end process;
end Behavioral;

--------------------------------------------------------------------------------

-- Nombre: Juan carlos tejada M

-- Documento: 10767388

-- Fecha: 19022023

--------------------------------------------------------------------------------

library IEEE;

use IEEE.std_logic_1164.all;

use IEEE.numeric_std.all;

use IEEE.std_logic_unsigned.all;

entity Compuerta_AND is

Port ( A: in STD_LOGIC;

B: in STD_LOGIC;

outC: in STD_LOGIC);

end Compuerta_AND ;

architecture Behavioral of Compuerta_AND is

begin
end Behavioral;