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انظمة رقمية ٦ - معلومات - ست رند
انظمة رقمية ٦ - معلومات - ست رند
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Note:
• in the second version, the always statement repeatedly pauses for 10 time units, then it
complements clock, providing a clock generator having a cycle time of 20 time units.
Notes:
• The variables to which value is assigned (the left-hand side of the procedural
statements) must be declared as having reg data type.
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module decoder_2x4_df_beh (
output reg [0: 3] D,
input A, B, enable);
end
endmodule
Note: With nonblocking (< =) assignments, the order in which the statements assigning value to the
bits of D are listed does not affect the outcome.
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always @ (A or B or select)
// Alternative: always @ (A, B, select)
if (select == 1) m_out = A;
else m_out = B;
endmodule
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Notes on Example 2
The signal m_out in mux_2x1_beh must be of the reg data type, because it is assigned value by a
Verilog procedural assignment statement.
Contrary to the wire data type, whereby the target of an assignment may be continuously
monitored and updated, a reg data type is not necessarily monitored, and retains its value until a
new value (in simulation memory) is assigned.
The procedural assignment statements inside the always block are executed every time there is a
change in any of the variables listed in the sensitivity list after the @ symbol (in this example,
these variables are A, B and select). The statements execute if A, B, or select changes value.
The keyword or, instead of the logical OR operator “|”, is used between variables.
There is no semicolon (;) at the end of the always statement.
The conditional statement if-else provides a decision based upon the value of the select input.
The if statement can be written without the equality symbol:
if (select) m_out = A;
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Notes on Example 3
Signal m_out in mux_4x1_beh is declared to have type reg because it is assigned value by a
procedural statement. It will retain its value until it is explicitly changed by a procedural
statement.
The always statement, in this example, has a sequential block enclosed between the
keywords case and endcase.
The block is executed whenever any of the inputs listed after the @ symbol changes in
value.
The case statement is a multiway conditional branch construct.
Whenever in_0, in_1, in_2, in_3 or select change, the case expression (select) is evaluated
and its value compared, from top to bottom, with the values in the list of statements that
follow, the so-called case items.
The statement associated with the first case item that matches the case expression is
executed.
In the absence of a match, no statement is executed. (Alternatively, a default case item and
an associated case expression can be included in the list to ensure that a statement will
always be executed.) Since select is a two-bit number, it can be equal to 00, 01, 10, or 11.
The case items have an implied priority because the list is evaluated from top to bottom.
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//Note: Since Q is assigned value by a procedural statement, its type must be declared to be reg.
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Reset Signals
Digital hardware always has a reset signal.
It is strongly recommended that all models of sequential circuits
include a reset (or preset) signal; otherwise, the initial state of the
flip-flops of the sequential circuit cannot be determined.
A sequential circuit cannot be tested with HDL simulation unless an
initial state can be assigned with by an external input signal.
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State Equations
The behavior of a clocked sequential
circuit can be described algebraically
by means of state equations.
A state equation (also called a
transition equation) specifies the
next state as a function of the
present state and inputs.
Example: Write the state equations
of the sequential circuit that is shown
on the right.
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State Table
The time sequence of inputs, outputs, and flip-flop states can be enumerated
in a state table (sometimes called a transition table).
The state table for the circuit of the figure in slide 24 is shown in the table
below.
A(t + 1) = Ax + Bx
B(t + 1) = A’x
y(t) = (A + B)x’
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• For each present state, there are two possible next states and outputs, depending on the
value of the input. One form may be preferable to the other, depending on the application.
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